From cab5f656856a0a3e97bc9322fed274923d994b5f Mon Sep 17 00:00:00 2001 From: Tomasz Wlostowski Date: Fri, 18 Nov 2022 15:13:54 +0100 Subject: [PATCH] qa/pns: added test case for via drag walkaround --- qa/data/pcbnew/pns_regressions/tests.lst | 3 +- .../via_drag_walkaround1/pns.dump | 1310 +++++++++++++++++ .../via_drag_walkaround1/pns.kicad_pro | 695 +++++++++ .../via_drag_walkaround1/pns.log | 49 + .../via_drag_walkaround1/pns.settings | 29 + 5 files changed, 2085 insertions(+), 1 deletion(-) create mode 100644 qa/data/pcbnew/pns_regressions/via_drag_walkaround1/pns.dump create mode 100644 qa/data/pcbnew/pns_regressions/via_drag_walkaround1/pns.kicad_pro create mode 100644 qa/data/pcbnew/pns_regressions/via_drag_walkaround1/pns.log create mode 100644 qa/data/pcbnew/pns_regressions/via_drag_walkaround1/pns.settings diff --git a/qa/data/pcbnew/pns_regressions/tests.lst b/qa/data/pcbnew/pns_regressions/tests.lst index 676ec97b0a..9c48c06cd8 100644 --- a/qa/data/pcbnew/pns_regressions/tests.lst +++ b/qa/data/pcbnew/pns_regressions/tests.lst @@ -1,3 +1,4 @@ simple_shove1 simple_drag_shove1 -backspace1 \ No newline at end of file +backspace1 +via_drag_walkaround1 \ No newline at end of file diff --git a/qa/data/pcbnew/pns_regressions/via_drag_walkaround1/pns.dump b/qa/data/pcbnew/pns_regressions/via_drag_walkaround1/pns.dump new file mode 100644 index 0000000000..233118b844 --- /dev/null +++ b/qa/data/pcbnew/pns_regressions/via_drag_walkaround1/pns.dump @@ -0,0 +1,1310 @@ +(kicad_pcb (version 20221018) (generator pcbnew) + + (general + (thickness 1.462) + ) + + (paper "A4") + (layers + (0 "F.Cu" signal "Top.Cu") + (1 "In1.Cu" mixed "In1.Cu-GND") + (2 "In2.Cu" signal "In2.Cu-POWER") + (3 "In3.Cu" signal) + (4 "In4.Cu" signal) + (5 "In5.Cu" signal) + (6 "In6.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "T.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user "T.Paste") + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "T.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user "T.Mask") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "T.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user "T.Fab") + ) + + (setup + (stackup + (layer "F.SilkS" (type "Top Silk Screen")) + (layer "F.Paste" (type "Top Solder Paste")) + (layer "F.Mask" (type "Top Solder Mask") (thickness 0.015)) + (layer "F.Cu" (type "copper") (thickness 0.035)) + (layer "dielectric 1" (type "prepreg") (thickness 0.22) (material "FR4") (epsilon_r 3.9) (loss_tangent 0.02)) + (layer "In1.Cu" (type "copper") (thickness 0.017)) + (layer "dielectric 2" (type "core") (thickness 0.15) (material "FR4") (epsilon_r 3.9) (loss_tangent 0.02)) + (layer "In2.Cu" (type "copper") (thickness 0.017)) + (layer "dielectric 3" (type "prepreg") (thickness 0.15) (material "FR4") (epsilon_r 3.9) (loss_tangent 0.02)) + (layer "In3.Cu" (type "copper") (thickness 0.017)) + (layer "dielectric 4" (type "core") (thickness 0.22) (material "FR4") (epsilon_r 3.9) (loss_tangent 0.02)) + (layer "In4.Cu" (type "copper") (thickness 0.017)) + (layer "dielectric 5" (type "prepreg") (thickness 0.15) (material "FR4") (epsilon_r 3.9) (loss_tangent 0.02)) + (layer "In5.Cu" (type "copper") (thickness 0.017)) + (layer "dielectric 6" (type "prepreg") (thickness 0.15) (material "FR4") (epsilon_r 3.9) (loss_tangent 0.02)) + (layer "In6.Cu" (type "copper") (thickness 0.017)) + (layer "dielectric 7" (type "core") (thickness 0.22) (material "FR4") (epsilon_r 3.9) (loss_tangent 0.02)) + (layer "B.Cu" (type "copper") (thickness 0.035)) + (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.015)) + (layer "B.Paste" (type "Bottom Solder Paste")) + (layer "B.SilkS" (type "Bottom Silk Screen")) + (copper_finish "None") + (dielectric_constraints yes) + ) + (pad_to_mask_clearance 0) + (aux_axis_origin 40 125) + (pcbplotparams + (layerselection 0x00010fc_ffffffff) + (plot_on_all_layers_selection 0x0000000_00000000) + (disableapertmacros false) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 6) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (dxfpolygonmode true) + (dxfimperialunits true) + (dxfusepcbnewfont true) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (sketchpadsonfab false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + + (net 0 "") + (net 1 "Net-(U1-CAP_VDD)") + (net 2 "GND") + (net 3 "Net-(C2-Pad1)") + (net 4 "Net-(U1-PWDWN)") + (net 5 "unconnected-(U1-X2)") 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