From cb334be8c445723cb9fb61097135ac28f530cf81 Mon Sep 17 00:00:00 2001
From: Jon Evans <jon@craftyjon.com>
Date: Fri, 17 Feb 2023 19:55:52 -0500
Subject: [PATCH] PNS: Diff pairs can have different hole-to-hole size

Fixes https://gitlab.com/kicad/code/kicad/-/issues/13993


(cherry picked from commit f12f2b8420cb7ed0c2c79d91da5677872d65011b)
---
 pcbnew/router/pns_diff_pair_placer.cpp |  2 +-
 pcbnew/router/pns_kicad_iface.cpp      | 13 ++++++++++++-
 pcbnew/router/pns_sizes_settings.h     |  4 ++++
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/pcbnew/router/pns_diff_pair_placer.cpp b/pcbnew/router/pns_diff_pair_placer.cpp
index 2aa209fe44..f5515a6707 100644
--- a/pcbnew/router/pns_diff_pair_placer.cpp
+++ b/pcbnew/router/pns_diff_pair_placer.cpp
@@ -559,7 +559,7 @@ bool DIFF_PAIR_PLACER::FindDpPrimitivePair( NODE* aWorld, const VECTOR2I& aP, IT
 int DIFF_PAIR_PLACER::viaGap() const
 {
     return std::max( m_sizes.DiffPairViaGap(),
-                     m_sizes.GetHoleToHole() + m_sizes.ViaDrill() - m_sizes.ViaDiameter() );
+                     m_sizes.GetDiffPairHoleToHole() + m_sizes.ViaDrill() - m_sizes.ViaDiameter() );
 }
 
 
diff --git a/pcbnew/router/pns_kicad_iface.cpp b/pcbnew/router/pns_kicad_iface.cpp
index 4ddb79ef05..38a19a95d2 100644
--- a/pcbnew/router/pns_kicad_iface.cpp
+++ b/pcbnew/router/pns_kicad_iface.cpp
@@ -736,10 +736,13 @@ bool PNS_KICAD_IFACE_BASE::ImportSizes( PNS::SIZES_SETTINGS& aSizes, PNS::ITEM*
     aSizes.SetDiffPairViaGapSameAsTraceGap( false );
 
     int      holeToHoleMin = bds.m_HoleToHoleMin;
-    PNS::VIA dummyVia;
+    PNS::VIA dummyVia, coupledVia;
 
     if( aStartItem )
+    {
         dummyVia.SetNet( aStartItem->Net() );
+        coupledVia.SetNet( m_ruleResolver->DpCoupledNet( aStartItem->Net() ) );
+    }
 
     if( m_ruleResolver->QueryConstraint( PNS::CONSTRAINT_TYPE::CT_HOLE_TO_HOLE, &dummyVia,
                                          &dummyVia, UNDEFINED_LAYER, &constraint ) )
@@ -749,6 +752,14 @@ bool PNS_KICAD_IFACE_BASE::ImportSizes( PNS::SIZES_SETTINGS& aSizes, PNS::ITEM*
 
     aSizes.SetHoleToHole( holeToHoleMin );
 
+    if( m_ruleResolver->QueryConstraint( PNS::CONSTRAINT_TYPE::CT_HOLE_TO_HOLE, &dummyVia,
+                                         &coupledVia, UNDEFINED_LAYER, &constraint ) )
+    {
+        holeToHoleMin = constraint.m_Value.Min();
+    }
+
+    aSizes.SetDiffPairHoleToHole( holeToHoleMin );
+
     return true;
 }
 
diff --git a/pcbnew/router/pns_sizes_settings.h b/pcbnew/router/pns_sizes_settings.h
index f625008c17..b83b5e8914 100644
--- a/pcbnew/router/pns_sizes_settings.h
+++ b/pcbnew/router/pns_sizes_settings.h
@@ -122,6 +122,9 @@ public:
     wxString GetDiffPairGapSource() const { return m_diffPairGapSource; }
     void SetDiffPairGapSource( const wxString& aSource ) { m_diffPairGapSource = aSource; }
 
+    void SetDiffPairHoleToHole( int aHoleToHole ) { m_diffPairHoleToHole = aHoleToHole; }
+    int GetDiffPairHoleToHole() const { return m_diffPairHoleToHole; }
+
 private:
     int     m_clearance;
     int     m_minClearance;
@@ -138,6 +141,7 @@ private:
     bool    m_diffPairViaGapSameAsTraceGap;
 
     int     m_holeToHole;
+    int     m_diffPairHoleToHole;
 
     std::map<int, int> m_layerPairs;