From cc7899738677fa1928ff4690e49f2caff9eeb00a Mon Sep 17 00:00:00 2001 From: Jeff Young Date: Mon, 1 Aug 2022 21:46:58 +0100 Subject: [PATCH] Add annular ring test and fix footprint/pad mismatch in other test. --- qa/data/pcbnew/issue12109.kicad_pcb | 220 +++++++++ qa/data/pcbnew/issue12109.kicad_pro | 433 ++++++++++++++++++ qa/data/pcbnew/issue7567.kicad_pcb | 4 - .../pcbnew/drc/test_drc_regressions.cpp | 25 +- 4 files changed, 666 insertions(+), 16 deletions(-) create mode 100644 qa/data/pcbnew/issue12109.kicad_pcb create mode 100644 qa/data/pcbnew/issue12109.kicad_pro diff --git a/qa/data/pcbnew/issue12109.kicad_pcb b/qa/data/pcbnew/issue12109.kicad_pcb new file mode 100644 index 0000000000..ad8e6c5870 --- /dev/null +++ b/qa/data/pcbnew/issue12109.kicad_pcb @@ -0,0 +1,220 @@ +(kicad_pcb (version 20211014) (generator pcbnew) + + (general + (thickness 1.6) + ) + + (paper "A4") + (layers + (0 "F.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + (50 "User.1" user) + (51 "User.2" user) + (52 "User.3" user) + (53 "User.4" user) + (54 "User.5" user) + (55 "User.6" user) + (56 "User.7" user) + (57 "User.8" user) + (58 "User.9" user) + ) + + (setup + (stackup + (layer "F.SilkS" (type "Top Silk Screen")) + (layer "F.Paste" (type "Top Solder Paste")) + (layer "F.Mask" (type "Top Solder Mask") (thickness 0.01)) + (layer "F.Cu" (type "copper") (thickness 0.035)) + (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02)) + (layer "B.Cu" (type "copper") (thickness 0.035)) + (layer "B.Mask" (type "Bottom Solder Mask") (thickness 0.01)) + (layer "B.Paste" (type "Bottom Solder Paste")) + (layer "B.SilkS" (type "Bottom Silk Screen")) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (pcbplotparams + (layerselection 0x00010fc_ffffffff) + (disableapertmacros false) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (svguseinch false) + (svgprecision 6) + (excludeedgelayer true) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (dxfpolygonmode true) + (dxfimperialunits true) + (dxfusepcbnewfont true) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (sketchpadsonfab false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + + (net 0 "") + (net 1 "Net-(J1-Pad1)") + (net 2 "Net-(J1-Pad2)") + (net 3 "Net-(J1-Pad3)") + (net 4 "Net-(J1-Pad4)") + (net 5 "Net-(J1-Pad5)") + (net 6 "Net-(J1-Pad6)") + + (footprint "Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical" (layer "F.Cu") + (tedit 59FED5CC) (tstamp 0f56ae0b-68c8-4d94-8ec9-a9bcb40c62ee) + (at 140.58 91.39) + (descr "Through hole straight pin header, 1x06, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x06 2.54mm single row") + (property "Sheetfile" "annular_ring_bug.kicad_sch") + (property "Sheetname" "") + (path "/8711afef-c83c-449a-ad23-0f17967c69a5") + (attr through_hole) + (fp_text reference "J2" (at 0 -2.33) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 14b21551-3464-4b95-ae3d-e7bed92cd58b) + ) + (fp_text value "Conn_01x06_Male" (at 0 15.03) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp a5b1873d-57e8-4c3a-b713-a7907fac9618) + ) + (fp_text user "${REFERENCE}" (at 0 6.35 90) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 399583cd-46de-43c1-8e60-9337ce6a73b5) + ) + (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer "F.SilkS") (width 0.12) (tstamp ac6f62f2-4beb-4d2e-9739-20b1c62c165e)) + (fp_line (start -1.33 14.03) (end 1.33 14.03) (layer "F.SilkS") (width 0.12) (tstamp da9b862a-d745-479d-a48b-cdc7f25a1630)) + (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer "F.SilkS") (width 0.12) (tstamp dbbca32b-4585-497f-8101-98c5bea4aca3)) + (fp_line (start -1.33 0) (end -1.33 -1.33) (layer "F.SilkS") (width 0.12) (tstamp e888874e-4ebf-4c45-a063-ad0a451852fc)) + (fp_line (start -1.33 1.27) (end -1.33 14.03) (layer "F.SilkS") (width 0.12) (tstamp f73b41ff-6df9-4e26-858c-b37237abcbe3)) + (fp_line (start 1.33 1.27) (end 1.33 14.03) (layer "F.SilkS") (width 0.12) (tstamp f8c82a02-6957-4766-ac2f-83d16be22fa8)) + (fp_line (start -1.8 14.5) (end 1.8 14.5) (layer "F.CrtYd") (width 0.05) (tstamp 00fa49b3-42a5-4940-9ba6-d0fd8cf12719)) + (fp_line (start -1.8 -1.8) (end -1.8 14.5) (layer "F.CrtYd") (width 0.05) (tstamp 2828609f-bc3c-45e9-a1eb-d4c4a97e7149)) + (fp_line (start 1.8 14.5) (end 1.8 -1.8) (layer "F.CrtYd") (width 0.05) (tstamp 6d6061d6-5d2f-44a1-9b1a-917ecedabd1d)) + (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer "F.CrtYd") (width 0.05) (tstamp 6eb31222-59a3-4034-930e-8f440bbc9ba0)) + (fp_line (start -1.27 13.97) (end -1.27 -0.635) (layer "F.Fab") (width 0.1) (tstamp 0fd1a0ad-ef65-4c4b-90ba-99bdb3fce65f)) + (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer "F.Fab") (width 0.1) (tstamp 40226fcd-0c6e-400b-96a7-b6362410613e)) + (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer "F.Fab") (width 0.1) (tstamp 4edba808-0ad0-49bf-8cb8-109ba13f78cd)) + (fp_line (start 1.27 13.97) (end -1.27 13.97) (layer "F.Fab") (width 0.1) (tstamp 73a54626-2028-43ef-8e82-a57f11967467)) + (fp_line (start 1.27 -1.27) (end 1.27 13.97) (layer "F.Fab") (width 0.1) (tstamp b7abe692-18c1-4b9c-8ca7-a0cacf235b37)) + (pad "1" thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 1 "Net-(J1-Pad1)") (pinfunction "Pin_1") (pintype "passive") (tstamp 5f2c1d16-8cd6-470f-8d8e-892801aec651)) + (pad "2" thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 2 "Net-(J1-Pad2)") (pinfunction "Pin_2") (pintype "passive") (tstamp 6a7d7d63-5112-4b7a-af4e-bab8551019bd)) + (pad "3" thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 3 "Net-(J1-Pad3)") (pinfunction "Pin_3") (pintype "passive") (tstamp 1c808bc2-d9fc-4d67-9cdd-c0052d39c987)) + (pad "4" thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 4 "Net-(J1-Pad4)") (pinfunction "Pin_4") (pintype "passive") (tstamp bd5d0ea9-d28c-44d1-9757-01dc2d24d097)) + (pad "5" thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 5 "Net-(J1-Pad5)") (pinfunction "Pin_5") (pintype "passive") (tstamp 7576a950-3a8f-4963-8e55-d6c523bb9dfd)) + (pad "6" thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 6 "Net-(J1-Pad6)") (pinfunction "Pin_6") (pintype "passive") (tstamp ccd42eda-bc51-4129-90af-f291fcf547b9)) + (model "${KICAD6_3DMODEL_DIR}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x06_P2.54mm_Vertical.wrl" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (footprint "Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical" (layer "F.Cu") + (tedit 59FED5CC) (tstamp 38c7189a-ba8d-4299-b230-48e6f64519bc) + (at 145.23 91.39) + (descr "Through hole straight pin header, 1x06, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x06 2.54mm single row") + (property "Sheetfile" "annular_ring_bug.kicad_sch") + (property "Sheetname" "") + (path "/b94d4009-e38f-4e78-9803-73c771efeaf3") + (attr through_hole) + (fp_text reference "J1" (at 0 -2.33) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 1d985ba7-e275-4145-8a0a-171b3237f8aa) + ) + (fp_text value "Conn_01x06_Male" (at 0 15.03) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 320ccb66-799b-44ce-97f1-996f35314629) + ) + (fp_text user "${REFERENCE}" (at 0 6.35 90) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp ac517229-abcc-4765-b855-6bc0eff44c22) + ) + (fp_line (start -1.33 1.27) (end -1.33 14.03) (layer "F.SilkS") (width 0.12) (tstamp 51ad516c-a5f1-4861-899f-7543e52cb1eb)) + (fp_line (start -1.33 14.03) (end 1.33 14.03) (layer "F.SilkS") (width 0.12) (tstamp 5d4c2df8-49d9-4c3a-b596-e104acb2622b)) + (fp_line (start 1.33 1.27) (end 1.33 14.03) (layer "F.SilkS") (width 0.12) (tstamp 62e5f7cc-f263-4368-aeb9-22c057e3dbaa)) + (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer "F.SilkS") (width 0.12) (tstamp 66108beb-b718-4b82-8605-1cc9a0d85aee)) + (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer "F.SilkS") (width 0.12) (tstamp f3394edb-f0d4-467f-ba04-752914c9c841)) + (fp_line (start -1.33 0) (end -1.33 -1.33) (layer "F.SilkS") (width 0.12) (tstamp f6674fc6-2577-4da0-ad35-c3a63b9532d5)) + (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer "F.CrtYd") (width 0.05) (tstamp 117655f2-48a7-4a07-b47d-202a2c2bc50a)) + (fp_line (start -1.8 14.5) (end 1.8 14.5) (layer "F.CrtYd") (width 0.05) (tstamp 5cb273cd-aeea-4812-a4a5-2bae856f44fa)) + (fp_line (start 1.8 14.5) (end 1.8 -1.8) (layer "F.CrtYd") (width 0.05) (tstamp 71d16bdf-0313-40ed-8e2d-595c580be6f0)) + (fp_line (start -1.8 -1.8) (end -1.8 14.5) (layer "F.CrtYd") (width 0.05) (tstamp 78702955-20fa-4066-8975-c8d45fc66e13)) + (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer "F.Fab") (width 0.1) (tstamp 366c46e5-a7af-4a31-bf82-220fbad56002)) + (fp_line (start -1.27 13.97) (end -1.27 -0.635) (layer "F.Fab") (width 0.1) (tstamp 36ad3867-64c6-4789-9df4-7c95faf7c87a)) + (fp_line (start 1.27 13.97) (end -1.27 13.97) (layer "F.Fab") (width 0.1) (tstamp 521acfdd-22a6-43dd-9213-cd1bc0c4a76a)) + (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer "F.Fab") (width 0.1) (tstamp 9ae5a357-49d2-45e9-a698-55470fef91be)) + (fp_line (start 1.27 -1.27) (end 1.27 13.97) (layer "F.Fab") (width 0.1) (tstamp f06a4aa8-aac5-457d-8423-66605e6070ba)) + (pad "1" thru_hole rect (at 0 0) (size 1.1 1.1) (drill 1) (layers *.Cu *.Mask) + (net 1 "Net-(J1-Pad1)") (pinfunction "Pin_1") (pintype "passive") (tstamp 5c469eb6-9b81-491f-bd33-d81fc5db2ebd)) + (pad "2" thru_hole circle (at 0 2.54) (size 1.1 1.1) (drill 1) (layers *.Cu *.Mask) + (net 2 "Net-(J1-Pad2)") (pinfunction "Pin_2") (pintype "passive") (tstamp 55c8d0fb-5866-4d93-9f5b-5e208178fbc0)) + (pad "3" thru_hole oval (at 0 5.08) (size 1.1 1.1) (drill 1) (layers *.Cu *.Mask) + (net 3 "Net-(J1-Pad3)") (pinfunction "Pin_3") (pintype "passive") (tstamp b5a7e57b-9375-4dcc-8aaa-843bb8ad79ef)) + (pad "4" thru_hole oval (at 0 7.62) (size 1.1 1.1) (drill 1) (layers *.Cu *.Mask) + (net 4 "Net-(J1-Pad4)") (pinfunction "Pin_4") (pintype "passive") (tstamp 7a4cf30b-7a58-4751-9358-1241c6201e8e)) + (pad "5" thru_hole oval (at 0 10.16) (size 1.1 1.1) (drill 1) (layers *.Cu *.Mask) + (net 5 "Net-(J1-Pad5)") (pinfunction "Pin_5") (pintype "passive") (tstamp 6cd5f354-5ccb-4b02-a452-cccc06d04362)) + (pad "6" thru_hole oval (at 0 12.7) (size 1.1 1.1) (drill 1) (layers *.Cu *.Mask) + (net 6 "Net-(J1-Pad6)") (pinfunction "Pin_6") (pintype "passive") (tstamp dff37c24-3a7a-44d4-a983-ecd21b7ea0a9)) + (model "${KICAD6_3DMODEL_DIR}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x06_P2.54mm_Vertical.wrl" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (gr_rect (start 137.74 87.91) (end 148.8 107.41) (layer "Edge.Cuts") (width 0.1) (fill none) (tstamp e928660c-538e-4fe5-9f61-abb7e9d73529)) + + (segment (start 140.58 91.39) (end 145.23 91.39) (width 0.25) (layer "F.Cu") (net 1) (tstamp 9f3d6ee9-2b66-443f-9d58-e7d83869ee41)) + (segment (start 140.58 93.93) (end 145.23 93.93) (width 0.25) (layer "F.Cu") (net 2) (tstamp d22f2765-db6b-434b-82db-875311bb207c)) + (segment (start 140.58 96.47) (end 145.23 96.47) (width 0.25) (layer "F.Cu") (net 3) (tstamp 1e70cc2b-eae0-4852-b1a6-e855a29891d2)) + (segment (start 145.23 96.47) (end 147.13 96.47) (width 0.25) (layer "F.Cu") (net 3) (tstamp b10e1fbd-c216-4d0a-b27e-a641d45dbf14)) + (segment (start 147.13 96.47) (end 147.92 95.68) (width 0.25) (layer "F.Cu") (net 3) (tstamp fd7a8e6e-6a9f-48ca-88d2-30191bf390a7)) + (via (at 147.92 95.68) (size 0.5) (drill 0.4) (layers "F.Cu" "B.Cu") (free) (net 3) (tstamp 56a3c0c1-a962-4ec3-b482-addc770b1808)) + (segment (start 140.58 99.01) (end 145.23 99.01) (width 0.25) (layer "F.Cu") (net 4) (tstamp 8b6a8608-07ec-48c1-bd60-e3097d9e9264)) + (segment (start 140.58 101.55) (end 145.23 101.55) (width 0.25) (layer "F.Cu") (net 5) (tstamp 23577d82-d28b-4dd6-b6dc-be3e68ae1eda)) + (segment (start 140.58 104.09) (end 145.23 104.09) (width 0.25) (layer "F.Cu") (net 6) (tstamp d84a7a50-883f-4f54-b520-ca2a64f38a10)) + +) diff --git a/qa/data/pcbnew/issue12109.kicad_pro b/qa/data/pcbnew/issue12109.kicad_pro new file mode 100644 index 0000000000..3d0a24969f --- /dev/null +++ b/qa/data/pcbnew/issue12109.kicad_pro @@ -0,0 +1,433 @@ +{ + "board": { + "design_settings": { + "defaults": { + "board_outline_line_width": 0.09999999999999999, + "copper_line_width": 0.19999999999999998, + "copper_text_italic": false, + "copper_text_size_h": 1.5, + "copper_text_size_v": 1.5, + "copper_text_thickness": 0.3, + "copper_text_upright": false, + "courtyard_line_width": 0.049999999999999996, + "dimension_precision": 4, + "dimension_units": 3, + "dimensions": { + "arrow_length": 1270000, + "extension_offset": 500000, + "keep_text_aligned": true, + "suppress_zeroes": false, + "text_position": 0, + "units_format": 1 + }, + "fab_line_width": 0.09999999999999999, + "fab_text_italic": false, + "fab_text_size_h": 1.0, + "fab_text_size_v": 1.0, + "fab_text_thickness": 0.15, + "fab_text_upright": false, + "other_line_width": 0.15, + "other_text_italic": false, + "other_text_size_h": 1.0, + "other_text_size_v": 1.0, + "other_text_thickness": 0.15, + "other_text_upright": false, + "pads": { + "drill": 1.0, + "height": 1.1, + "width": 1.1 + }, + "silk_line_width": 0.15, + "silk_text_italic": false, + "silk_text_size_h": 1.0, + "silk_text_size_v": 1.0, + "silk_text_thickness": 0.15, + "silk_text_upright": false, + "zones": { + "45_degree_only": false, + "min_clearance": 0.508 + } + }, + "diff_pair_dimensions": [ + { + "gap": 0.0, + "via_gap": 0.0, + "width": 0.0 + } + ], + "drc_exclusions": [], + "meta": { + "version": 2 + }, + "rule_severities": { + "annular_width": "error", + "clearance": "error", + "copper_edge_clearance": "error", + "courtyards_overlap": "error", + "diff_pair_gap_out_of_range": "error", + "diff_pair_uncoupled_length_too_long": "error", + "drill_out_of_range": "error", + "duplicate_footprints": "warning", + "extra_footprint": "warning", + "footprint_type_mismatch": "error", + "hole_clearance": "error", + "hole_near_hole": "error", + "invalid_outline": "error", + "item_on_disabled_layer": "error", + "items_not_allowed": "error", + "length_out_of_range": "error", + "malformed_courtyard": "error", + "microvia_drill_out_of_range": "error", + "missing_courtyard": "ignore", + "missing_footprint": "warning", + "net_conflict": "warning", + "npth_inside_courtyard": "ignore", + "padstack": "error", + "pth_inside_courtyard": "ignore", + "shorting_items": "error", + "silk_over_copper": "warning", + "silk_overlap": "warning", + "skew_out_of_range": "error", + "through_hole_pad_without_hole": "error", + "too_many_vias": "error", + "track_dangling": "warning", + "track_width": "error", + "tracks_crossing": "error", + "unconnected_items": "error", + "unresolved_variable": "error", + "via_dangling": "warning", + "zone_has_empty_net": "error", + "zones_intersect": "error" + }, + "rules": { + "allow_blind_buried_vias": false, + "allow_microvias": false, + "max_error": 0.005, + "min_clearance": 0.19999999999999998, + "min_copper_edge_clearance": 0.5, + "min_hole_clearance": 0.25, + "min_hole_to_hole": 0.25, + "min_microvia_diameter": 0.19999999999999998, + "min_microvia_drill": 0.09999999999999999, + "min_silk_clearance": 0.0, + "min_through_hole_diameter": 0.3, + "min_track_width": 0.19999999999999998, + "min_via_annular_width": 0.19999999999999998, + "min_via_diameter": 0.39999999999999997, + "solder_mask_clearance": 0.0, + "solder_mask_min_width": 0.0, + "use_height_for_length_calcs": true + }, + "track_widths": [ + 0.0 + ], + "via_dimensions": [ + { + "diameter": 0.0, + "drill": 0.0 + } + ], + "zones_allow_external_fillets": true, + "zones_use_no_outline": true + }, + "layer_presets": [] + }, + "boards": [], + "cvpcb": { + "equivalence_files": [] + }, + "erc": { + "erc_exclusions": [], + "meta": { + "version": 0 + }, + "pin_map": [ + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 2, + 0, + 1, + 0, + 0, + 1, + 0, + 2, + 2, + 2, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 1, + 0, + 1, + 2 + ], + [ + 0, + 1, + 0, + 0, + 0, + 0, + 1, + 1, + 2, + 1, + 1, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2 + ], + [ + 1, + 1, + 1, + 1, + 1, + 0, + 1, + 1, + 1, + 1, + 1, + 2 + ], + [ + 0, + 0, + 0, + 1, + 0, + 0, + 1, + 0, + 0, + 0, + 0, + 2 + ], + [ + 0, + 2, + 1, + 2, + 0, + 0, + 1, + 0, + 2, + 2, + 2, + 2 + ], + [ + 0, + 2, + 0, + 1, + 0, + 0, + 1, + 0, + 2, + 0, + 0, + 2 + ], + [ + 0, + 2, + 1, + 1, + 0, + 0, + 1, + 0, + 2, + 0, + 0, + 2 + ], + [ + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2, + 2 + ] + ], + "rule_severities": { + "bus_definition_conflict": "error", + "bus_entry_needed": "error", + "bus_label_syntax": "error", + "bus_to_bus_conflict": "error", + "bus_to_net_conflict": "error", + "different_unit_footprint": "error", + "different_unit_net": "error", + "duplicate_reference": "error", + "duplicate_sheet_names": "error", + "extra_units": "error", + "global_label_dangling": "warning", + "hier_label_mismatch": "error", + "label_dangling": "error", + "lib_symbol_issues": "warning", + "multiple_net_names": "warning", + "net_not_bus_member": "warning", + "no_connect_connected": "warning", + "no_connect_dangling": "warning", + "pin_not_connected": "error", + "pin_not_driven": "error", + "pin_to_pin": "warning", + "power_pin_not_driven": "error", + "similar_labels": "warning", + "unannotated": "error", + "unit_value_mismatch": "error", + "unresolved_variable": "error", + "wire_dangling": "error" + } + }, + "libraries": { + "pinned_footprint_libs": [], + "pinned_symbol_libs": [] + }, + "meta": { + "filename": "annular_ring_bug.kicad_pro", + "version": 1 + }, + "net_settings": { + "classes": [ + { + "bus_width": 12.0, + "clearance": 0.2, + "diff_pair_gap": 0.25, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.2, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "Default", + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.25, + "via_diameter": 0.8, + "via_drill": 0.4, + "wire_width": 6.0 + } + ], + "meta": { + "version": 2 + }, + "net_colors": null + }, + "pcbnew": { + "last_paths": { + "gencad": "", + "idf": "", + "netlist": "", + "specctra_dsn": "", + "step": "", + "vrml": "" + }, + "page_layout_descr_file": "" + }, + "schematic": { + "annotate_start_num": 0, + "drawing": { + "default_line_thickness": 6.0, + "default_text_size": 50.0, + "field_names": [], + "intersheets_ref_own_page": false, + "intersheets_ref_prefix": "", + "intersheets_ref_short": false, + "intersheets_ref_show": false, + "intersheets_ref_suffix": "", + "junction_size_choice": 3, + "label_size_ratio": 0.375, + "pin_symbol_size": 25.0, + "text_offset_ratio": 0.15 + }, + "legacy_lib_dir": "", + "legacy_lib_list": [], + "meta": { + "version": 1 + }, + "net_format_name": "", + "ngspice": { + "fix_include_paths": true, + "fix_passive_vals": false, + "meta": { + "version": 0 + }, + "model_mode": 0, + "workbook_filename": "" + }, + "page_layout_descr_file": "", + "plot_directory": "", + "spice_adjust_passive_values": false, + "spice_external_command": "spice \"%I\"", + "subpart_first_id": 65, + "subpart_id_separator": 0 + }, + "sheets": [ + [ + "2fefeeaa-67ac-4417-8942-fd028df5cfd1", + "" + ] + ], + "text_variables": {} +} diff --git a/qa/data/pcbnew/issue7567.kicad_pcb b/qa/data/pcbnew/issue7567.kicad_pcb index acc7359471..34e678f34b 100644 --- a/qa/data/pcbnew/issue7567.kicad_pcb +++ b/qa/data/pcbnew/issue7567.kicad_pcb @@ -212,7 +212,6 @@ (descr "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,") (tags "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,") (path "/00000000-0000-0000-0000-000058633372") - (attr through_hole) (fp_text reference "MK2" (at 0 -4.50088) (layer "F.SilkS") hide (effects (font (size 1 1) (thickness 0.15))) (tstamp ff4093c6-37e5-4062-80ab-cee0613ea782) @@ -232,7 +231,6 @@ (descr "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,") (tags "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,") (path "/00000000-0000-0000-0000-000058633409") - (attr through_hole) (fp_text reference "MK1" (at 0 -4.50088) (layer "F.SilkS") hide (effects (font (size 1 1) (thickness 0.15))) (tstamp fdb9b92b-133b-4b47-8202-34e9c2a71818) @@ -252,7 +250,6 @@ (descr "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,") (tags "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,") (path "/00000000-0000-0000-0000-00005863348e") - (attr through_hole) (fp_text reference "MK4" (at 0 -4.50088) (layer "F.SilkS") hide (effects (font (size 1 1) (thickness 0.15))) (tstamp 89f8f381-144b-4f6d-97c0-9d50963af224) @@ -272,7 +269,6 @@ (descr "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,") (tags "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,") (path "/00000000-0000-0000-0000-000058633454") - (attr through_hole) (fp_text reference "MK3" (at 0 -4.50088) (layer "F.SilkS") hide (effects (font (size 1 1) (thickness 0.15))) (tstamp ec3af793-b9a1-4776-987a-62dc3ac44e4a) diff --git a/qa/unittests/pcbnew/drc/test_drc_regressions.cpp b/qa/unittests/pcbnew/drc/test_drc_regressions.cpp index 962df78439..d4e80c1d89 100644 --- a/qa/unittests/pcbnew/drc/test_drc_regressions.cpp +++ b/qa/unittests/pcbnew/drc/test_drc_regressions.cpp @@ -117,18 +117,19 @@ BOOST_FIXTURE_TEST_CASE( DRCFalseNegativeRegressions, DRC_REGRESSION_TEST_FIXTUR std::vector< std::pair > tests = { - { "issue1358", 2 }, - { "issue2512", 5 }, - { "issue2528", 1 }, - { "issue5750", 4 }, //Shorting zone fills pass DRC in some cases - { "issue5854", 3 }, - { "issue6879", 7 }, - { "issue6945", 2 }, - { "issue7241", 1 }, - { "issue7267", 4 }, - { "issue7325", 2 }, - { "issue8003", 2 }, - { "issue9081", 2 } + { "issue1358", 2 }, + { "issue2512", 5 }, + { "issue2528", 1 }, + { "issue5750", 4 }, // Shorting zone fills pass DRC in some cases + { "issue5854", 3 }, + { "issue6879", 7 }, + { "issue6945", 2 }, + { "issue7241", 1 }, + { "issue7267", 4 }, + { "issue7325", 2 }, + { "issue8003", 2 }, + { "issue9081", 2 }, + { "issue12109", 8 } // Pads fail annular width test }; for( const std::pair& entry : tests )