diff --git a/pcbnew/board_item.cpp b/pcbnew/board_item.cpp
index b89fe46db3..9da33476e5 100644
--- a/pcbnew/board_item.cpp
+++ b/pcbnew/board_item.cpp
@@ -181,8 +181,8 @@ bool BOARD_ITEM::ptr_cmp::operator() ( const BOARD_ITEM* a, const BOARD_ITEM* b
     if( a->Type() != b->Type() )
         return a->Type() < b->Type();
 
-    if( a->GetLayer() != b->GetLayer() )
-        return a->GetLayer() < b->GetLayer();
+    if( a->GetLayerSet() != b->GetLayerSet() )
+        return a->GetLayerSet().Seq() < b->GetLayerSet().Seq();
 
     if( a->m_Uuid != b->m_Uuid )       // UUIDs *should* always be unique (for valid boards anyway)
         return a->m_Uuid < b->m_Uuid;
diff --git a/pcbnew/drc/drc_test_provider_edge_clearance.cpp b/pcbnew/drc/drc_test_provider_edge_clearance.cpp
index 7f9e6e2de6..6b023910d8 100644
--- a/pcbnew/drc/drc_test_provider_edge_clearance.cpp
+++ b/pcbnew/drc/drc_test_provider_edge_clearance.cpp
@@ -255,7 +255,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
                         m_largestClearance );
             }
 
-            if( testSilk && ( item->GetLayer() == F_SilkS || item->GetLayer() == B_SilkS ) )
+            if( testSilk && ( item->IsOnLayer( F_SilkS ) || item->IsOnLayer( B_SilkS ) ) )
             {
                 if( edgesTree.QueryColliding( item, UNDEFINED_LAYER, testLayer, nullptr,
                         [&]( BOARD_ITEM* edge ) -> bool