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+P 3 0 1 0 50 50 -50 0 50 -50 F +X K 1 -150 0 100 R 50 50 1 1 P +X A 2 150 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 50 V V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# VSOURCE +# +DEF ~VSOURCE V 0 40 Y Y 1 F N +F0 "V" 200 200 50 H V C CNN +F1 "VSOURCE" 250 100 50 H I C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +F4 "Value" 0 0 60 H I C CNN "Fieldname" +F5 "V" 0 0 60 H I C CNN "Spice_Primitive" +F6 "1 2" -300 200 60 H I C CNN "Spice_Node_Sequence" +DRAW +C 0 0 100 0 1 0 N +P 2 0 1 0 0 -75 0 75 N +P 4 0 1 0 0 75 -25 25 25 25 0 75 F +X ~ 1 0 200 100 D 50 50 1 1 I +X ~ 2 0 -200 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/demos/simulation/rectifier/rectifier.pro b/demos/simulation/rectifier/rectifier.pro new file mode 100644 index 0000000000..d9bf54bb1a --- /dev/null +++ b/demos/simulation/rectifier/rectifier.pro @@ -0,0 +1,63 @@ +update=śro, 11 maj 2016, 18:59:29 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=/home/twl/Kicad-dev/kicad-library/library +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves +LibName30=pspice diff --git a/demos/simulation/rectifier/rectifier.sch b/demos/simulation/rectifier/rectifier.sch new file mode 100644 index 0000000000..055b7ba0a8 --- /dev/null +++ b/demos/simulation/rectifier/rectifier.sch @@ -0,0 +1,159 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:pspice +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L VSOURCE V1 +U 1 1 57336052 +P 4400 4050 +F 0 "V1" H 4528 4096 50 0000 L CNN +F 1 "SINE(0 1.5 1k 0 0 0 0)" H 4528 4005 50 0000 L CNN +F 2 "" H 4400 4050 50 0000 C CNN +F 3 "" H 4400 4050 50 0000 C CNN +F 4 "Value" H 4400 4050 60 0001 C CNN "Fieldname" +F 5 "V" H 4400 4050 60 0001 C CNN "Spice_Primitive" +F 6 "1 2" H 4100 4250 60 0001 C CNN "Spice_Node_Sequence" + 1 4400 4050 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR1 +U 1 1 573360D3 +P 4400 4350 +F 0 "#PWR1" H 4400 4100 50 0001 C CNN +F 1 "GND" H 4405 4177 50 0000 C CNN +F 2 "" H 4400 4350 50 0000 C CNN +F 3 "" H 4400 4350 50 0000 C CNN + 1 4400 4350 + 1 0 0 -1 +$EndComp +$Comp +L R R1 +U 1 1 573360F5 +P 4650 3700 +F 0 "R1" V 4443 3700 50 0000 C CNN +F 1 "1k" V 4534 3700 50 0000 C CNN +F 2 "" V 4580 3700 50 0000 C CNN +F 3 "" H 4650 3700 50 0000 C CNN +F 4 "Value" H 4650 3700 60 0001 C CNN "Fieldname" +F 5 "1 2" H 4650 3700 60 0001 C CNN "SpiceMapping" +F 6 "R" V 4650 3700 60 0001 C CNN "Spice_Primitive" + 1 4650 3700 + 0 1 1 0 +$EndComp +$Comp +L D D1 +U 1 1 573361B8 +P 5100 3700 +F 0 "D1" H 5100 3485 50 0000 C CNN +F 1 "1N4148" H 5100 3576 50 0000 C CNN +F 2 "" H 5100 3700 50 0000 C CNN +F 3 "" H 5100 3700 50 0000 C CNN +F 4 "Value" H 5100 3700 60 0001 C CNN "Fieldname" +F 5 "D" H 5100 3700 60 0001 C CNN "Spice_Primitive" +F 6 "2 1" H 5100 3700 60 0001 C CNN "Spice_Node_Sequence" + 1 5100 3700 + -1 0 0 1 +$EndComp +$Comp +L C C1 +U 1 1 5733628F +P 5400 4000 +F 0 "C1" H 5515 4046 50 0000 L CNN +F 1 "100n" H 5515 3955 50 0000 L CNN +F 2 "" H 5438 3850 50 0000 C CNN +F 3 "" H 5400 4000 50 0000 C CNN +F 4 "Value" H 5400 4000 60 0001 C CNN "Fieldname" +F 5 "C" H 5400 4000 60 0001 C CNN "Spice_Primitive" +F 6 "1 2" H 5400 4000 60 0001 C CNN "SpiceMapping" + 1 5400 4000 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 573362F7 +P 5750 4000 +F 0 "R2" H 5680 3954 50 0000 R CNN +F 1 "100k" H 5680 4045 50 0000 R CNN +F 2 "" V 5680 4000 50 0000 C CNN +F 3 "" H 5750 4000 50 0000 C CNN +F 4 "Value" H 5750 4000 60 0001 C CNN "Fieldname" +F 5 "1 2" H 5750 4000 60 0001 C CNN "SpiceMapping" +F 6 "R" V 5750 4000 60 0001 C CNN "Spice_Primitive" + 1 5750 4000 + -1 0 0 1 +$EndComp +Text Notes 4300 4900 0 60 ~ 0 +.tran 1u 10m\n +Wire Wire Line + 4400 4350 4400 4250 +Wire Wire Line + 4400 4300 5750 4300 +Connection ~ 4400 4300 +Wire Wire Line + 5250 3700 5750 3700 +Wire Wire Line + 5750 3700 5750 3850 +Wire Wire Line + 5400 3850 5400 3700 +Connection ~ 5400 3700 +Wire Wire Line + 5400 4300 5400 4150 +Wire Wire Line + 5750 4300 5750 4150 +Connection ~ 5400 4300 +Wire Wire Line + 4800 3700 4950 3700 +Connection ~ 4900 3700 +Wire Wire Line + 4400 3850 4400 3700 +Wire Wire Line + 4400 3700 4500 3700 +Text Label 4400 3800 0 60 ~ 0 +in +Text Label 5550 3700 0 60 ~ 0 +rect +Text Notes 4300 5000 0 60 ~ 0 +*.ac dec 10 1 1Meg\n +$EndSCHEMATC diff --git a/demos/simulation/sallen_key/AD8051.lib b/demos/simulation/sallen_key/AD8051.lib new file mode 100644 index 0000000000..20ac791cd7 --- /dev/null +++ b/demos/simulation/sallen_key/AD8051.lib @@ -0,0 +1,112 @@ +* AD8051 SPICE Macro-model +* Description: Amplifier +* Generic Desc: Single 110 MHz rail-to-rail op amp - 3V +* Developed by: JCH / ADI +* Revision History: 08/10/2012 - Updated to new header style +* 0.0 (09/1998) +* Copyright 1998, 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance with the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* CMRR IS NOT MODELED +* +* Parameters modeled include: +* THIS MODEL IS FOR SINGLE SUPPLY OPERATION (+5V) +* +* END Notes +* +* Node assignments +* noninverting input +* | inverting input +* | | positive supply +* | | | negative supply +* | | | | output +* | | | | | +* | | | | | +.SUBCKT AD8051 1 2 99 50 45 +* +* INPUT STAGE +* +Q1 4 3 5 QPI +Q2 6 2 7 QPI +RC1 50 4 20.5k +RC2 50 6 20.5k +RE1 5 8 5k +RE2 7 8 5k +EOS 3 1 POLY(1) 53 98 1.7E-3 1 +IOS 1 2 0.1u +FNOI1 1 0 VMEAS2 1E-4 +FNOI2 2 0 VMEAS2 1E-4 + +CPAR1 3 50 1.7p +CPAR2 2 50 1.7p +VCMH1 99 9 1 +VCMH2 99 10 1 +D1 5 9 DX +D2 7 10 DX +IBIAS 99 8 73u +* +* INTERNAL VOLTAGE REFERENCE +* +EREF1 98 0 POLY(2) 99 0 50 0 0 0.5 0.5 +EREF2 97 0 POLY(2) 1 0 2 0 0 0.5 0.5 +GREF2 97 0 97 0 1E-6 +* +*VOLTAGE NOISE STAGE +* +DN1 51 52 DNOI1 +VN1 51 98 0.61 +VMEAS 52 98 0 +RNOI1 52 98 6.5E-3 + +H1 53 98 VMEAS 1 +RNOI2 53 98 1 +* +*CURRENT NOISE STAGE +* +DN2 61 62 DNOI2 +VN2 61 98 0.545 +VMEAS2 62 98 0 +RNOI3 62 98 2E-4 +* +* INTERMEDIATE GAIN STAGE WITH POLE = 96MHz +* +G1 98 20 4 6 1E-3 +RP1 98 20 550 +CP1 98 20 3p +* +* GAIN STAGE WITH DOMINANT POLE +* +G4 98 30 20 98 2.6E-3 +RG1 30 98 155k +CF1 30 45 13.5p +D5 31 99 DX +D6 50 32 DX +V1 31 30 0.6 +V2 30 32 0.6 +* +* OUTPUT STAGE +* +Q3 45 42 99 QPOX +Q4 45 44 50 QNOX +EO3 99 42 POLY(1) 98 30 0.7175 0.5 +EO4 44 50 POLY(1) 30 98 0.7355 0.5 +* +* MODELS +* +.MODEL QPI PNP (IS=8.6E-18,BF=91,VAF=30.6) +.MODEL QNOX NPN(IS=6.37E-16,BF=100,VAF=90,RC=3) +.MODEL QPOX PNP(IS=1.19E-15,BF=112,VAF=19.2,RC=6) +.MODEL DX D(IS=1E-16) +.MODEL DZ D(IS=1E-14,BV=6.6) +.MODEL DNOI1 D(KF=9E-10) +.MODEL DNOI2 D(KF=1E-8) +.ENDS AD8051 + + + + diff --git a/demos/simulation/sallen_key/sallen_key-cache.lib b/demos/simulation/sallen_key/sallen_key-cache.lib new file mode 100644 index 0000000000..96a2f7eecf --- /dev/null +++ b/demos/simulation/sallen_key/sallen_key-cache.lib @@ -0,0 +1,124 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 50 H V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + C? + C_????_* + C_???? + SMD*_c + Capacitor* + Capacitors_ThroughHole:C_Radial_D10_L13_P5 + Capacitors_SMD:C_0805 + Capacitors_SMD:C_1206 +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# Generic_Opamp +# +DEF Generic_Opamp U 0 20 Y Y 1 F N +F0 "U" 0 250 50 H V L CNN +F1 "Generic_Opamp" 0 150 50 H V L CNN +F2 "" -100 -100 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +P 4 0 1 10 -200 200 200 0 -200 -200 -200 200 f +X + 1 -300 100 100 R 50 50 1 1 I +X - 2 -300 -100 100 R 50 50 1 1 I +X V+ 3 -100 300 150 D 50 50 1 1 W +X V- 4 -100 -300 150 U 50 50 1 1 W +X ~ 5 300 0 100 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 50 V V C CNN +F3 "" 0 0 50 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# VDD +# +DEF VDD #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VDD" 0 150 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VDD 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# VSOURCE +# +DEF ~VSOURCE V 0 40 Y Y 1 F N +F0 "V" 200 200 50 H V C CNN +F1 "VSOURCE" 250 100 50 H I C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +F4 "Value" 0 0 60 H I C CNN "Fieldname" +F5 "V" 0 0 60 H I C CNN "Spice_Primitive" +F6 "1 2" -300 200 60 H I C CNN "Spice_Node_Sequence" +DRAW +C 0 0 100 0 1 0 N +P 2 0 1 0 0 -75 0 75 N +P 4 0 1 0 0 75 -25 25 25 25 0 75 F +X ~ 1 0 200 100 D 50 50 1 1 I +X ~ 2 0 -200 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# VSS +# +DEF VSS #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VSS" 0 150 50 H V C CNN +F2 "" 0 0 50 H V C CNN +F3 "" 0 0 50 H V C CNN +DRAW +C 0 75 25 0 1 0 N +P 2 0 1 0 0 0 0 50 N +X VSS 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/demos/simulation/sallen_key/sallen_key.pro b/demos/simulation/sallen_key/sallen_key.pro new file mode 100644 index 0000000000..d91a6573a1 --- /dev/null +++ b/demos/simulation/sallen_key/sallen_key.pro @@ -0,0 +1,74 @@ +update=pią, 15 lip 2016, 17:18:36 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 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+LibName28=contrib +LibName29=valves +LibName30=pspice +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 +ERC_TestSimilarLabels=1 diff --git a/demos/simulation/sallen_key/sallen_key.sch b/demos/simulation/sallen_key/sallen_key.sch new file mode 100644 index 0000000000..4b0d2e2edd --- /dev/null +++ b/demos/simulation/sallen_key/sallen_key.sch @@ -0,0 +1,285 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:pspice +LIBS:sallen_key-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L VSOURCE V1 +U 1 1 57336052 +P 6000 4700 +F 0 "V1" H 6128 4746 50 0000 L CNN +F 1 "AC 1" H 6128 4655 50 0000 L CNN +F 2 "" H 6000 4700 50 0000 C CNN +F 3 "" H 6000 4700 50 0000 C CNN +F 4 "Value" H 6000 4700 60 0001 C CNN "Fieldname" +F 5 "V" H 6000 4700 60 0001 C CNN "Spice_Primitive" +F 6 "1 2" H 5700 4900 60 0001 C CNN "Spice_Node_Sequence" + 1 6000 4700 + 1 0 0 -1 +$EndComp +Text Notes 4300 4900 0 60 ~ 0 +*.tran 1u 10m\n +Text Notes 4300 4800 0 60 ~ 0 +.include diodes.lib\n +Text Label 8550 4400 0 60 ~ 0 +lowpass +Text Notes 4300 5000 0 60 ~ 0 +.ac dec 10 1 1Meg\n +$Comp +L Generic_Opamp U1 +U 1 1 5788FF9F +P 7850 4400 +F 0 "U1" H 8191 4446 50 0000 L CNN +F 1 "AD8051" H 8191 4355 50 0000 L CNN +F 2 "" H 7750 4300 50 0000 C CNN +F 3 "" H 7850 4400 50 0000 C CNN +F 4 "Value" H 7850 4400 60 0001 C CNN "Fieldname" +F 5 "X" H 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