diff --git a/internat/fr/kicad.mo b/internat/fr/kicad.mo index 149ffe46a1..34bf308c68 100644 Binary files a/internat/fr/kicad.mo and b/internat/fr/kicad.mo differ diff --git a/internat/fr/kicad.po b/internat/fr/kicad.po index 66cfd60f49..538f3fd90b 100644 --- a/internat/fr/kicad.po +++ b/internat/fr/kicad.po @@ -2,7 +2,7 @@ msgid "" msgstr "" "Project-Id-Version: kicad\n" "POT-Creation-Date: \n" -"PO-Revision-Date: 2007-10-13 19:18+0100\n" +"PO-Revision-Date: 2007-10-19 08:14+0100\n" "Last-Translator: \n" "Language-Team: kicad team \n" "MIME-Version: 1.0\n" @@ -734,8 +734,8 @@ msgstr "Outils" #: pcbnew/gendrill.cpp:1098 #: pcbnew/gendrill.cpp:1674 #: pcbnew/class_pad.cpp:995 -#: pcbnew/class_track.cpp:812 -#: pcbnew/class_track.cpp:817 +#: pcbnew/class_track.cpp:836 +#: pcbnew/class_track.cpp:841 msgid "Drill" msgstr "Perçage" @@ -984,8 +984,8 @@ msgstr "Texte Pcb" #: pcbnew/class_text_mod.cpp:347 #: pcbnew/class_text_mod.cpp:351 #: pcbnew/class_pad.cpp:972 -#: pcbnew/class_track.cpp:796 #: pcbnew/dialog_edit_module.cpp:234 +#: pcbnew/class_track.cpp:820 #: pcbnew/sel_layer.cpp:145 #: pcbnew/class_module.cpp:1116 #: gerbview/affiche.cpp:109 @@ -1035,8 +1035,8 @@ msgstr "Orient" #: pcbnew/classpcb.cpp:202 #: pcbnew/class_text_mod.cpp:364 #: pcbnew/pcbtexte.cpp:130 -#: pcbnew/class_track.cpp:820 #: pcbnew/class_edge_mod.cpp:297 +#: pcbnew/class_track.cpp:844 #: eeschema/affiche.cpp:188 #: eeschema/dialog_cmp_graphic_properties.cpp:188 #: gerbview/affiche.cpp:52 @@ -1558,7 +1558,7 @@ msgstr "Mode d'affichage Haut Contraste" #: pcbnew/pcbframe.cpp:442 #: pcbnew/class_board_item.cpp:140 -#: pcbnew/class_track.cpp:729 +#: pcbnew/class_track.cpp:753 msgid "Track" msgstr "Piste" @@ -1920,10 +1920,6 @@ msgstr "Inclure pistes autorout msgid "Include Locked Tracks" msgstr "Inclure pistes verrouillées" -#: pcbnew/deltrack.cpp:153 -msgid "Delete NET ?" -msgstr "Supprimer Net ?" - #: pcbnew/dialog_track_options.cpp:125 msgid "Via Size" msgstr "Diametre Via" @@ -2004,6 +2000,7 @@ msgid "Filled" msgstr "Plein" #: pcbnew/dialog_display_options.cpp:196 +#: pcbnew/ioascii.cpp:196 msgid "Tracks:" msgstr "Pistes:" @@ -2082,65 +2079,9 @@ msgstr "Afficher autres msgid "Show page limits" msgstr " Afficher limites de page" -#: pcbnew/clean.cpp:163 -msgid "Delete unconnected tracks:" -msgstr "Suppression Pistes non connectées" - -#: pcbnew/clean.cpp:181 -msgid "ViaDef" -msgstr "ViaDef" - -#: pcbnew/clean.cpp:332 -msgid "Clean Null Segments" -msgstr "Nettoyage segments nulls" - -#: pcbnew/clean.cpp:420 -msgid "Merging Segments:" -msgstr "Associe Segment" - -#: pcbnew/clean.cpp:422 -msgid "Merge" -msgstr "Merge" - -#: pcbnew/clean.cpp:422 -#: pcbnew/dialog_pad_edit.cpp:186 -#: eeschema/dialog_erc.cpp:192 -#: eeschema/dialog_erc.cpp:196 -#: eeschema/dialog_edit_component_in_schematic.cpp:172 -msgid "0" -msgstr "0" - -#: pcbnew/clean.cpp:435 -msgid "Merge: " -msgstr "Merge: " - -#: pcbnew/clean.cpp:647 -msgid "DRC Control:" -msgstr "Controle DRC:" - -#: pcbnew/clean.cpp:652 -msgid "NetCtr" -msgstr "NetCtr" - -#: pcbnew/clean.cpp:886 -msgid "Centre" -msgstr "Centre" - -#: pcbnew/clean.cpp:886 -msgid "0 " -msgstr "0" - -#: pcbnew/clean.cpp:897 -msgid "Pads: " -msgstr "Pastilles: " - -#: pcbnew/clean.cpp:900 -msgid "Max" -msgstr "Max" - -#: pcbnew/clean.cpp:902 -msgid "Segm" -msgstr "Segm" +#: pcbnew/deltrack.cpp:153 +msgid "Delete NET ?" +msgstr "Supprimer Net ?" #: pcbnew/plotgerb.cpp:72 msgid "unable to create file " @@ -2244,7 +2185,7 @@ msgid "No Net" msgstr "No Net" #: pcbnew/zones.cpp:916 -#: pcbnew/class_track.cpp:755 +#: pcbnew/class_track.cpp:779 msgid "NetName" msgstr "NetName" @@ -2432,10 +2373,6 @@ msgstr "Segment en cours d' msgid "Delete Layer " msgstr "Effacer Couche" -#: pcbnew/ioascii.cpp:207 -msgid "Error: Unexpected end of file !" -msgstr "Erreur: Fin de fichier inattendue !" - #: pcbnew/set_grid.cpp:147 #: pcbnew/dialog_general_options.cpp:271 #: gerbview/options.cpp:183 @@ -2512,7 +2449,7 @@ msgstr "NetName Pad:" #: pcbnew/dialog_pad_edit.cpp:196 #: pcbnew/classpcb.cpp:186 #: pcbnew/class_board_item.cpp:108 -#: pcbnew/class_track.cpp:766 +#: pcbnew/class_track.cpp:790 msgid "Circle" msgstr "Cercle" @@ -2525,6 +2462,14 @@ msgstr "Ovale" msgid "Drill Shape:" msgstr "Forme du perçage:" +#: pcbnew/dialog_pad_edit.cpp:186 +#: pcbnew/clean.cpp:446 +#: eeschema/dialog_erc.cpp:192 +#: eeschema/dialog_erc.cpp:196 +#: eeschema/dialog_edit_component_in_schematic.cpp:172 +msgid "0" +msgstr "0" + #: pcbnew/dialog_pad_edit.cpp:187 msgid "90" msgstr "90" @@ -2562,7 +2507,7 @@ msgid "Pad Shape:" msgstr "Forme Pad:" #: pcbnew/dialog_pad_edit.cpp:205 -#: pcbnew/class_track.cpp:768 +#: pcbnew/class_track.cpp:792 msgid "Standard" msgstr "Standard" @@ -2657,6 +2602,14 @@ msgstr "Supprimer Module" msgid "Value " msgstr "Valeur " +#: pcbnew/ioascii.cpp:200 +msgid "Zones:" +msgstr "Zones:" + +#: pcbnew/ioascii.cpp:207 +msgid "Error: Unexpected end of file !" +msgstr "Erreur: Fin de fichier inattendue !" + #: pcbnew/pcbcfg.cpp:68 #: eeschema/eeconfig.cpp:58 #: cvpcb/menucfg.cpp:170 @@ -2709,10 +2662,62 @@ msgstr "Librairie: " msgid "Modules (%d items)" msgstr "Modules (%d éléments)" +#: pcbnew/clean.cpp:169 +msgid "Delete unconnected tracks:" +msgstr "Suppression Pistes non connectées" + +#: pcbnew/clean.cpp:188 +msgid "ViaDef" +msgstr "ViaDef" + +#: pcbnew/clean.cpp:348 +msgid "Clean Null Segments" +msgstr "Nettoyage segments nulls" + +#: pcbnew/clean.cpp:444 +msgid "Merging Segments:" +msgstr "Associe Segment" + +#: pcbnew/clean.cpp:446 +msgid "Merge" +msgstr "Merge" + +#: pcbnew/clean.cpp:460 +msgid "Merge: " +msgstr "Merge: " + +#: pcbnew/clean.cpp:680 +msgid "DRC Control:" +msgstr "Controle DRC:" + +#: pcbnew/clean.cpp:685 +msgid "NetCtr" +msgstr "NetCtr" + +#: pcbnew/clean.cpp:963 +msgid "Centre" +msgstr "Centre" + +#: pcbnew/clean.cpp:963 +msgid "0 " +msgstr "0" + +#: pcbnew/clean.cpp:976 +msgid "Pads: " +msgstr "Pastilles: " + +#: pcbnew/clean.cpp:980 +msgid "Max" +msgstr "Max" + +#: pcbnew/clean.cpp:983 +msgid "Segm" +msgstr "Segm" + #: pcbnew/classpcb.cpp:181 #: pcbnew/classpcb.cpp:313 #: pcbnew/class_text_mod.cpp:337 -#: pcbnew/class_track.cpp:740 +#: pcbnew/class_track.cpp:764 #: gerbview/affiche.cpp:93 msgid "Type" msgstr "Type" @@ -2726,7 +2731,7 @@ msgid " Arc " msgstr " Arc " #: pcbnew/classpcb.cpp:195 -#: pcbnew/class_track.cpp:764 +#: pcbnew/class_track.cpp:788 msgid "Segment" msgstr "Segment" @@ -3586,7 +3591,7 @@ msgid "Length:" msgstr "Long.:" #: pcbnew/class_board_item.cpp:153 -#: pcbnew/class_track.cpp:733 +#: pcbnew/class_track.cpp:757 msgid "Zone" msgstr "Zone" @@ -4013,19 +4018,6 @@ msgstr "Deselection" msgid "Deselect this layer to restore its No Change state" msgstr "Deselectionner cette couche pour restorer l'option Pas de Changement" -#: pcbnew/class_track.cpp:760 -msgid "NetCode" -msgstr "NetCode" - -#: pcbnew/class_track.cpp:780 -#: pcbnew/class_module.cpp:1135 -msgid "Stat" -msgstr "Stat" - -#: pcbnew/class_track.cpp:804 -msgid "Diam" -msgstr "Diam" - #: pcbnew/dialog_edit_module.cpp:39 msgid "Module properties" msgstr "Propriétés du Module" @@ -4200,6 +4192,19 @@ msgstr "Couche Mod." msgid "Seg Layer" msgstr "Couche Seg." +#: pcbnew/class_track.cpp:784 +msgid "NetCode" +msgstr "NetCode" + +#: pcbnew/class_track.cpp:804 +#: pcbnew/class_module.cpp:1135 +msgid "Stat" +msgstr "Stat" + +#: pcbnew/class_track.cpp:828 +msgid "Diam" +msgstr "Diam" + #: pcbnew/moduleframe.cpp:177 msgid "Module Editor: module modified!, Continue ?" msgstr "Editeur de Module: module modifié! Continuer ?" diff --git a/pcbnew/class_board_item.cpp b/pcbnew/class_board_item.cpp index cc9b0f6b1a..ad3fb20da5 100644 --- a/pcbnew/class_board_item.cpp +++ b/pcbnew/class_board_item.cpp @@ -170,9 +170,9 @@ wxString BOARD_ITEM::MenuText( const BOARD* aPcb ) const text << _( "Via" ) << wxT( " " ) << via->ShowWidth(); int shape = via->Shape(); - if( shape == VIA_ENTERREE ) + if( shape == BURIED_VIA ) text << wxT(" ") << _( "Blind" ); - else if( shape == VIA_BORGNE ) + else if( shape == BLIND_VIA ) text << wxT(" ") << _("Buried"); // else say nothing about normal vias @@ -182,7 +182,7 @@ wxString BOARD_ITEM::MenuText( const BOARD* aPcb ) const text << wxT( " [" ) << net->m_Netname << wxT( "]" ); } - if( shape != VIA_NORMALE ) + if( shape != THROUGH_VIA ) { // say which layers, only two for now int topLayer; diff --git a/pcbnew/class_track.cpp b/pcbnew/class_track.cpp index 36851ed7c0..3bc6b290ee 100644 --- a/pcbnew/class_track.cpp +++ b/pcbnew/class_track.cpp @@ -1,6 +1,6 @@ -/******************************************************************/ -/* fonctions membres des classes TRACK et derivees (voir struct.h */ -/******************************************************************/ +/*******************************************************************/ +/* Functions relatives to tracks, vias and zones(see class_track.h */ +/*******************************************************************/ #include "fctsys.h" #include "gr_basic.h" @@ -21,49 +21,50 @@ #ifdef RATSNET_DEBUG /**************************************/ -void DbgDisplayTrackInfos(TRACK * track) +void DbgDisplayTrackInfos( TRACK* track ) /**************************************/ + /* Only for ratsnest debug -*/ + */ { -wxString msg; - msg << wxT("Netcode ") << track->GetNet(); - msg << wxT(" - ") << track->GetSubNet(); - msg << wxT("\nptrS ") << (unsigned) track->start; - msg << wxT(" ptrE ") << (unsigned) track->end; - msg << wxT(" this ") << (unsigned) track; - - wxMessageBox(msg); + wxString msg; + + msg << wxT( "Netcode " ) << track->GetNet(); + msg << wxT( " - " ) << track->GetSubNet(); + msg << wxT( "\nptrS " ) << (unsigned) track->start; + msg << wxT( " ptrE " ) << (unsigned) track->end; + msg << wxT( " this " ) << (unsigned) track; + + wxMessageBox( msg ); } + #endif -/**************************************/ -/* Classes pour Pistes, Vias et Zones */ -/**************************************/ - -/* Constructeur des classes type pistes, vias et zones */ - +/**********************************************************/ TRACK::TRACK( BOARD_ITEM* StructFather, KICAD_T idtype ) : BOARD_ITEM( StructFather, idtype ) +/**********************************************************/ { - m_Width = 0; - m_Shape = S_SEGMENT; - start = end = NULL; + m_Width = 0; + m_Shape = S_SEGMENT; + start = end = NULL; SetNet( 0 ); SetSubNet( 0 ); - m_Drill = -1; - m_Param = 0; + m_Drill = -1; + m_Param = 0; } +/***************************/ wxString TRACK::ShowWidth() +/***************************/ { wxString msg; - -#if 0 + +#if 0 double value = To_User_Unit( g_UnitMetric, m_Width, PCB_INTERNAL_UNIT ); - + if( g_UnitMetric == INCHES ) // Affichage en mils msg.Printf( wxT( "%.1f" ), value * 1000 ); else @@ -73,7 +74,7 @@ wxString TRACK::ShowWidth() valeur_param( m_Width, msg ); #endif - + return msg; } @@ -94,7 +95,7 @@ SEGVIA::SEGVIA( BOARD_ITEM* StructFather ) : TRACK::TRACK( const TRACK& Source ) : BOARD_ITEM( Source ) { - m_Shape = Source.m_Shape; + m_Shape = Source.m_Shape; SetNet( Source.GetNet() ); m_Flags = Source.m_Flags; m_TimeStamp = Source.m_TimeStamp; @@ -108,28 +109,27 @@ TRACK::TRACK( const TRACK& Source ) : } -/* Because of the way SEGVIA and SEGZONE are derived from TRACK and because there are - virtual functions being used, we can no longer simply copy a TRACK and - expect it to be a via or zone. We must construct a true SEGVIA or SEGZONE so its constructor - can initialize the virtual function table properly. This factory type of - function called Copy() can duplicate either a TRACK, SEGVIA, or SEGZONE. -*/ +/* Because of the way SEGVIA and SEGZONE are derived from TRACK and because there are + * virtual functions being used, we can no longer simply copy a TRACK and + * expect it to be a via or zone. We must construct a true SEGVIA or SEGZONE so its constructor + * can initialize the virtual function table properly. This factory type of + * function called Copy() can duplicate either a TRACK, SEGVIA, or SEGZONE. + */ TRACK* TRACK::Copy() const { if( Type() == TYPETRACK ) - return new TRACK(*this); - + return new TRACK( *this ); + if( Type() == TYPEVIA ) - return new SEGVIA( (const SEGVIA&) *this ); + return new SEGVIA( (const SEGVIA &) * this ); if( Type() == TYPEZONE ) - return new SEGZONE( (const SEGZONE&) *this ); - + return new SEGZONE( (const SEGZONE &) * this ); + return NULL; // should never happen } - /***********************/ bool TRACK::IsNull() /***********************/ @@ -147,13 +147,13 @@ bool TRACK::IsNull() double TRACK::GetLength() const /*************************************************************/ { - int dx = m_Start.x - m_End.x; - int dy = m_Start.y - m_End.y; + int dx = m_Start.x - m_End.x; + int dy = m_Start.y - m_End.y; double dist = ( (double) dx * dx ) + ( (double) dy * dy ); - + dist = sqrt( dist ); - + return dist; } @@ -177,7 +177,7 @@ int TRACK::IsPointOnEnds( const wxPoint& point, int min_dist ) int dx = m_Start.x - point.x; int dy = m_Start.y - point.y; - + if( min_dist == 0 ) { if( (dx == 0) && (dy == 0 ) ) @@ -212,13 +212,13 @@ int TRACK::IsPointOnEnds( const wxPoint& point, int min_dist ) // see class_track.h // SEGVIA and SEGZONE inherit this version -SEARCH_RESULT TRACK::Visit( INSPECTOR* inspector, const void* testData, - const KICAD_T scanTypes[] ) +SEARCH_RESULT TRACK::Visit( INSPECTOR* inspector, const void* testData, + const KICAD_T scanTypes[] ) { - KICAD_T stype = *scanTypes; + KICAD_T stype = *scanTypes; -#if 0 && defined(DEBUG) - std::cout << GetClass().mb_str() << ' '; +#if 0 && defined (DEBUG) + std::cout << GetClass().mb_str() << ' '; #endif // If caller wants to inspect my type @@ -232,22 +232,14 @@ SEARCH_RESULT TRACK::Visit( INSPECTOR* inspector, const void* testData, } -// see class_track.h +/***********************************************/ bool SEGVIA::IsOnLayer( int layer_number ) const +/***********************************************/ { -/* its the same logic, don't need this - int via_type = Shape(); - - if( via_type == VIA_NORMALE ) - { - if( layer_number <= LAYER_CMP_N ) - return true; - else - return false; - } - - // VIA_BORGNE ou VIA_ENTERREE: -*/ +/** + * @param layer_number = layer number to test + * @return true if the via is on the layer layer_number + */ int bottom_layer, top_layer; @@ -264,24 +256,23 @@ bool SEGVIA::IsOnLayer( int layer_number ) const int TRACK::ReturnMaskLayer() /***********************************/ -/* Retourne le masque (liste bit a bit ) des couches occupees par le segment - * de piste pointe par PtSegm. - * Si PtSegm pointe une via, il y a plusieurs couches occupees +/* Return the mask layer for this. + * for a via, there is more than one layer used */ { if( Type() == TYPEVIA ) { int via_type = Shape(); - if( via_type == VIA_NORMALE ) + if( via_type == THROUGH_VIA ) return ALL_CU_LAYERS; - // VIA_BORGNE ou VIA_ENTERREE: + // BLIND_VIA ou BURIED_VIA: int bottom_layer, top_layer; // ReturnLayerPair() knows how layers are stored - ((SEGVIA*)this)->ReturnLayerPair( &top_layer, &bottom_layer ); + ( (SEGVIA*) this )->ReturnLayerPair( &top_layer, &bottom_layer ); int layermask = 0; while( bottom_layer <= top_layer ) @@ -300,13 +291,18 @@ int TRACK::ReturnMaskLayer() void SEGVIA::SetLayerPair( int top_layer, int bottom_layer ) /*********************************************************/ -/* Met a jour .m_Layer pour une via: - * m_Layer code les 2 couches limitant la via +/** Set the .m_Layer member param: + * For a via m_Layer contains the 2 layers : + * top layer and bottom layer used by the via. + * The via connect all layers from top layer to bottom layer + * 4 bits for the first layer and 4 next bits for the secaon layer + * @param top_layer = first layer connected by the via + * @param bottom_layer = last layer connected by the via */ { int via_type = Shape(); - if( via_type == VIA_NORMALE ) + if( via_type == THROUGH_VIA ) { top_layer = LAYER_CMP_N; bottom_layer = COPPER_LAYER_N; @@ -323,8 +319,10 @@ void SEGVIA::SetLayerPair( int top_layer, int bottom_layer ) void SEGVIA::ReturnLayerPair( int* top_layer, int* bottom_layer ) const /*********************************************************************/ -/* Retourne les 2 couches limitant la via - * les pointeurs top_layer et bottom_layer peuvent etre NULLs +/* Return the 2 layers used by the via (the via actually uses + * all layers between these 2 layers) + * @param top_layer = pointer to the first layer (can be null) + * @param bottom_layer = pointer to the last layer (can be null) */ { int b_layer = (m_Layer >> 4) & 15; @@ -332,21 +330,20 @@ void SEGVIA::ReturnLayerPair( int* top_layer, int* bottom_layer ) const if( b_layer > t_layer ) EXCHG( b_layer, t_layer ); - + if( top_layer ) *top_layer = t_layer; - + if( bottom_layer ) *bottom_layer = b_layer; } -/* supprime du chainage la structure Struct - * les structures arrieres et avant sont chainees directement +/* Remove this from the track linked list */ void TRACK::UnLink() { - /* Modification du chainage arriere */ + /* Remove the back link */ if( Pback ) { if( Pback->Type() != TYPEPCB ) @@ -358,7 +355,7 @@ void TRACK::UnLink() if( GetState( DELETED ) ) // A REVOIR car Pback = NULL si place en undelete { if( g_UnDeleteStack ) - g_UnDeleteStack[g_UnDeleteStackPtr - 1] = (BOARD_ITEM*)Pnext; + g_UnDeleteStack[g_UnDeleteStackPtr - 1] = (BOARD_ITEM*) Pnext; } else { @@ -374,7 +371,7 @@ void TRACK::UnLink() } } - /* Modification du chainage avant */ + /* Remove the forward link */ if( Pnext ) Pnext->Pback = Pback; @@ -385,24 +382,28 @@ void TRACK::UnLink() /************************************************************/ void TRACK::Insert( BOARD* Pcb, BOARD_ITEM* InsertPoint ) /************************************************************/ + +/* insert this (and its linked segments is exists) + * in the track linked list + * @param InsertPoint = insert point within the linked list + * if NULL: insert as first element of Pcb->m_Tracks + */ { TRACK* track; TRACK* NextS; - /* Insertion du debut de la chaine a greffer */ if( InsertPoint == NULL ) { Pback = Pcb; - + if( Type() == TYPEZONE ) // put SEGZONE on front of m_Zone list { - NextS = Pcb->m_Zone; - Pcb->m_Zone = (SEGZONE*)this; + NextS = Pcb->m_Zone; + Pcb->m_Zone = (SEGZONE*) this; } - else // put TRACK or SEGVIA on front of m_Track list { - NextS = Pcb->m_Track; + NextS = Pcb->m_Track; Pcb->m_Track = this; } } @@ -413,12 +414,12 @@ void TRACK::Insert( BOARD* Pcb, BOARD_ITEM* InsertPoint ) InsertPoint->Pnext = this; } - /* Chainage de la fin de la liste a greffer */ + /* Set the forward link */ track = this; - while( track->Pnext ) + while( track->Pnext ) // Search the end of added chain track = (TRACK*) track->Pnext; - /* Track pointe la fin de la chaine a greffer */ + /* Link the end of chain */ track->Pnext = NextS; if( NextS ) NextS->Pback = track; @@ -429,11 +430,10 @@ void TRACK::Insert( BOARD* Pcb, BOARD_ITEM* InsertPoint ) TRACK* TRACK::GetBestInsertPoint( BOARD* Pcb ) /***********************************************/ -/* Recherche du meilleur point d'insertion pour le nouveau segment de piste - * Retourne - * un pointeur sur le segment de piste APRES lequel l'insertion - * doit se faire ( dernier segment du net d'apartenance ) - * NULL si pas de piste ( liste vide ); +/** + * Search the "best" insertion point within the track linked list + * the best point is the of the corresponding net code section + * @return the item found in the linked list (or NULL if no track) */ { TRACK* track, * NextTrack; @@ -445,8 +445,8 @@ TRACK* TRACK::GetBestInsertPoint( BOARD* Pcb ) /* Traitement du debut de liste */ if( track == NULL ) - return NULL; /* pas de piste ! */ - if( GetNet() < track->GetNet() ) /* insertion en tete de liste */ + return NULL; /* No tracks ! */ + if( GetNet() < track->GetNet() ) /* no net code or net code = 0 (track not connected) */ return NULL; while( (NextTrack = (TRACK*) track->Pnext) != NULL ) @@ -460,13 +460,13 @@ TRACK* TRACK::GetBestInsertPoint( BOARD* Pcb ) } -/* Recherche du debut du net - * ( les elements sont classes par net_code croissant ) - * la recherche se fait a partir de this - * si net_code == -1 le netcode de this sera utilise - * Retourne un pointeur sur le debut du net, ou NULL si net non trouve - */ +/*******************************************/ TRACK* TRACK::GetStartNetCode( int NetCode ) +/*******************************************/ + +/* Search (within the track linked list) the first segment matching the netcode + * ( the linked list is always sorted by net codes ) + */ { TRACK* Track = this; int ii = 0; @@ -478,13 +478,13 @@ TRACK* TRACK::GetStartNetCode( int NetCode ) { if( Track->GetNet() > NetCode ) break; - + if( Track->GetNet() == NetCode ) { - ii++; + ii++; break; } - + Track = (TRACK*) Track->Pnext; } @@ -495,10 +495,13 @@ TRACK* TRACK::GetStartNetCode( int NetCode ) } -/* Recherche de la fin du net - * Retourne un pointeur sur la fin du net, ou NULL si net non trouve - */ +/*****************************************/ TRACK* TRACK::GetEndNetCode( int NetCode ) +/*****************************************/ + +/* Search (within the track linked list) the last segment matching the netcode + * ( the linked list is always sorted by net codes ) + */ { TRACK* NextS, * Track = this; int ii = 0; @@ -514,13 +517,13 @@ TRACK* TRACK::GetEndNetCode( int NetCode ) NextS = (TRACK*) Track->Pnext; if( Track->GetNet() == NetCode ) ii++; - + if( NextS == NULL ) break; - + if( NextS->GetNet() > NetCode ) break; - + Track = NextS; } @@ -531,43 +534,11 @@ TRACK* TRACK::GetEndNetCode( int NetCode ) } -#if 0 -/**********************************/ -TRACK* TRACK:: CopyList( int NbSegm ) const -/**********************************/ -/* Copie d'un Element ou d'une chaine de n elements - * Retourne un pointeur sur le nouvel element ou le debut de la - * nouvelle chaine - */ -{ - TRACK* NewTrack; - TRACK* FirstTrack; - TRACK* OldTrack; - const TRACK* Source = this; - - FirstTrack = NewTrack = Source->Copy(); - - for( int ii = 1; ii < NbSegm; ii++ ) - { - Source = Source->Next(); - if( Source == NULL ) - break; - - OldTrack = NewTrack; - - NewTrack = Source->Copy(); - - NewTrack->Insert( NULL, OldTrack ); - } - - return FirstTrack; -} -#endif - - /********************************************/ bool TRACK::WriteTrackDescr( FILE* File ) /********************************************/ +/* write a via description on file +*/ { int type = 0; @@ -592,9 +563,10 @@ bool TRACK::WriteTrackDescr( FILE* File ) void TRACK::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode ) /*********************************************************************/ -/* routine de trace de 1 segment de piste. - * Parametres : - * draw_mode = mode ( GR_XOR, GR_OR..) +/** Draws the segment. + * @param panel = current panel + * @param DC = current device context + * @param draw_mode = GR_XOR, GR_OR.. */ { int l_piste; @@ -608,7 +580,7 @@ void TRACK::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode ) GRSetDrawMode( DC, draw_mode ); - if( Type() == TYPEVIA ) /* VIA rencontree */ + if( Type() == TYPEVIA ) color = g_DesignSettings.m_ViaColor[m_Shape]; else color = g_DesignSettings.m_LayerColor[m_Layer]; @@ -639,9 +611,10 @@ void TRACK::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode ) l_piste = m_Width >> 1; - if( Type() == TYPEVIA ) /* VIA rencontree */ + if( Type() == TYPEVIA ) /* The via is drawn as a circle */ { - rayon = l_piste; if( rayon < zoom ) + rayon = l_piste; + if( rayon < zoom ) rayon = zoom; GRCircle( &panel->m_ClipBox, DC, m_Start.x, m_Start.y, rayon, color ); if( rayon > (4 * zoom) ) @@ -650,7 +623,7 @@ void TRACK::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode ) GRCircle( &panel->m_ClipBox, DC, m_Start.x, m_Start.y, inner_rayon, color ); - // Draw the via hole if the display option request it + // Draw the via hole if the display option allows it if( DisplayOpt.m_DisplayViaMode != VIA_HOLE_NOT_SHOW ) { if( (DisplayOpt.m_DisplayViaMode == ALL_VIA_HOLE_SHOW) @@ -685,7 +658,7 @@ void TRACK::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode ) } else { - if( l_piste <= zoom ) /* trace simplifie si l_piste/zoom <= 1 */ + if( l_piste <= zoom ) /* Sketch mode if l_piste/zoom <= 1 */ { GRCircle( &panel->m_ClipBox, DC, m_Start.x, m_Start.y, rayon, color ); } @@ -721,9 +694,9 @@ void TRACK::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode ) m_End.x, m_End.y, m_Width, color ); } - /* Trace de l'isolation (pour segments type CUIVRE et TRACK uniquement */ + /* Shows clearance (for tracks and vias, not for zone segments */ if( DisplayOpt.DisplayTrackIsol && ( m_Layer <= CMP_N ) - && ( Type() == TYPETRACK ) ) + && ( Type() == TYPETRACK || Type() == TYPEVIA) ) { GRCSegm( &panel->m_ClipBox, DC, m_Start.x, m_Start.y, m_End.x, m_End.y, @@ -737,8 +710,9 @@ void TRACK::Display_Infos( WinEDA_DrawFrame* frame ) { wxString msg; int text_pos; + #ifdef RATSNET_DEBUG -DbgDisplayTrackInfos(this); + DbgDisplayTrackInfos( this ); #endif frame->MsgPanel->EraseMsgBox(); @@ -763,22 +737,22 @@ DbgDisplayTrackInfos(this); text_pos = 1; Affiche_1_Parametre( frame, text_pos, _( "Type" ), msg, DARKCYAN ); - /* Affiche NetName pour les segments de piste type cuivre */ + /* Display NetName pour les segments de piste type cuivre */ text_pos += 15; - if( Type() == TYPETRACK - || Type() == TYPEZONE - || Type() == TYPEVIA ) + if( Type() == TYPETRACK + || Type() == TYPEZONE + || Type() == TYPEVIA ) { - EQUIPOT* equipot = ((WinEDA_PcbFrame*)frame)->m_Pcb->FindNet( GetNet() ); - + EQUIPOT* equipot = ( (WinEDA_PcbFrame*) frame )->m_Pcb->FindNet( GetNet() ); + if( equipot ) msg = equipot->m_Netname; else msg = wxT( "" ); - + Affiche_1_Parametre( frame, text_pos, _( "NetName" ), msg, RED ); - /* Affiche net code :*/ + /* Display net code : (usefull in test or debug) */ msg.Printf( wxT( "%d .%d" ), GetNet(), GetSubNet() ); text_pos += 18; Affiche_1_Parametre( frame, text_pos, _( "NetCode" ), msg, RED ); @@ -792,26 +766,26 @@ DbgDisplayTrackInfos(this); Affiche_1_Parametre( frame, -1, wxEmptyString, _( "Standard" ), RED ); } - /* Affiche les flags Status piste */ + /* Display the Status flags */ msg = wxT( ". . " ); if( GetState( SEGM_FIXE ) ) msg[0] = 'F'; - + if( GetState( SEGM_AR ) ) msg[2] = 'A'; - + text_pos = 42; Affiche_1_Parametre( frame, text_pos, _( "Stat" ), msg, MAGENTA ); - /* Affiche Layer(s) */ + /* Display layer or layer pair) */ if( Type() == TYPEVIA ) { SEGVIA* Via = (SEGVIA*) this; int top_layer, bottom_layer; - + Via->ReturnLayerPair( &top_layer, &bottom_layer ); - msg = ReturnPcbLayerName( top_layer, TRUE ) + wxT( "/" ) - + ReturnPcbLayerName( bottom_layer, TRUE ); + msg = ReturnPcbLayerName( top_layer, TRUE ) + wxT( "/" ) + + ReturnPcbLayerName( bottom_layer, TRUE ); } else msg = ReturnPcbLayerName( m_Layer ); @@ -819,25 +793,25 @@ DbgDisplayTrackInfos(this); text_pos += 5; Affiche_1_Parametre( frame, text_pos, _( "Layer" ), msg, BROWN ); - /* Affiche Epaisseur */ + /* Display width */ valeur_param( (unsigned) m_Width, msg ); text_pos += 11; - + if( Type() == TYPEVIA ) // Display Diam and Drill values { Affiche_1_Parametre( frame, text_pos, _( "Diam" ), msg, DARKCYAN ); int drill_value = m_Drill >= 0 ? m_Drill : g_DesignSettings.m_ViaDrill; - + valeur_param( (unsigned) drill_value, msg ); - + text_pos += 8; wxString title = _( "Drill" ); - + if( g_DesignSettings.m_ViaDrill >= 0 ) title += wxT( "*" ); - + Affiche_1_Parametre( frame, text_pos, _( "Drill" ), msg, RED ); } else @@ -853,24 +827,24 @@ DbgDisplayTrackInfos(this); */ bool TRACK::HitTest( const wxPoint& ref_pos ) { - int l_piste; /* demi-largeur de la piste */ - int dx, dy, spot_cX, spot_cY; - int ux0, uy0; - + int l_piste; /* demi-largeur de la piste */ + int dx, dy, spot_cX, spot_cY; + int ux0, uy0; + /* calcul des coordonnees du segment teste */ l_piste = m_Width >> 1; /* l_piste = demi largeur piste */ - - ux0 = m_Start.x; + + ux0 = m_Start.x; uy0 = m_Start.y; /* coord de depart */ - - dx = m_End.x; + + dx = m_End.x; dy = m_End.y; /* coord d'arrivee */ /* recalcul des coordonnees avec ux0, uy0 = origine des coordonnees */ - dx -= ux0; + dx -= ux0; dy -= uy0; - - spot_cX = ref_pos.x - ux0; + + spot_cX = ref_pos.x - ux0; spot_cY = ref_pos.y - uy0; if( Type() == TYPEVIA ) /* VIA rencontree */ @@ -885,58 +859,59 @@ bool TRACK::HitTest( const wxPoint& ref_pos ) if( DistanceTest( l_piste, dx, dy, spot_cX, spot_cY ) ) return true; } - - return false; + + return false; } - -#if defined(DEBUG) +#if defined (DEBUG) /** * Function Show * is used to output the object tree, currently for debugging only. - * @param nestLevel An aid to prettier tree indenting, and is the level + * @param nestLevel An aid to prettier tree indenting, and is the level * of nesting of this object within the overall tree. * @param os The ostream& to output to. */ void TRACK::Show( int nestLevel, std::ostream& os ) { NestedSpace( nestLevel, os ) << '<' << GetClass().Lower().mb_str() << + // " shape=\"" << m_Shape << '"' << - " layer=\"" << m_Layer << '"' << - " width=\"" << m_Width << '"' << + " layer=\"" << m_Layer << '"' << + " width=\"" << m_Width << '"' << + // " drill=\"" << m_Drill << '"' << - " netcode=\"" << GetNet() << "\">" << - "" << - ""; - - os << "\n"; + " netcode=\"" << GetNet() << "\">" << + "" << + ""; + + os << "\n"; } /** * Function Show * is used to output the object tree, currently for debugging only. - * @param nestLevel An aid to prettier tree indenting, and is the level + * @param nestLevel An aid to prettier tree indenting, and is the level * of nesting of this object within the overall tree. * @param os The ostream& to output to. */ void SEGVIA::Show( int nestLevel, std::ostream& os ) { const char* cp; - + switch( Shape() ) { - case VIA_NORMALE: + case THROUGH_VIA: cp = "through"; break; - case VIA_ENTERREE: + case BURIED_VIA: cp = "blind"; break; - case VIA_BORGNE: + case BLIND_VIA: cp = "buried"; break; @@ -946,26 +921,22 @@ void SEGVIA::Show( int nestLevel, std::ostream& os ) break; } - int topLayer; - int botLayer; - + int topLayer; + int botLayer; + ReturnLayerPair( &topLayer, &botLayer ); - + NestedSpace( nestLevel, os ) << '<' << GetClass().Lower().mb_str() << - " type=\"" << cp << '"' << - " layers=\"" << ReturnPcbLayerName( topLayer).Trim().mb_str() << "," - << ReturnPcbLayerName( botLayer ).Trim().mb_str() << '"' << - " width=\"" << m_Width << '"' << - " drill=\"" << m_Drill << '"' << - " netcode=\"" << GetNet() << "\">" << - ""; - - os << "\n"; + " type=\"" << cp << '"' << + " layers=\"" << ReturnPcbLayerName( topLayer ).Trim().mb_str() << "," + << ReturnPcbLayerName( botLayer ).Trim().mb_str() << '"' << + " width=\"" << m_Width << '"' << + " drill=\"" << m_Drill << '"' << + " netcode=\"" << GetNet() << "\">" << + ""; + + os << "\n"; } - - - - #endif diff --git a/pcbnew/class_track.h b/pcbnew/class_track.h index fd6d8a2dd7..270b405ac5 100644 --- a/pcbnew/class_track.h +++ b/pcbnew/class_track.h @@ -1,5 +1,5 @@ /*******************************************************************/ -/* class_track.h: definition des structures de donnees type track */ +/* class_track.h: definitions relatives to tracks, vias and zones */ /*******************************************************************/ #ifndef CLASS_TRACK_H @@ -15,10 +15,6 @@ #define NOT_DEFINED_VIA 0 /* reserved (unused) */ #define SQUARE_VIA_SHAPE 0x80000000 /* Flag pour forme carree */ -#define VIA_NORMALE THROUGH_VIA -#define VIA_ENTERREE BURIED_VIA -#define VIA_BORGNE BLIND_VIA - /***/ class TRACK : public BOARD_ITEM @@ -78,18 +74,20 @@ public: */ void Insert( BOARD* Pcb, BOARD_ITEM* InsertPoint ); - /* Recherche du meilleur point d'insertion */ +/*Search the "best" insertion point within the track linked list + * the best point is the of the corresponding net code section + * @return the item found in the linked list (or NULL if no track) + */ TRACK* GetBestInsertPoint( BOARD* Pcb ); - /* Copie d'un Element d'une chaine de n elements - * TRACK* CopyList( int NbSegm = 1 ) const; + /* Search (within the track linked list) the first segment matching the netcode + * ( the linked list is always sorted by net codes ) */ - - /* Recherche du debut du net - * ( les elements sont classes par net_code croissant ) */ TRACK* GetStartNetCode( int NetCode ); - /* Recherche de la fin du net */ + /* Search (within the track linked list) the last segment matching the netcode + * ( the linked list is always sorted by net codes ) + */ TRACK* GetEndNetCode( int NetCode ); /** diff --git a/pcbnew/classpcb.cpp b/pcbnew/classpcb.cpp index 932ce33434..99383dcc1f 100644 --- a/pcbnew/classpcb.cpp +++ b/pcbnew/classpcb.cpp @@ -433,7 +433,7 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings() m_CopperLayerCount = 2; // Default design is a double sided board m_ViaDrill = 250; // via drill (for the entire board) m_CurrentViaSize = 450; // Current via size - m_CurrentViaType = VIA_NORMALE; /* via type (BLIND, TROUGHT ...), bits 1 and 2 (not 0 and 1)*/ + m_CurrentViaType = THROUGH_VIA; /* via type (BLIND, TROUGHT ...), bits 1 and 2 (not 0 and 1)*/ m_CurrentTrackWidth = 170; // current track width for( ii = 0; ii < HIST0RY_NUMBER; ii++ ) { @@ -454,9 +454,9 @@ EDA_BoardDesignSettings::EDA_BoardDesignSettings() m_LayerColor[ii] = default_layer_color[ii]; // Layer colors (tracks and graphic items) - m_ViaColor[VIA_BORGNE] = CYAN; - m_ViaColor[VIA_ENTERREE] = BROWN; - m_ViaColor[VIA_NORMALE] = WHITE; + m_ViaColor[BLIND_VIA] = CYAN; + m_ViaColor[BURIED_VIA] = BROWN; + m_ViaColor[THROUGH_VIA] = WHITE; m_ModuleTextCMPColor = LIGHTGRAY; // Text module color for modules on the COMPONENT layer m_ModuleTextCUColor = MAGENTA; // Text module color for modules on the COPPER layer m_ModuleTextNOVColor = DARKGRAY; // Text module color for "invisible" texts (must be BLACK if really not displayed) diff --git a/pcbnew/classtrc.cpp.notused b/pcbnew/classtrc.cpp.notused deleted file mode 100644 index 784b540d58..0000000000 --- a/pcbnew/classtrc.cpp.notused +++ /dev/null @@ -1,510 +0,0 @@ -/******************************************************************/ -/* fonctions membres des classes TRACK et derivees (voir struct.h */ -/******************************************************************/ - -#include "fctsys.h" -#include "gr_basic.h" - -#include "common.h" -#include "pcbnew.h" - -#ifdef CVPCB -#include "cvpcb.h" -#endif - - - -/**************************************/ -/* Classes pour Pistes, Vias et Zones */ -/**************************************/ - -/* Constructeur des classes type pistes, vias et zones */ - -TRACK::TRACK( EDA_BaseStruct* StructFather, KICAD_T idtype ) : - SEGDRAW_Struct( StructFather, idtype ) -{ - m_Shape = S_SEGMENT; - start = end = NULL; - m_NetCode = 0; - m_Sous_Netcode = 0; -} - - -SEGZONE::SEGZONE( EDA_BaseStruct* StructFather ) : - TRACK( StructFather, TYPEZONE ) -{ -} - - -SEGVIA::SEGVIA( EDA_BaseStruct* StructFather ) : - TRACK( StructFather, TYPEVIA ) -{ -} - - -/******************************************/ -bool SEGVIA::IsViaOnLayer( int layer_number ) -/******************************************/ - -/* Retoune TRUE si Via sur layer layer_number - */ -{ - int via_type = Shape(); - - if( via_type == VIA_NORMALE ) - { - if( layer_number <= LAYER_CMP_N ) - return TRUE; - else - return FALSE; - } - - // VIA_BORGNE ou VIA_ENTERREE: - - int bottom_layer, top_layer; - ReturnLayerPair( &top_layer, &bottom_layer ); - if( (bottom_layer <= layer_number) && (top_layer >= layer_number) ) - return TRUE; - else - return FALSE; -} - - -/*********************************************************/ -void SEGVIA::SetLayerPair( int top_layer, int bottom_layer ) -/*********************************************************/ - -/* Met a jour .m_Layer pour une via: - * m_Layer code les 2 couches limitant la via - */ -{ - int via_type = m_Shape & 255; - - if( via_type == VIA_NORMALE ) - { - top_layer = LAYER_CMP_N; bottom_layer = LAYER_COPPER_LAYER_N; - } - - if( bottom_layer > top_layer ) - EXCHG( bottom_layer, top_layer ); - m_Layer = (top_layer & 15) + ( (bottom_layer & 15) << 4 ); -} - - -/***************************************************************/ -void SEGVIA::ReturnLayerPair( int* top_layer, int* bottom_layer ) -/***************************************************************/ - -/* Retourne les 2 couches limitant la via - * les pointeurs top_layer et bottom_layer peuvent etre NULLs - */ -{ - int b_layer = (m_Layer >> 4) & 15; - int t_layer = m_Layer & 15; - - if( b_layer > t_layer ) - EXCHG( b_layer, t_layer ); - if( top_layer ) - *top_layer = t_layer; - if( bottom_layer ) - *bottom_layer = b_layer; -} - - -/* supprime du chainage la structure Struct - * les structures arrieres et avant sont chainees directement - */ -void TRACK::UnLink( void ) -{ - /* Modification du chainage arriere */ - if( Pback ) - { - if( Pback->m_StructType != TYPEPCB ) - { - Pback->Pnext = Pnext; - } - else /* Le chainage arriere pointe sur la structure "Pere" */ - { - if( GetState( DELETED ) ) // A REVOIR car Pback = NULL si place en undelete - { - if( g_UnDeleteStack ) - g_UnDeleteStack[g_UnDeleteStackPtr - 1] = Pnext; - } - else - { - if( m_StructType == TYPEZONE ) - { - ( (BOARD*) Pback )->m_Zone = (TRACK*) Pnext; - } - else - { - ( (BOARD*) Pback )->m_Track = (TRACK*) Pnext; - } - } - } - } - - /* Modification du chainage avant */ - if( Pnext ) - Pnext->Pback = Pback; - - Pnext = Pback = NULL; -} - - -/************************************************************/ -void TRACK::Insert( BOARD* Pcb, EDA_BaseStruct* InsertPoint ) -/************************************************************/ - -/* Ajoute un element ou une liste a une liste de base - * Si Insertpoint == NULL: insertion en debut de - * liste Pcb->Track ou Pcb->Zone - * Insertion a la suite de InsertPoint - * Si InsertPoint == NULL, insertion en tete de liste - */ -{ - TRACK* track; - TRACK* NextS; - - /* Insertion du debut de la chaine a greffer */ - if( InsertPoint == NULL ) - { - Pback = Pcb; - if( m_StructType == TYPEZONE ) - { - NextS = Pcb->m_Zone; Pcb->m_Zone = this; - } - else - { - NextS = Pcb->m_Track; Pcb->m_Track = this; - } - } - else - { - NextS = (TRACK*) InsertPoint->Pnext; - Pback = InsertPoint; - InsertPoint->Pnext = this; - } - - /* Chainage de la fin de la liste a greffer */ - track = this; - while( track->Pnext ) - track = (TRACK*) track->Pnext; - - /* Track pointe la fin de la chaine a greffer */ - track->Pnext = NextS; - if( NextS ) - NextS->Pback = track; -} - - -/***********************************************/ -TRACK* TRACK::GetBestInsertPoint( BOARD* Pcb ) -/***********************************************/ - -/* Recherche du meilleur point d'insertion pour le nouveau segment de piste - * Retourne - * un pointeur sur le segment de piste APRES lequel l'insertion - * doit se faire ( dernier segment du net d'apartenance ) - * NULL si pas de piste ( liste vide ); - */ -{ - TRACK* track, * NextTrack; - - if( m_StructType == TYPEZONE ) - track = Pcb->m_Zone; - else - track = Pcb->m_Track; - - /* Traitement du debut de liste */ - if( track == NULL ) - return NULL; /* pas de piste ! */ - if( m_NetCode < track->m_NetCode ) /* insertion en tete de liste */ - return NULL; - - while( (NextTrack = (TRACK*) track->Pnext) != NULL ) - { - if( NextTrack->m_NetCode > this->m_NetCode ) - break; - track = NextTrack; - } - - return track; -} - - -/* Recherche du debut du net - * ( les elements sont classes par net_code croissant ) - * la recherche se fait a partir de this - * si net_code == -1 le netcode de this sera utilise - * Retourne un pointeur sur le debut du net, ou NULL si net non trouve - */ -TRACK* TRACK::GetStartNetCode( int NetCode ) -{ - TRACK* Track = this; - int ii = 0; - - if( NetCode == -1 ) - NetCode = m_NetCode; - - while( Track != NULL ) - { - if( Track->m_NetCode > NetCode ) - break; - - if( Track->m_NetCode == NetCode ) - { - ii++; - break; - } - Track = (TRACK*) Track->Pnext; - } - - if( ii ) - return Track; - else - return NULL; -} - - -/* Recherche de la fin du net - * Retourne un pointeur sur la fin du net, ou NULL si net non trouve - */ -TRACK* TRACK::GetEndNetCode( int NetCode ) -{ - TRACK* NextS; - TRACK* Track = this; - int ii = 0; - - if( Track == NULL ) - return NULL; - - if( NetCode == -1 ) - NetCode = m_NetCode; - - while( Track != NULL ) - { - NextS = (TRACK*) Track->Pnext; - if( Track->m_NetCode == NetCode ) - ii++; - if( NextS == NULL ) - break; - if( NextS->m_NetCode > NetCode ) - break; - Track = NextS; - } - - if( ii ) - return Track; - else - return NULL; -} - - -/**********************************/ -TRACK* TRACK:: Copy( int NbSegm ) -/**********************************/ - -/* Copie d'un Element ou d'une chaine de n elements - * Retourne un pointeur sur le nouvel element ou le debut de la - * nouvelle chaine - */ -{ - TRACK* NewTrack, * FirstTrack, * OldTrack, * Source = this; - int ii; - - FirstTrack = NewTrack = new TRACK( NULL ); - - *NewTrack = *Source; - - /* correction du chainage */ - NewTrack->Pback = NewTrack->Pnext = NULL; - - /* reset des pointeurs auxiliaires */ - NewTrack->start = NewTrack->end = NULL; - - if( NbSegm <=1 ) - return FirstTrack; - - for( ii = 1; ii < NbSegm; ii++ ) - { - Source = (TRACK*) Source->Pnext; - if( Source == NULL ) - break; - OldTrack = NewTrack; - NewTrack = new TRACK( m_Parent ); - - if( NewTrack == NULL ) - break; - NewTrack->m_StructType = Source->m_StructType; - NewTrack->m_Shape = Source->m_Shape; - NewTrack->m_NetCode = Source->m_NetCode; - NewTrack->m_Flags = Source->m_Flags; - NewTrack->m_TimeStamp = Source->m_TimeStamp; - NewTrack->SetStatus( Source->ReturnStatus() ); - NewTrack->m_Layer = Source->m_Layer; - NewTrack->m_Start = Source->m_Start; - NewTrack->m_End = Source->m_End; - NewTrack->m_Width = Source->m_Width; - - NewTrack->Insert( NULL, OldTrack ); - } - - return FirstTrack; -} - - -/********************************************/ -bool TRACK::WriteTrackDescr( FILE* File ) -/********************************************/ -{ - int type; - - type = 0; - if( m_StructType == TYPEVIA ) - type = 1; - - if( GetState( DELETED ) ) - return FALSE; - - fprintf( File, "Po %d %d %d %d %d %d\n", m_Shape, - m_Start.x, m_Start.y, m_End.x, m_End.y, m_Width ); - - fprintf( File, "De %d %d %d %lX %X\n", - m_Layer, type, m_NetCode, - m_TimeStamp, ReturnStatus() ); - return TRUE; -} - - -/**********************************************************************/ -void TRACK::Draw( WinEDA_DrawPanel* panel, wxDC* DC, int draw_mode ) -/*********************************************************************/ - -/* routine de trace de 1 segment de piste. - * Parametres : - * draw_mode = mode ( GR_XOR, GR_OR..) - */ -{ - int l_piste; - int color; - int zoom; - int rayon; - int curr_layer = ( (PCB_SCREEN*) panel->GetScreen() )->m_Active_Layer; - - if( m_StructType == TYPEZONE && (!DisplayOpt.DisplayZones) ) - return; - - GRSetDrawMode( DC, draw_mode ); - - if( m_StructType == TYPEVIA ) /* VIA rencontree */ - color = g_DesignSettings.m_ViaColor[m_Shape]; - else - color = g_DesignSettings.m_LayerColor[m_Layer]; - - if( ( color & (ITEM_NOT_SHOW | HIGHT_LIGHT_FLAG) ) == ITEM_NOT_SHOW ) - return; - - if( DisplayOpt.ContrastModeDisplay ) - { - if( m_StructType == TYPEVIA ) - { - if( !( (SEGVIA*) this )->IsViaOnLayer( curr_layer ) ) - { - color &= ~MASKCOLOR; - color |= DARKDARKGRAY; - } - } - else if( m_Layer != curr_layer ) - { - color &= ~MASKCOLOR; - color |= DARKDARKGRAY; - } - } - - if( draw_mode & GR_SURBRILL ) - { - if( draw_mode & GR_AND ) - color &= ~HIGHT_LIGHT_FLAG; - else - color |= HIGHT_LIGHT_FLAG; - } - if( color & HIGHT_LIGHT_FLAG ) - color = ColorRefs[color & MASKCOLOR].m_LightColor; - - zoom = panel->GetZoom(); - - l_piste = m_Width >> 1; - - if( m_StructType == TYPEVIA ) /* VIA rencontree */ - { - rayon = l_piste; if( rayon < zoom ) - rayon = zoom; - GRCircle( &panel->m_ClipBox, DC, m_Start.x, m_Start.y, rayon, color ); - if( rayon > (4 * zoom) ) - { - GRCircle( &panel->m_ClipBox, DC, m_Start.x, m_Start.y, - rayon - (2 * zoom), color ); - - if( DisplayOpt.DisplayTrackIsol ) - GRCircle( &panel->m_ClipBox, DC, m_Start.x, m_Start.y, - rayon + g_DesignSettings.m_TrackClearence, color ); - } - return; - } - - if( m_Shape == S_CIRCLE ) - { - rayon = (int) hypot( (double) (m_End.x - m_Start.x), - (double) (m_End.y - m_Start.y) ); - if( (l_piste / zoom) < L_MIN_DESSIN ) - { - GRCircle( &panel->m_ClipBox, DC, m_Start.x, m_Start.y, rayon, color ); - } - else - { - if( l_piste <= zoom ) /* trace simplifie si l_piste/zoom <= 1 */ - { - GRCircle( &panel->m_ClipBox, DC, m_Start.x, m_Start.y, rayon, color ); - } - else if( ( !DisplayOpt.DisplayPcbTrackFill) || GetState( FORCE_SKETCH ) ) - { - GRCircle( &panel->m_ClipBox, DC, m_Start.x, m_Start.y, rayon - l_piste, color ); - GRCircle( &panel->m_ClipBox, DC, m_Start.x, m_Start.y, rayon + l_piste, color ); - } - else - { - GRCircle( &panel->m_ClipBox, DC, m_Start.x, m_Start.y, rayon, - m_Width, color ); - } - } - return; - } - - if( (l_piste / zoom) < L_MIN_DESSIN ) - { - GRLine( &panel->m_ClipBox, DC, m_Start.x, m_Start.y, - m_End.x, m_End.y, color ); - return; - } - - if( (!DisplayOpt.DisplayPcbTrackFill) || GetState( FORCE_SKETCH ) ) - { - GRCSegm( &panel->m_ClipBox, DC, m_Start.x, m_Start.y, - m_End.x, m_End.y, m_Width, color ); - } - else - { - GRFillCSegm( &panel->m_ClipBox, DC, m_Start.x, m_Start.y, - m_End.x, m_End.y, m_Width, color ); - } - - /* Trace de l'isolation (pour segments type CUIVRE et TRACK uniquement */ - if( (DisplayOpt.DisplayTrackIsol) && (m_Layer <= CMP_N ) - && ( m_StructType == TYPETRACK) ) - { - GRCSegm( &panel->m_ClipBox, DC, m_Start.x, m_Start.y, - m_End.x, m_End.y, - m_Width + (g_DesignSettings.m_TrackClearence * 2), color ); - } -} diff --git a/pcbnew/clean.cpp b/pcbnew/clean.cpp index 2d6ba2a9e3..dd3288c6f9 100644 --- a/pcbnew/clean.cpp +++ b/pcbnew/clean.cpp @@ -81,7 +81,7 @@ void Clean_Pcb_Items( WinEDA_PcbFrame* frame, wxDC* DC ) TRACK* next_track; for( track = frame->m_Pcb->m_Track; track != NULL; track = track->Next() ) { - if( track->m_Shape != VIA_NORMALE ) + if( track->m_Shape != THROUGH_VIA ) continue; /* Search and delete others vias at same location */ @@ -89,7 +89,7 @@ void Clean_Pcb_Items( WinEDA_PcbFrame* frame, wxDC* DC ) for( ; alt_track != NULL; alt_track = next_track ) { next_track = alt_track->Next(); - if( alt_track->m_Shape != VIA_NORMALE ) + if( alt_track->m_Shape != THROUGH_VIA ) continue; if( alt_track->m_Start != track->m_Start ) @@ -105,7 +105,7 @@ void Clean_Pcb_Items( WinEDA_PcbFrame* frame, wxDC* DC ) for( track = frame->m_Pcb->m_Track; track != NULL; track = next_track ) { next_track = track->Next(); - if( track->m_Shape != VIA_NORMALE ) + if( track->m_Shape != THROUGH_VIA ) continue; D_PAD* pad = Fast_Locate_Pad_Connecte( frame->m_Pcb, track->m_Start, ALL_CU_LAYERS ); diff --git a/pcbnew/dialog_track_options.cpp b/pcbnew/dialog_track_options.cpp index 6d86a9c984..e26b19bdfa 100644 --- a/pcbnew/dialog_track_options.cpp +++ b/pcbnew/dialog_track_options.cpp @@ -251,11 +251,11 @@ void WinEDA_PcbTracksDialog::AcceptPcbOptions(wxCommandEvent& event) /*******************************************************************/ { g_DesignSettings.m_CurrentViaType = m_OptViaType->GetSelection() + 1; - if ( g_DesignSettings.m_CurrentViaType != VIA_NORMALE ) + if ( g_DesignSettings.m_CurrentViaType != THROUGH_VIA ) { if( ! IsOK(this, _("You have selected VIA Blind or VIA Buried\nWARNING: this feature is EXPERIMENTAL!!! Accept ?") ) ) - g_DesignSettings.m_CurrentViaType = VIA_NORMALE; + g_DesignSettings.m_CurrentViaType = THROUGH_VIA; } g_DesignSettings.m_CurrentViaSize = diff --git a/pcbnew/editrack-part2.cpp b/pcbnew/editrack-part2.cpp index 2562eb685e..194845dfc3 100644 --- a/pcbnew/editrack-part2.cpp +++ b/pcbnew/editrack-part2.cpp @@ -231,12 +231,12 @@ void WinEDA_PcbFrame::Other_Layer_Route( TRACK* track, wxDC* DC ) GetScreen()->m_Active_Layer = GetScreen()->m_Route_Layer_BOTTOM; /* Adjust the via layer pair */ - if( Via->Shape() == VIA_ENTERREE ) + if( Via->Shape() == BURIED_VIA ) { Via->SetLayerPair( old_layer, GetScreen()->m_Active_Layer ); } - else if( Via->Shape() == VIA_BORGNE ) //blind via + else if( Via->Shape() == BLIND_VIA ) //blind via { // A revoir! ( la via devrait deboucher sur 1 cote ) Via->SetLayerPair( old_layer, GetScreen()->m_Active_Layer ); diff --git a/pcbnew/router.cpp b/pcbnew/router.cpp index 44832ad76b..6063e3ec19 100644 --- a/pcbnew/router.cpp +++ b/pcbnew/router.cpp @@ -604,9 +604,9 @@ void WinEDA_PcbFrame::ReadAutoroutedTracks( wxDC* DC ) NewVia->m_Width = via_size; NewVia->SetLayer( via_layer1 + (via_layer2 << 4) ); if( NewVia->GetLayer() == 0x0F || NewVia->GetLayer() == 0xF0 ) - NewVia->m_Shape = VIA_NORMALE; + NewVia->m_Shape = THROUGH_VIA; else - NewVia->m_Shape = VIA_ENTERREE; + NewVia->m_Shape = BURIED_VIA; NewVia->Insert( m_Pcb, NULL ); NbTrack++; diff --git a/pcbnew/swap_layers.cpp b/pcbnew/swap_layers.cpp index c0b32600df..a2b5d662f1 100644 --- a/pcbnew/swap_layers.cpp +++ b/pcbnew/swap_layers.cpp @@ -218,7 +218,7 @@ void WinEDA_PcbFrame::Swap_Layers( wxCommandEvent& event ) if( pt_segm->Type() == TYPEVIA ) { SEGVIA* Via = (SEGVIA*) pt_segm; - if( Via->Shape() == VIA_NORMALE ) + if( Via->Shape() == THROUGH_VIA ) continue; int top_layer, bottom_layer; Via->ReturnLayerPair( &top_layer, &bottom_layer );