diff --git a/pcbnew/exporters/export_idf.cpp b/pcbnew/exporters/export_idf.cpp index d77e20d573..4d6debd5aa 100644 --- a/pcbnew/exporters/export_idf.cpp +++ b/pcbnew/exporters/export_idf.cpp @@ -439,10 +439,13 @@ static void idf_export_module( BOARD* aPcb, MODULE* aModule, comp->SetPosition( aModule->GetPosition().x * scale + dx, -aModule->GetPosition().y * scale + dy, rotz, IDF3::LYR_TOP ); - else - comp->SetPosition( aModule->GetPosition().x * scale + dx, - -aModule->GetPosition().y * scale + dy, - rotz, IDF3::LYR_BOTTOM ); + else + comp->SetPosition( aModule->GetPosition().x * scale + dx, + -aModule->GetPosition().y * scale + dy, + rotz, IDF3::LYR_BOTTOM ); + + comp->SetPlacement( IDF3::PS_ECAD ); + } else { diff --git a/utils/idftools/idf_parser.cpp b/utils/idftools/idf_parser.cpp index 864f93a5ad..866c417d52 100644 --- a/utils/idftools/idf_parser.cpp +++ b/utils/idftools/idf_parser.cpp @@ -728,7 +728,8 @@ void IDF3_COMP_OUTLINE_DATA::writePlaceData( std::ofstream& aBoardFile, if( aPlacement == PS_INVALID ) { - ERROR_IDF << "placement invalid; defaulting to PLACED\n"; + ERROR_IDF << "placement invalid (" << aRefDes << ":"; + std::cerr << aPlacement << "); defaulting to PLACED\n"; aPlacement = PS_PLACED; } diff --git a/utils/idftools/vrml_layer.cpp b/utils/idftools/vrml_layer.cpp index 2aa1345d13..65188249f7 100644 --- a/utils/idftools/vrml_layer.cpp +++ b/utils/idftools/vrml_layer.cpp @@ -30,7 +30,7 @@ // a closed loop as assumed for all other outlines. // 3. a scheme is needed to tell a castellated edge from a plain board edge -#include + #include #include #include