From d88eaaf4773600e4442dcd1ce83bb045517988d6 Mon Sep 17 00:00:00 2001 From: Ian McInerney Date: Wed, 11 Nov 2020 00:18:35 +0000 Subject: [PATCH] Fix various compiler and Coverity warnings --- common/widgets/widget_hotkey_list.cpp | 51 ++++++++-------- eeschema/schematic_settings.cpp | 5 +- .../dialogs/dialog_select_net_from_list.cpp | 4 +- pcbnew/drc/drc_engine.cpp | 58 +++++++++---------- pcbnew/router/pns_kicad_iface.cpp | 2 +- pcbnew/undo_redo.cpp | 4 +- pcbnew/zone_filler.cpp | 4 +- 7 files changed, 67 insertions(+), 61 deletions(-) diff --git a/common/widgets/widget_hotkey_list.cpp b/common/widgets/widget_hotkey_list.cpp index 22bd01c489..9f61e6e226 100644 --- a/common/widgets/widget_hotkey_list.cpp +++ b/common/widgets/widget_hotkey_list.cpp @@ -136,7 +136,32 @@ public: } - void OnCharHook( wxKeyEvent& aEvent ) + /** + * End the dialog whether modal or quasimodal + */ + void EndFlexible( int aRtnCode ) + { + if( IsQuasiModal() ) + EndQuasiModal( aRtnCode ); + else + EndModal( aRtnCode ); + } + + + static wxKeyEvent PromptForKey( wxWindow* aParent, const wxString& aName, + const wxString& aCurrentKey ) + { + HK_PROMPT_DIALOG dialog( aParent, wxID_ANY, _( "Set Hotkey" ), aName, aCurrentKey ); + + if( dialog.ShowModal() == wxID_OK ) + return dialog.m_event; + else + return wxKeyEvent(); + } + + +protected: + void OnCharHook( wxKeyEvent& aEvent ) override { // On certain platforms, EVT_CHAR_HOOK is the only handler that receives // certain "special" keys. However, it doesn't always receive "normal" @@ -184,30 +209,6 @@ public: m_event = aEvent; EndFlexible( wxID_OK ); } - - - /** - * End the dialog whether modal or quasimodal - */ - void EndFlexible( int aRtnCode ) - { - if( IsQuasiModal() ) - EndQuasiModal( aRtnCode ); - else - EndModal( aRtnCode ); - } - - - static wxKeyEvent PromptForKey( wxWindow* aParent, const wxString& aName, - const wxString& aCurrentKey ) - { - HK_PROMPT_DIALOG dialog( aParent, wxID_ANY, _( "Set Hotkey" ), aName, aCurrentKey ); - - if( dialog.ShowModal() == wxID_OK ) - return dialog.m_event; - else - return wxKeyEvent(); - } }; diff --git a/eeschema/schematic_settings.cpp b/eeschema/schematic_settings.cpp index 1459124cfa..3f55cfddf6 100644 --- a/eeschema/schematic_settings.cpp +++ b/eeschema/schematic_settings.cpp @@ -41,6 +41,7 @@ SCHEMATIC_SETTINGS::SCHEMATIC_SETTINGS( JSON_SETTINGS* aParent, const std::strin m_TextOffsetRatio( 0.08 ), m_PinSymbolSize( DEFAULT_TEXT_SIZE * IU_PER_MILS / 2 ), m_JunctionSize( DEFAULT_JUNCTION_DIAM * IU_PER_MILS ), + m_JunctionSizeChoice( 3 ), m_IntersheetsRefShow( false ), m_IntersheetsRefFormatShort( false ), m_IntersheetsRefPrefix( DEFAULT_IREF_PREFIX ), @@ -62,7 +63,7 @@ SCHEMATIC_SETTINGS::SCHEMATIC_SETTINGS( JSON_SETTINGS* aParent, const std::strin int defaultJunctionSize = appSettings ? appSettings->m_Drawing.default_junction_size : DEFAULT_JUNCTION_DIAM; int defaultJunctionSizeChoice = - appSettings ? appSettings->m_Drawing.junction_size_choice : 3; + appSettings ? appSettings->m_Drawing.junction_size_choice : 3; bool defaultIntersheetsRefShow = appSettings ? appSettings->m_Drawing.intersheets_ref_show : false; bool defaultIntersheetsRefFormatShort = @@ -114,7 +115,7 @@ SCHEMATIC_SETTINGS::SCHEMATIC_SETTINGS( JSON_SETTINGS* aParent, const std::strin &m_JunctionSize, Mils2iu( defaultJunctionSize ), Mils2iu( 5 ), Mils2iu( 1000 ), 1 / IU_PER_MILS ) ); - // User choice for junction dot size ( e.g. none = 0, smallest = 1, small = 2, etc ) + // User choice for junction dot size ( e.g. none = 0, smallest = 1, small = 2, etc ) m_params.emplace_back(new PARAM("drawing.junction_size_choice", &m_JunctionSizeChoice, defaultJunctionSizeChoice) ); diff --git a/pcbnew/dialogs/dialog_select_net_from_list.cpp b/pcbnew/dialogs/dialog_select_net_from_list.cpp index 5d668cc20a..4950de4cd5 100644 --- a/pcbnew/dialogs/dialog_select_net_from_list.cpp +++ b/pcbnew/dialogs/dialog_select_net_from_list.cpp @@ -1454,7 +1454,9 @@ std::unique_ptr DIALOG_SELECT_NET_FROM_L void DIALOG_SELECT_NET_FROM_LIST::buildNetsList() { - wxCHECK( m_brd, /* void */ ); + // Only build the list of nets if there is a board present + if( !m_brd ) + return; m_in_build_nets_list = true; diff --git a/pcbnew/drc/drc_engine.cpp b/pcbnew/drc/drc_engine.cpp index c8d47f30ba..80c182d09b 100644 --- a/pcbnew/drc/drc_engine.cpp +++ b/pcbnew/drc/drc_engine.cpp @@ -208,25 +208,25 @@ void DRC_ENGINE::loadImplicitRules() { wxString ncName = nc->GetName(); - DRC_RULE* rule; + DRC_RULE* netclassRule; wxString expr; if( nc->GetClearance() || nc->GetTrackWidth() ) { - rule = new DRC_RULE; - rule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName ); - rule->m_Implicit = true; + netclassRule = new DRC_RULE; + netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName ); + netclassRule->m_Implicit = true; expr = wxString::Format( "A.NetClass == '%s'", ncName ); - rule->m_Condition = new DRC_RULE_CONDITION( expr ); - netclassClearanceRules.push_back( rule ); + netclassRule->m_Condition = new DRC_RULE_CONDITION( expr ); + netclassClearanceRules.push_back( netclassRule ); if( nc->GetClearance() ) { DRC_CONSTRAINT constraint( CLEARANCE_CONSTRAINT ); constraint.Value().SetMin( std::max( bds.m_MinClearance, nc->GetClearance() ) ); - rule->AddConstraint( constraint ); + netclassRule->AddConstraint( constraint ); } if( nc->GetTrackWidth() ) @@ -234,27 +234,27 @@ void DRC_ENGINE::loadImplicitRules() DRC_CONSTRAINT constraint( TRACK_WIDTH_CONSTRAINT ); constraint.Value().SetMin( bds.m_TrackMinWidth ); constraint.Value().SetOpt( nc->GetTrackWidth() ); - rule->AddConstraint( constraint ); + netclassRule->AddConstraint( constraint ); } } if( nc->GetDiffPairWidth() || nc->GetDiffPairGap() ) { - rule = new DRC_RULE; - rule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName ); - rule->m_Implicit = true; + netclassRule = new DRC_RULE; + netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName ); + netclassRule->m_Implicit = true; expr = wxString::Format( "A.NetClass == '%s' && A.isDiffPair()", ncName ); - rule->m_Condition = new DRC_RULE_CONDITION( expr ); - netclassItemSpecificRules.push_back( rule ); + netclassRule->m_Condition = new DRC_RULE_CONDITION( expr ); + netclassItemSpecificRules.push_back( netclassRule ); if( nc->GetDiffPairWidth() ) { DRC_CONSTRAINT constraint( TRACK_WIDTH_CONSTRAINT ); constraint.Value().SetMin( bds.m_TrackMinWidth ); constraint.Value().SetOpt( nc->GetDiffPairWidth() ); - rule->AddConstraint( constraint ); + netclassRule->AddConstraint( constraint ); } if( nc->GetDiffPairGap() ) @@ -262,27 +262,27 @@ void DRC_ENGINE::loadImplicitRules() DRC_CONSTRAINT constraint( DIFF_PAIR_GAP_CONSTRAINT ); constraint.Value().SetMin( std::max( bds.m_MinClearance, nc->GetClearance() ) ); constraint.Value().SetOpt( nc->GetDiffPairGap() ); - rule->AddConstraint( constraint ); + netclassRule->AddConstraint( constraint ); } } if( nc->GetViaDiameter() || nc->GetViaDrill() ) { - rule = new DRC_RULE; - rule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName ); - rule->m_Implicit = true; + netclassRule = new DRC_RULE; + netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName ); + netclassRule->m_Implicit = true; expr = wxString::Format( "A.NetClass == '%s' && A.Via_Type != 'Micro'", ncName ); - rule->m_Condition = new DRC_RULE_CONDITION( expr ); - netclassItemSpecificRules.push_back( rule ); + netclassRule->m_Condition = new DRC_RULE_CONDITION( expr ); + netclassItemSpecificRules.push_back( netclassRule ); if( nc->GetViaDiameter() ) { DRC_CONSTRAINT constraint( VIA_DIAMETER_CONSTRAINT ); constraint.Value().SetMin( bds.m_ViasMinSize ); constraint.Value().SetOpt( nc->GetViaDiameter() ); - rule->AddConstraint( constraint ); + netclassRule->AddConstraint( constraint ); } if( nc->GetViaDrill() ) @@ -290,27 +290,27 @@ void DRC_ENGINE::loadImplicitRules() DRC_CONSTRAINT constraint( HOLE_SIZE_CONSTRAINT ); constraint.Value().SetMin( bds.m_MinThroughDrill ); constraint.Value().SetOpt( nc->GetViaDrill() ); - rule->AddConstraint( constraint ); + netclassRule->AddConstraint( constraint ); } } if( nc->GetuViaDiameter() || nc->GetuViaDrill() ) { - rule = new DRC_RULE; - rule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName ); - rule->m_Implicit = true; + netclassRule = new DRC_RULE; + netclassRule->m_Name = wxString::Format( _( "netclass '%s'" ), ncName ); + netclassRule->m_Implicit = true; expr = wxString::Format( "A.NetClass == '%s' && A.Via_Type == 'Micro'", ncName ); - rule->m_Condition = new DRC_RULE_CONDITION( expr ); - netclassItemSpecificRules.push_back( rule ); + netclassRule->m_Condition = new DRC_RULE_CONDITION( expr ); + netclassItemSpecificRules.push_back( netclassRule ); if( nc->GetuViaDiameter() ) { DRC_CONSTRAINT constraint( VIA_DIAMETER_CONSTRAINT ); constraint.Value().SetMin( bds.m_MicroViasMinSize ); constraint.Value().SetMin( nc->GetuViaDiameter() ); - rule->AddConstraint( constraint ); + netclassRule->AddConstraint( constraint ); } if( nc->GetuViaDrill() ) @@ -318,7 +318,7 @@ void DRC_ENGINE::loadImplicitRules() DRC_CONSTRAINT constraint( HOLE_SIZE_CONSTRAINT ); constraint.Value().SetMin( bds.m_MicroViasMinDrill ); constraint.Value().SetOpt( nc->GetuViaDrill() ); - rule->AddConstraint( constraint ); + netclassRule->AddConstraint( constraint ); } } }; diff --git a/pcbnew/router/pns_kicad_iface.cpp b/pcbnew/router/pns_kicad_iface.cpp index 2fb29d9a78..8f08320457 100644 --- a/pcbnew/router/pns_kicad_iface.cpp +++ b/pcbnew/router/pns_kicad_iface.cpp @@ -224,7 +224,7 @@ bool PNS_PCBNEW_RULE_RESOLVER::QueryConstraint( PNS::CONSTRAINT_TYPE aType, DRC_CONSTRAINT hostConstraint; // A track being routed may not have a BOARD_ITEM associated yet. - if( !parentA ) + if( aItemA && !parentA ) { switch( aItemA->Kind() ) { diff --git a/pcbnew/undo_redo.cpp b/pcbnew/undo_redo.cpp index 4af2abf5cd..0459e63712 100644 --- a/pcbnew/undo_redo.cpp +++ b/pcbnew/undo_redo.cpp @@ -503,7 +503,9 @@ void PCB_BASE_EDIT_FRAME::PutDataInPreviousState( PICKED_ITEMS_LIST* aList, bool break; case UNDO_REDO::UNGROUP: - group->AddItem( static_cast( eda_item ) ); + if( group ) + group->AddItem( static_cast( eda_item ) ); + break; case UNDO_REDO::MOVED: diff --git a/pcbnew/zone_filler.cpp b/pcbnew/zone_filler.cpp index 343a09f1af..a2b6db9434 100644 --- a/pcbnew/zone_filler.cpp +++ b/pcbnew/zone_filler.cpp @@ -683,9 +683,9 @@ void ZONE_FILLER::buildCopperItemClearances( const ZONE_CONTAINER* aZone, PCB_LA auto evalRulesForItems = [&bds]( DRC_CONSTRAINT_TYPE_T aConstraint, const BOARD_ITEM* a, const BOARD_ITEM* b, - PCB_LAYER_ID aLayer ) -> int + PCB_LAYER_ID aEvalLayer ) -> int { - DRC_CONSTRAINT c = bds.m_DRCEngine->EvalRulesForItems( aConstraint, a, b, aLayer ); + DRC_CONSTRAINT c = bds.m_DRCEngine->EvalRulesForItems( aConstraint, a, b, aEvalLayer ); return c.Value().HasMin() ? c.Value().Min() : 0; };