From d9eb15c9fa7c00741565308c612f4bc6fb5b3850 Mon Sep 17 00:00:00 2001 From: Maciej Suminski Date: Tue, 13 May 2014 11:22:51 +0200 Subject: [PATCH] Moved NETCLASSES to BOARD_DESIGN_SETTINGS. Most of the changes are just adding GetDesignSettings() before every occurence of m_NetClasses. More complex changes: class_netclass.cpp - NETCLASS does not store the pointer to the parent BOARD anymore. Added function SetParams( BOARD_DESIGN_SETTINGS& ). class_netclass.h - Removed GetTrackMinWidth(), GetViaMinDiameter(), GetViaMinDrill(), GetuViaMinDiameter(), GetuViaMinDrill() as they were refering to BOARD_DESIGN_SETTINGS anyway (they are not net class specific). kicad_plugin.cpp - filters out empty nets (that are anyway not saved) when storing net class information. Previously it was done in NETCLASS::Format() function. --- include/class_board_design_settings.h | 61 ++++++++ pcbnew/autorouter/routing_matrix.cpp | 2 +- pcbnew/autorouter/solve.cpp | 2 +- pcbnew/class_board.cpp | 112 +-------------- pcbnew/class_board.h | 65 --------- pcbnew/class_board_connected_item.cpp | 4 +- pcbnew/class_board_design_settings.cpp | 97 +++++++++++++ pcbnew/class_module.cpp | 2 +- pcbnew/class_netclass.cpp | 130 +++++------------- pcbnew/class_netclass.h | 50 ++++--- pcbnew/dialogs/dialog_design_rules.cpp | 67 ++++----- pcbnew/dialogs/dialog_design_rules.h | 2 +- .../dialog_global_edit_tracks_and_vias.cpp | 21 +-- pcbnew/dialogs/dialog_plot.cpp | 4 +- pcbnew/drc.cpp | 2 +- pcbnew/drc_clearance_test_functions.cpp | 7 +- pcbnew/eagle_plugin.cpp | 4 +- pcbnew/edit_track_width.cpp | 2 +- pcbnew/editrack.cpp | 2 +- pcbnew/files.cpp | 6 +- pcbnew/kicad_plugin.cpp | 107 ++++++++------ pcbnew/legacy_plugin.cpp | 16 +-- pcbnew/legacy_plugin.h | 2 +- pcbnew/onleftclick.cpp | 2 +- pcbnew/onrightclick.cpp | 6 +- pcbnew/pcb_parser.cpp | 18 +-- pcbnew/router/pns_router.cpp | 2 +- pcbnew/router/router_tool.cpp | 4 +- pcbnew/specctra_export.cpp | 9 +- ...nvert_brd_items_to_polygons_with_Boost.cpp | 2 +- ...ones_convert_to_polygons_aux_functions.cpp | 2 +- 31 files changed, 378 insertions(+), 434 deletions(-) diff --git a/include/class_board_design_settings.h b/include/class_board_design_settings.h index 9fce5db845..a22f3c5bb6 100644 --- a/include/class_board_design_settings.h +++ b/include/class_board_design_settings.h @@ -8,6 +8,7 @@ #include // NB_COLORS #include #include +#include #include /** @@ -61,6 +62,9 @@ public: /// Track width list std::vector m_TrackWidthList; + /// List of current netclasses. There is always the default netclass. + NETCLASSES m_NetClasses; + bool m_MicroViasAllowed; ///< true to allow micro vias bool m_BlindBuriedViaAllowed; ///< true to allow blind/buried vias VIATYPE_T m_CurrentViaType; ///< via type (VIA_BLIND_BURIED, VIA_THROUGH VIA_MICROVIA) @@ -97,6 +101,56 @@ public: BOARD_DESIGN_SETTINGS(); + /** + * Function SetCurrentNetClassName + * sets the current net class name to \a aName. + * + * @param aName is a reference to a wxString object containing the current net class name. + */ + void SetCurrentNetClassName( const wxString& aName ) { m_currentNetClassName = aName; } + + /** + * Function GetCurrentNetClassName + * @return the current net class name. + */ + const wxString& GetCurrentNetClassName() const { return m_currentNetClassName; } + + /** + * Function SetCurrentNetClass + * Must be called after a netclass selection (or after a netclass parameter change + * Initialize vias and tracks values displayed in comb boxes of the auxiliary toolbar + * and some others parameters (netclass name ....) + * @param aNetClassName = the new netclass name + * @return true if lists of tracks and vias sizes are modified + */ + bool SetCurrentNetClass( const wxString& aNetClassName ); + + /** + * Function GetBiggestClearanceValue + * @return the biggest clearance value found in NetClasses list + */ + int GetBiggestClearanceValue(); + + /** + * Function GetSmallestClearanceValue + * @return the smallest clearance value found in NetClasses list + */ + int GetSmallestClearanceValue(); + + /** + * Function GetCurrentMicroViaSize + * @return the current micro via size, + * that is the current netclass value + */ + int GetCurrentMicroViaSize(); + + /** + * Function GetCurrentMicroViaDrill + * @return the current micro via drill, + * that is the current netclass value + */ + int GetCurrentMicroViaDrill(); + /** * Function GetTrackWidthIndex * @return the current track width list index. @@ -413,6 +467,13 @@ private: LAYER_MSK m_visibleLayers; ///< Bit-mask for layer visibility int m_visibleElements; ///< Bit-mask for element category visibility int m_boardThickness; ///< Board thickness for 3D viewer + + /// Current net class name used to display netclass info. + /// This is also the last used netclass after starting a track. + wxString m_currentNetClassName; + + void formatNetClass( NETCLASS* aNetClass, OUTPUTFORMATTER* aFormatter, int aNestLevel, + int aControlBits ) const throw( IO_ERROR ); }; #endif // BOARD_DESIGN_SETTINGS_H_ diff --git a/pcbnew/autorouter/routing_matrix.cpp b/pcbnew/autorouter/routing_matrix.cpp index 8449c90bc1..9d87b52bda 100644 --- a/pcbnew/autorouter/routing_matrix.cpp +++ b/pcbnew/autorouter/routing_matrix.cpp @@ -201,7 +201,7 @@ void PlaceCells( BOARD* aPcb, int net_code, int flag ) LAYER_MSK layerMask; // use the default NETCLASS? - NETCLASS* nc = aPcb->m_NetClasses.GetDefault(); + NETCLASS* nc = aPcb->GetDesignSettings().m_NetClasses.GetDefault(); int trackWidth = nc->GetTrackWidth(); int clearance = nc->GetClearance(); diff --git a/pcbnew/autorouter/solve.cpp b/pcbnew/autorouter/solve.cpp index 9da2804e9f..c1f66b5423 100644 --- a/pcbnew/autorouter/solve.cpp +++ b/pcbnew/autorouter/solve.cpp @@ -280,7 +280,7 @@ int PCB_EDIT_FRAME::Solve( wxDC* DC, int aLayersCount ) m_canvas->SetAbortRequest( false ); - s_Clearance = GetBoard()->m_NetClasses.GetDefault()->GetClearance(); + s_Clearance = GetBoard()->GetDesignSettings().m_NetClasses.GetDefault()->GetClearance(); // Prepare the undo command info s_ItemsListPicker.ClearListAndDeleteItems(); // Should not be necessary, but... diff --git a/pcbnew/class_board.cpp b/pcbnew/class_board.cpp index c5784848d7..c05474d29f 100644 --- a/pcbnew/class_board.cpp +++ b/pcbnew/class_board.cpp @@ -66,8 +66,7 @@ wxPoint BOARD_ITEM::ZeroOffset( 0, 0 ); BOARD::BOARD() : BOARD_ITEM( (BOARD_ITEM*) NULL, PCB_T ), m_NetInfo( this ), - m_paper( PAGE_INFO::A4 ), - m_NetClasses( this ) + m_paper( PAGE_INFO::A4 ) { // we have not loaded a board yet, assume latest until then. m_fileFormatVersionAtLoad = LEGACY_BOARD_FILE_VERSION; @@ -92,19 +91,12 @@ BOARD::BOARD() : m_Layer[layer].m_Type = LT_UNDEFINED; } - m_NetClasses.GetDefault()->SetDescription( _( "This is the default net class." ) ); + NETCLASS* defaultClass = m_designSettings.m_NetClasses.GetDefault(); + defaultClass->SetDescription( _( "This is the default net class." ) ); - m_designSettings.SetViaSizeIndex( 0 ); - m_designSettings.SetTrackWidthIndex( 0 ); - - /* Dick 5-Feb-2012: this seems unnecessary. I don't believe the comment - near line 70 of class_netclass.cpp. I stepped through with debugger. - Perhaps something else is at work, it is not a constructor race. // Initialize default values in default netclass. - */ - m_NetClasses.GetDefault()->SetParams(); - - SetCurrentNetClass( m_NetClasses.GetDefault()->GetName() ); + defaultClass->SetParams( m_designSettings ); + m_designSettings.SetCurrentNetClass( defaultClass->GetName() ); // Set sensible initial values for custom track width & via size m_designSettings.UseCustomTrackViaSize( false ); @@ -319,100 +311,6 @@ void BOARD::PopHighLight() } -bool BOARD::SetCurrentNetClass( const wxString& aNetClassName ) -{ - NETCLASS* netClass = m_NetClasses.Find( aNetClassName ); - bool lists_sizes_modified = false; - - // if not found (should not happen) use the default - if( netClass == NULL ) - netClass = m_NetClasses.GetDefault(); - - m_currentNetClassName = netClass->GetName(); - - // Initialize others values: - if( m_designSettings.m_ViasDimensionsList.size() == 0 ) - { - VIA_DIMENSION viadim; - lists_sizes_modified = true; - m_designSettings.m_ViasDimensionsList.push_back( viadim ); - } - - if( m_designSettings.m_TrackWidthList.size() == 0 ) - { - lists_sizes_modified = true; - m_designSettings.m_TrackWidthList.push_back( 0 ); - } - - /* note the m_ViasDimensionsList[0] and m_TrackWidthList[0] values - * are always the Netclass values - */ - if( m_designSettings.m_ViasDimensionsList[0].m_Diameter != netClass->GetViaDiameter() ) - lists_sizes_modified = true; - - m_designSettings.m_ViasDimensionsList[0].m_Diameter = netClass->GetViaDiameter(); - - if( m_designSettings.m_TrackWidthList[0] != netClass->GetTrackWidth() ) - lists_sizes_modified = true; - - m_designSettings.m_TrackWidthList[0] = netClass->GetTrackWidth(); - - if( m_designSettings.GetViaSizeIndex() >= m_designSettings.m_ViasDimensionsList.size() ) - m_designSettings.SetViaSizeIndex( m_designSettings.m_ViasDimensionsList.size() ); - - if( m_designSettings.GetTrackWidthIndex() >= m_designSettings.m_TrackWidthList.size() ) - m_designSettings.SetTrackWidthIndex( m_designSettings.m_TrackWidthList.size() ); - - return lists_sizes_modified; -} - - -int BOARD::GetBiggestClearanceValue() -{ - int clearance = m_NetClasses.GetDefault()->GetClearance(); - - //Read list of Net Classes - for( NETCLASSES::const_iterator nc = m_NetClasses.begin(); nc != m_NetClasses.end(); nc++ ) - { - NETCLASS* netclass = nc->second; - clearance = std::max( clearance, netclass->GetClearance() ); - } - - return clearance; -} - - -int BOARD::GetSmallestClearanceValue() -{ - int clearance = m_NetClasses.GetDefault()->GetClearance(); - - //Read list of Net Classes - for( NETCLASSES::const_iterator nc = m_NetClasses.begin(); nc != m_NetClasses.end(); nc++ ) - { - NETCLASS* netclass = nc->second; - clearance = std::min( clearance, netclass->GetClearance() ); - } - - return clearance; -} - - -int BOARD::GetCurrentMicroViaSize() -{ - NETCLASS* netclass = m_NetClasses.Find( m_currentNetClassName ); - - return netclass->GetuViaDiameter(); -} - - -int BOARD::GetCurrentMicroViaDrill() -{ - NETCLASS* netclass = m_NetClasses.Find( m_currentNetClassName ); - - return netclass->GetuViaDrill(); -} - - bool BOARD::SetLayer( LAYER_NUM aIndex, const LAYER& aLayer ) { if( aIndex < NB_COPPER_LAYERS ) diff --git a/pcbnew/class_board.h b/pcbnew/class_board.h index a728061ba0..ccb3589ccf 100644 --- a/pcbnew/class_board.h +++ b/pcbnew/class_board.h @@ -208,10 +208,6 @@ private: /// Number of unconnected nets in the current rats nest. int m_unconnectedNetCount; - /// Current net class name used to display netclass info. - /// This is also the last used netclass after starting a track. - wxString m_currentNetClassName; - /** * Function chainMarkedSegments * is used by MarkTrace() to set the BUSY flag of connected segments of the trace @@ -223,10 +219,6 @@ private: */ void chainMarkedSegments( wxPoint aPosition, LAYER_MSK aLayerMask, TRACK_PTRS* aList ); - void formatNetClass( NETCLASS* aNetClass, OUTPUTFORMATTER* aFormatter, int aNestLevel, - int aControlBits ) const - throw( IO_ERROR ); - public: void SetFileName( const wxString& aFileName ) { m_fileName = aFileName; } @@ -250,9 +242,6 @@ public: /// zone contour currently in progress ZONE_CONTAINER* m_CurrentZoneContour; - /// List of current netclasses. There is always the default netclass. - NETCLASSES m_NetClasses; - BOARD(); ~BOARD(); @@ -742,20 +731,6 @@ public: */ void SetUnconnectedNetCount( unsigned aCount ) { m_unconnectedNetCount = aCount; } - /** - * Function SetCurrentNetClassName - * sets the current net class name to \a aName. - * - * @param aName is a reference to a wxString object containing the current net class name. - */ - void SetCurrentNetClassName( const wxString& aName ) { m_currentNetClassName = aName; } - - /** - * Function GetCurrentNetClassName - * @return the current net class name. - */ - const wxString& GetCurrentNetClassName() const { return m_currentNetClassName; } - /** * Function GetPadCount * @return the number of pads in board @@ -964,10 +939,6 @@ public: */ int SortedNetnamesList( wxArrayString& aNames, bool aSortbyPadsCount ); - /************************************** - * Functions related to NetClasses: - **************************************/ - /** * Function SynchronizeNetsAndNetClasses * copies NETCLASS info to each NET, based on NET membership in a NETCLASS. @@ -977,42 +948,6 @@ public: */ void SynchronizeNetsAndNetClasses(); - /** - * Function SetCurrentNetClass - * Must be called after a netclass selection (or after a netclass parameter change - * Initialize vias and tracks values displayed in comb boxes of the auxiliary toolbar - * and some others parameters (netclass name ....) - * @param aNetClassName = the new netclass name - * @return true if lists of tracks and vias sizes are modified - */ - bool SetCurrentNetClass( const wxString& aNetClassName ); - - /** - * Function GetBiggestClearanceValue - * @return the biggest clearance value found in NetClasses list - */ - int GetBiggestClearanceValue(); - - /** - * Function GetSmallestClearanceValue - * @return the smallest clearance value found in NetClasses list - */ - int GetSmallestClearanceValue(); - - /** - * Function GetCurrentMicroViaSize - * @return the current micro via size, - * that is the current netclass value - */ - int GetCurrentMicroViaSize(); - - /** - * Function GetCurrentMicroViaDrill - * @return the current micro via drill, - * that is the current netclass value - */ - int GetCurrentMicroViaDrill(); - /***************************************************************************/ wxString GetClass() const diff --git a/pcbnew/class_board_connected_item.cpp b/pcbnew/class_board_connected_item.cpp index 0248131d35..9aaa6d14ad 100644 --- a/pcbnew/class_board_connected_item.cpp +++ b/pcbnew/class_board_connected_item.cpp @@ -144,7 +144,7 @@ NETCLASS* BOARD_CONNECTED_ITEM::GetNetClass() const if( netclass ) return netclass; else - return board->m_NetClasses.GetDefault(); + return board->GetDesignSettings().m_NetClasses.GetDefault(); } @@ -158,7 +158,7 @@ wxString BOARD_CONNECTED_ITEM::GetNetClassName() const else { BOARD* board = GetBoard(); - name = board->m_NetClasses.GetDefault()->GetName(); + name = board->GetDesignSettings().m_NetClasses.GetDefault()->GetName(); } return name; diff --git a/pcbnew/class_board_design_settings.cpp b/pcbnew/class_board_design_settings.cpp index a727c904f9..aac977d827 100644 --- a/pcbnew/class_board_design_settings.cpp +++ b/pcbnew/class_board_design_settings.cpp @@ -102,6 +102,9 @@ BOARD_DESIGN_SETTINGS::BOARD_DESIGN_SETTINGS() : // Layer thickness for 3D viewer m_boardThickness = Millimeter2iu( DEFAULT_BOARD_THICKNESS_MM ); + + m_viaSizeIndex = 0; + m_trackWidthIndex = 0; } // Add parameters to save in project config. @@ -171,6 +174,100 @@ void BOARD_DESIGN_SETTINGS::AppendConfigs( PARAM_CFG_ARRAY* aResult ) } +bool BOARD_DESIGN_SETTINGS::SetCurrentNetClass( const wxString& aNetClassName ) +{ + NETCLASS* netClass = m_NetClasses.Find( aNetClassName ); + bool lists_sizes_modified = false; + + // if not found (should not happen) use the default + if( netClass == NULL ) + netClass = m_NetClasses.GetDefault(); + + m_currentNetClassName = netClass->GetName(); + + // Initialize others values: + if( m_ViasDimensionsList.size() == 0 ) + { + VIA_DIMENSION viadim; + lists_sizes_modified = true; + m_ViasDimensionsList.push_back( viadim ); + } + + if( m_TrackWidthList.size() == 0 ) + { + lists_sizes_modified = true; + m_TrackWidthList.push_back( 0 ); + } + + /* note the m_ViasDimensionsList[0] and m_TrackWidthList[0] values + * are always the Netclass values + */ + if( m_ViasDimensionsList[0].m_Diameter != netClass->GetViaDiameter() ) + lists_sizes_modified = true; + + m_ViasDimensionsList[0].m_Diameter = netClass->GetViaDiameter(); + + if( m_TrackWidthList[0] != netClass->GetTrackWidth() ) + lists_sizes_modified = true; + + m_TrackWidthList[0] = netClass->GetTrackWidth(); + + if( GetViaSizeIndex() >= m_ViasDimensionsList.size() ) + SetViaSizeIndex( m_ViasDimensionsList.size() ); + + if( GetTrackWidthIndex() >= m_TrackWidthList.size() ) + SetTrackWidthIndex( m_TrackWidthList.size() ); + + return lists_sizes_modified; +} + + +int BOARD_DESIGN_SETTINGS::GetBiggestClearanceValue() +{ + int clearance = m_NetClasses.GetDefault()->GetClearance(); + + //Read list of Net Classes + for( NETCLASSES::const_iterator nc = m_NetClasses.begin(); nc != m_NetClasses.end(); nc++ ) + { + NETCLASS* netclass = nc->second; + clearance = std::max( clearance, netclass->GetClearance() ); + } + + return clearance; +} + + +int BOARD_DESIGN_SETTINGS::GetSmallestClearanceValue() +{ + int clearance = m_NetClasses.GetDefault()->GetClearance(); + + //Read list of Net Classes + for( NETCLASSES::const_iterator nc = m_NetClasses.begin(); nc != m_NetClasses.end(); nc++ ) + { + NETCLASS* netclass = nc->second; + clearance = std::min( clearance, netclass->GetClearance() ); + } + + return clearance; +} + + +int BOARD_DESIGN_SETTINGS::GetCurrentMicroViaSize() +{ + NETCLASS* netclass = m_NetClasses.Find( m_currentNetClassName ); + + return netclass->GetuViaDiameter(); +} + + +int BOARD_DESIGN_SETTINGS::GetCurrentMicroViaDrill() +{ + NETCLASS* netclass = m_NetClasses.Find( m_currentNetClassName ); + + return netclass->GetuViaDrill(); +} + + void BOARD_DESIGN_SETTINGS::SetViaSizeIndex( unsigned aIndex ) { if( aIndex >= m_ViasDimensionsList.size() ) diff --git a/pcbnew/class_module.cpp b/pcbnew/class_module.cpp index bc55907cb3..5673c06f2d 100644 --- a/pcbnew/class_module.cpp +++ b/pcbnew/class_module.cpp @@ -447,7 +447,7 @@ const EDA_RECT MODULE::GetBoundingBox() const // Add the Clearance shape size: (shape around the pads when the // clearance is shown. Not optimized, but the draw cost is small // (perhaps smaller than optimization). - int biggest_clearance = GetBoard()->GetBiggestClearanceValue(); + int biggest_clearance = GetBoard()->GetDesignSettings().GetBiggestClearanceValue(); area.Inflate( biggest_clearance ); return area; diff --git a/pcbnew/class_netclass.cpp b/pcbnew/class_netclass.cpp index 73729324ef..daa72ff32b 100644 --- a/pcbnew/class_netclass.cpp +++ b/pcbnew/class_netclass.cpp @@ -39,59 +39,43 @@ const wxChar NETCLASS::Default[] = wxT( "Default" ); // Initial values for netclass initialization -int NETCLASS::DEFAULT_CLEARANCE = DMils2iu( 100 ); // track to track and track to pads clearance -int NETCLASS::DEFAULT_VIA_DRILL = DMils2iu( 250 ); // default via drill -int NETCLASS::DEFAULT_UVIA_DRILL = DMils2iu( 50 ); // micro via drill +const int NETCLASS::DEFAULT_CLEARANCE = DMils2iu( 100 ); // track to track and track to pads clearance +const int NETCLASS::DEFAULT_VIA_DRILL = DMils2iu( 250 ); // default via drill +const int NETCLASS::DEFAULT_UVIA_DRILL = DMils2iu( 50 ); // micro via drill -NETCLASS::NETCLASS( BOARD* aParent, const wxString& aName, const NETCLASS* initialParameters ) : - m_Parent( aParent ), +NETCLASS::NETCLASS( const wxString& aName ) : m_Name( aName ) { - // use initialParameters if not NULL, else set the initial - // parameters from boardDesignSettings (try to change this) - SetParams( initialParameters ); + // Default settings + SetClearance( DEFAULT_CLEARANCE ); + SetViaDrill( DEFAULT_VIA_DRILL ); + SetuViaDrill( DEFAULT_UVIA_DRILL ); } -void NETCLASS::SetParams( const NETCLASS* defaults ) +void NETCLASS::SetParams( const NETCLASS& aDefaults ) { - if( defaults ) - { - SetClearance( defaults->GetClearance() ); - SetTrackWidth( defaults->GetTrackWidth() ); - SetViaDiameter( defaults->GetViaDiameter() ); - SetViaDrill( defaults->GetViaDrill() ); - SetuViaDiameter( defaults->GetuViaDiameter() ); - SetuViaDrill( defaults->GetuViaDrill() ); - } - else - { + SetClearance( aDefaults.GetClearance() ); + SetTrackWidth( aDefaults.GetTrackWidth() ); + SetViaDiameter( aDefaults.GetViaDiameter() ); + SetViaDrill( aDefaults.GetViaDrill() ); + SetuViaDiameter( aDefaults.GetuViaDiameter() ); + SetuViaDrill( aDefaults.GetuViaDrill() ); +} -/* Dick 5-Feb-2012: I do not believe this comment to be true with current code. - It is certainly not a constructor race. Normally items are initialized - within a class according to the order of their appearance. - // Note: - // We use m_Parent->GetDesignSettings() to get some default values - // But when this function is called when instantiating a BOARD class, - // by the NETCLASSES constructor that calls NETCLASS constructor, - // the BOARD constructor (see BOARD::BOARD) is not yet run, - // and BOARD::m_designSettings contains not yet initialized values. - // So inside the BOARD constructor itself, you SHOULD recall SetParams -*/ +void NETCLASS::SetParams( const BOARD_DESIGN_SETTINGS& aSettings ) +{ + SetTrackWidth( aSettings.m_TrackMinWidth ); + SetViaDiameter( aSettings.m_ViasMinSize ); + SetuViaDiameter( aSettings.m_MicroViasMinSize ); - const BOARD_DESIGN_SETTINGS& g = m_Parent->GetDesignSettings(); - - SetTrackWidth( g.m_TrackMinWidth ); - SetViaDiameter( g.m_ViasMinSize ); - SetuViaDiameter( g.m_MicroViasMinSize ); - - // Use default values for next parameters: - SetClearance( DEFAULT_CLEARANCE ); - SetViaDrill( DEFAULT_VIA_DRILL ); - SetuViaDrill( DEFAULT_UVIA_DRILL ); - } + // TODO: BOARD_DESIGN_SETTINGS may provide the following parameters - should it? + // Use default values for next parameters: + SetClearance( DEFAULT_CLEARANCE ); + SetViaDrill( DEFAULT_VIA_DRILL ); + SetuViaDrill( DEFAULT_UVIA_DRILL ); } @@ -100,9 +84,8 @@ NETCLASS::~NETCLASS() } -NETCLASSES::NETCLASSES( BOARD* aParent ) : - m_Parent( aParent ), - m_Default( aParent, NETCLASS::Default ) +NETCLASSES::NETCLASSES() : + m_Default( NETCLASS::Default ) { } @@ -198,7 +181,7 @@ NETCLASS* NETCLASSES::Find( const wxString& aName ) const void BOARD::SynchronizeNetsAndNetClasses() { - // D(printf("start\n");) // simple performance/timing indicator. + NETCLASSES& netClasses = m_designSettings.m_NetClasses; // set all NETs to the default NETCLASS, then later override some // as we go through the NETCLASSes. @@ -206,19 +189,19 @@ void BOARD::SynchronizeNetsAndNetClasses() for( NETINFO_LIST::iterator net( m_NetInfo.begin() ), netEnd( m_NetInfo.end() ); net != netEnd; ++net ) { - net->SetClass( m_NetClasses.GetDefault() ); + net->SetClass( netClasses.GetDefault() ); } // Add netclass name and pointer to nets. If a net is in more than one netclass, // set the net's name and pointer to only the first netclass. Subsequent // and therefore bogus netclass memberships will be deleted in logic below this loop. - for( NETCLASSES::iterator clazz=m_NetClasses.begin(); clazz!=m_NetClasses.end(); ++clazz ) + for( NETCLASSES::iterator clazz = netClasses.begin(); clazz != netClasses.end(); ++clazz ) { NETCLASS* netclass = clazz->second; - for( NETCLASS::iterator member = netclass->begin(); member!=netclass->end(); ++member ) + for( NETCLASS::iterator member = netclass->begin(); member != netclass->end(); ++member ) { - const wxString& netname = *member; + const wxString& netname = *member; // although this overall function seems to be adequately fast, // FindNet( wxString ) uses now a fast binary search and is fast @@ -237,14 +220,14 @@ void BOARD::SynchronizeNetsAndNetClasses() // contain netnames that do not exist, by deleting all netnames from // every netclass and re-adding them. - for( NETCLASSES::iterator clazz=m_NetClasses.begin(); clazz!=m_NetClasses.end(); ++clazz ) + for( NETCLASSES::iterator clazz = netClasses.begin(); clazz != netClasses.end(); ++clazz ) { NETCLASS* netclass = clazz->second; netclass->Clear(); } - m_NetClasses.GetDefault()->Clear(); + netClasses.GetDefault()->Clear(); for( NETINFO_LIST::iterator net( m_NetInfo.begin() ), netEnd( m_NetInfo.end() ); net != netEnd; ++net ) @@ -253,14 +236,12 @@ void BOARD::SynchronizeNetsAndNetClasses() // because of the std:map<> this should be fast, and because of // prior logic, netclass should not be NULL. - NETCLASS* netclass = m_NetClasses.Find( classname ); + NETCLASS* netclass = netClasses.Find( classname ); wxASSERT( netclass ); netclass->Add( net->GetNetname() ); } - - // D(printf("stop\n");) } @@ -286,36 +267,6 @@ void NETCLASS::Show( int nestLevel, std::ostream& os ) const #endif -int NETCLASS::GetTrackMinWidth() const -{ - return m_Parent->GetDesignSettings().m_TrackMinWidth; -} - - -int NETCLASS::GetViaMinDiameter() const -{ - return m_Parent->GetDesignSettings().m_ViasMinSize; -} - - -int NETCLASS::GetViaMinDrill() const -{ - return m_Parent->GetDesignSettings().m_ViasMinDrill; -} - - -int NETCLASS::GetuViaMinDiameter() const -{ - return m_Parent->GetDesignSettings().m_MicroViasMinSize; -} - - -int NETCLASS::GetuViaMinDrill() const -{ - return m_Parent->GetDesignSettings().m_MicroViasMinDrill; -} - - void NETCLASS::Format( OUTPUTFORMATTER* aFormatter, int aNestLevel, int aControlBits ) const throw( IO_ERROR ) { @@ -333,14 +284,7 @@ void NETCLASS::Format( OUTPUTFORMATTER* aFormatter, int aNestLevel, int aControl aFormatter->Print( aNestLevel+1, "(uvia_drill %s)\n", FMT_IU( GetuViaDrill() ).c_str() ); for( NETCLASS::const_iterator it = begin(); it != end(); ++it ) - { - NETINFO_ITEM* netinfo = m_Parent->FindNet( *it ); - - if( netinfo && netinfo->GetNodesCount() > 0 ) - { - aFormatter->Print( aNestLevel+1, "(add_net %s)\n", aFormatter->Quotew( *it ).c_str() ); - } - } + aFormatter->Print( aNestLevel+1, "(add_net %s)\n", aFormatter->Quotew( *it ).c_str() ); aFormatter->Print( aNestLevel, ")\n\n" ); } diff --git a/pcbnew/class_netclass.h b/pcbnew/class_netclass.h index d5e0005357..7085b3ebe3 100644 --- a/pcbnew/class_netclass.h +++ b/pcbnew/class_netclass.h @@ -41,6 +41,7 @@ class LINE_READER; class BOARD; +class BOARD_DESIGN_SETTINGS; /** @@ -53,17 +54,15 @@ class NETCLASS { private: // Default values used to init a NETCLASS - static int DEFAULT_CLEARANCE; - static int DEFAULT_VIA_DRILL; - static int DEFAULT_UVIA_DRILL; + const static int DEFAULT_CLEARANCE; + const static int DEFAULT_VIA_DRILL; + const static int DEFAULT_UVIA_DRILL; protected: - - BOARD* m_Parent; wxString m_Name; ///< Name of the net class wxString m_Description; ///< what this NETCLASS is for. - typedef std::set STRINGSET; + typedef std::set STRINGSET; STRINGSET m_Members; ///< names of NET members of this class @@ -85,12 +84,9 @@ public: /** * Constructor * stuffs a NETCLASS instance with aParent, aName, and optionally the initialParameters - * @param aParent = the parent board * @param aName = the name of this new netclass - * @param initialParameters is a NETCLASS to copy parameters from, or if - * NULL tells me to copy default settings from BOARD::m_designSettings. */ - NETCLASS( BOARD* aParent, const wxString& aName, const NETCLASS* initialParameters = NULL ); + NETCLASS( const wxString& aName ); ~NETCLASS(); @@ -115,7 +111,6 @@ public: return m_Members.size(); } - /** * Function Clear * empties the collection of members. @@ -125,7 +120,6 @@ public: m_Members.clear(); } - /** * Function AddMember * adds \a aNetname to this NETCLASS if it is not already in this NETCLASS. @@ -169,34 +163,35 @@ public: void SetClearance( int aClearance ) { m_Clearance = aClearance; } int GetTrackWidth() const { return m_TrackWidth; } - int GetTrackMinWidth() const; void SetTrackWidth( int aWidth ) { m_TrackWidth = aWidth; } int GetViaDiameter() const { return m_ViaDia; } - int GetViaMinDiameter() const; void SetViaDiameter( int aDia ) { m_ViaDia = aDia; } int GetViaDrill() const { return m_ViaDrill; } - int GetViaMinDrill() const; void SetViaDrill( int aSize ) { m_ViaDrill = aSize; } int GetuViaDiameter() const { return m_uViaDia; } - int GetuViaMinDiameter() const; void SetuViaDiameter( int aSize ) { m_uViaDia = aSize; } int GetuViaDrill() const { return m_uViaDrill; } - int GetuViaMinDrill() const; void SetuViaDrill( int aSize ) { m_uViaDrill = aSize; } - /** * Function SetParams * will set all the parameters by copying them from \a defaults. * Parameters are the values like m_ViaSize, etc, but do not include m_Description. - * @param defaults is another NETCLASS to copy from. If NULL, then copy - * from global preferences instead. + * @param aDefaults is another NETCLASS object to copy from. */ - void SetParams( const NETCLASS* defaults = NULL ); + void SetParams( const NETCLASS& aDefaults ); + + /** + * Function SetParams + * will set all the parameters by copying them from board design settings. + * @param aSettings is a BOARD_DESIGN_SETTINGS object to copy from. Clearance, via drill and + * microvia drill values are taken from the defaults. + */ + void SetParams( const BOARD_DESIGN_SETTINGS& aSettings ); /** * Function Format @@ -225,9 +220,7 @@ public: class NETCLASSES { private: - BOARD* m_Parent; - - typedef std::map NETCLASSMAP; + typedef std::map NETCLASSMAP; /// all the NETCLASSes except the default one. NETCLASSMAP m_NetClasses; @@ -236,7 +229,7 @@ private: NETCLASS m_Default; public: - NETCLASSES( BOARD* aParent = NULL ); + NETCLASSES(); ~NETCLASSES(); /** @@ -245,7 +238,7 @@ public: */ void Clear(); - typedef NETCLASSMAP::iterator iterator; + typedef NETCLASSMAP::iterator iterator; iterator begin() { return m_NetClasses.begin(); } iterator end() { return m_NetClasses.end(); } @@ -253,7 +246,6 @@ public: const_iterator begin() const { return m_NetClasses.begin(); } const_iterator end() const { return m_NetClasses.end(); } - /** * Function GetCount * @return the number of netclasses, excluding the default one. @@ -263,6 +255,10 @@ public: return m_NetClasses.size(); } + /** + * Function GetDefault + * @return the default net class. + */ NETCLASS* GetDefault() const { return (NETCLASS*) &m_Default; diff --git a/pcbnew/dialogs/dialog_design_rules.cpp b/pcbnew/dialogs/dialog_design_rules.cpp index 35b687de13..13f6da13c9 100644 --- a/pcbnew/dialogs/dialog_design_rules.cpp +++ b/pcbnew/dialogs/dialog_design_rules.cpp @@ -190,15 +190,15 @@ void DIALOG_DESIGN_RULES::PrintCurrentSettings() m_MessagesList->AppendToPage( _( "Current general settings:
" ) ); // Display min values: - value = StringFromValue( g_UserUnit, m_BrdSettings.m_TrackMinWidth, true ); + value = StringFromValue( g_UserUnit, m_BrdSettings->m_TrackMinWidth, true ); msg.Printf( _( "Minimum value for tracks width: %s
\n" ), GetChars( value ) ); m_MessagesList->AppendToPage( msg ); - value = StringFromValue( g_UserUnit, m_BrdSettings.m_ViasMinSize, true ); + value = StringFromValue( g_UserUnit, m_BrdSettings->m_ViasMinSize, true ); msg.Printf( _( "Minimum value for vias diameter: %s
\n" ), GetChars( value ) ); m_MessagesList->AppendToPage( msg ); - value = StringFromValue( g_UserUnit, m_BrdSettings.m_MicroViasMinSize, true ); + value = StringFromValue( g_UserUnit, m_BrdSettings->m_MicroViasMinSize, true ); msg.Printf( _( "Minimum value for microvias diameter: %s
\n" ), GetChars( value ) ); m_MessagesList->AppendToPage( msg ); } @@ -212,7 +212,7 @@ void DIALOG_DESIGN_RULES::InitDialogRules() SetReturnCode( 0 ); m_Pcb = m_Parent->GetBoard(); - m_BrdSettings = m_Pcb->GetDesignSettings(); + m_BrdSettings = &m_Pcb->GetDesignSettings(); // Initialize the Rules List InitRulesList(); @@ -220,13 +220,8 @@ void DIALOG_DESIGN_RULES::InitDialogRules() // copy all NETs into m_AllNets by adding them as NETCUPs. // @todo go fix m_Pcb->SynchronizeNetsAndNetClasses() so that the netcode==0 is not present in the BOARD::m_NetClasses - - - NETCLASS* netclass; - - NETCLASSES& netclasses = m_Pcb->m_NetClasses; - - netclass = netclasses.GetDefault(); + NETCLASSES& netclasses = m_BrdSettings->m_NetClasses; + NETCLASS* netclass = netclasses.GetDefault(); // Initialize list of nets for Default Net Class for( NETCLASS::const_iterator name = netclass->begin(); name != netclass->end(); ++name ) @@ -262,23 +257,23 @@ void DIALOG_DESIGN_RULES::InitGlobalRules() AddUnitSymbol( *m_MicroViaMinDrillTitle ); AddUnitSymbol( *m_TrackMinWidthTitle ); - PutValueInLocalUnits( *m_SetViasMinSizeCtrl, m_BrdSettings.m_ViasMinSize ); - PutValueInLocalUnits( *m_SetViasMinDrillCtrl, m_BrdSettings.m_ViasMinDrill ); + PutValueInLocalUnits( *m_SetViasMinSizeCtrl, m_BrdSettings->m_ViasMinSize ); + PutValueInLocalUnits( *m_SetViasMinDrillCtrl, m_BrdSettings->m_ViasMinDrill ); - if( m_BrdSettings.m_BlindBuriedViaAllowed ) + if( m_BrdSettings->m_BlindBuriedViaAllowed ) m_OptViaType->SetSelection( 1 ); - m_AllowMicroViaCtrl->SetSelection( m_BrdSettings.m_MicroViasAllowed ? 1 : 0 ); - PutValueInLocalUnits( *m_SetMicroViasMinSizeCtrl, m_BrdSettings.m_MicroViasMinSize ); - PutValueInLocalUnits( *m_SetMicroViasMinDrillCtrl, m_BrdSettings.m_MicroViasMinDrill ); - PutValueInLocalUnits( *m_SetTrackMinWidthCtrl, m_BrdSettings.m_TrackMinWidth ); + m_AllowMicroViaCtrl->SetSelection( m_BrdSettings->m_MicroViasAllowed ? 1 : 0 ); + PutValueInLocalUnits( *m_SetMicroViasMinSizeCtrl, m_BrdSettings->m_MicroViasMinSize ); + PutValueInLocalUnits( *m_SetMicroViasMinDrillCtrl, m_BrdSettings->m_MicroViasMinDrill ); + PutValueInLocalUnits( *m_SetTrackMinWidthCtrl, m_BrdSettings->m_TrackMinWidth ); // Initialize Vias and Tracks sizes lists. // note we display only extra values, never the current netclass value. // (the first value in history list) - m_TracksWidthList = m_BrdSettings.m_TrackWidthList; + m_TracksWidthList = m_BrdSettings->m_TrackWidthList; m_TracksWidthList.erase( m_TracksWidthList.begin() ); // remove the netclass value - m_ViasDimensionsList = m_BrdSettings.m_ViasDimensionsList; + m_ViasDimensionsList = m_BrdSettings->m_ViasDimensionsList; m_ViasDimensionsList.erase( m_ViasDimensionsList.begin() ); // remove the netclass value InitDimensionsLists(); } @@ -484,7 +479,7 @@ static void class2gridRow( wxGrid* grid, int row, NETCLASS* nc ) */ void DIALOG_DESIGN_RULES::InitRulesList() { - NETCLASSES& netclasses = m_Pcb->m_NetClasses; + NETCLASSES& netclasses = m_BrdSettings->m_NetClasses; // the +1 is for the Default NETCLASS. if( netclasses.GetCount() + 1 > (unsigned) m_grid->GetNumberRows() ) @@ -524,7 +519,7 @@ static void gridRow2class( wxGrid* grid, int row, NETCLASS* nc ) */ void DIALOG_DESIGN_RULES::CopyRulesListToBoard() { - NETCLASSES& netclasses = m_Pcb->m_NetClasses; + NETCLASSES& netclasses = m_BrdSettings->m_NetClasses; // Remove all netclasses from board. We'll copy new list after netclasses.Clear(); @@ -535,9 +530,9 @@ void DIALOG_DESIGN_RULES::CopyRulesListToBoard() // Copy other NetClasses : for( int row = 1; row < m_grid->GetNumberRows(); ++row ) { - NETCLASS* nc = new NETCLASS( m_Pcb, m_grid->GetRowLabelValue( row ) ); + NETCLASS* nc = new NETCLASS( m_grid->GetRowLabelValue( row ) ); - if( !m_Pcb->m_NetClasses.Add( nc ) ) + if( !m_BrdSettings->m_NetClasses.Add( nc ) ) { // this netclass cannot be added because an other netclass with the same name exists // Should not occur because OnAddNetclassClick() tests for existing NetClass names @@ -568,20 +563,20 @@ void DIALOG_DESIGN_RULES::CopyRulesListToBoard() void DIALOG_DESIGN_RULES::CopyGlobalRulesToBoard() /*************************************************/ { - m_BrdSettings.m_BlindBuriedViaAllowed = m_OptViaType->GetSelection() > 0; + m_BrdSettings->m_BlindBuriedViaAllowed = m_OptViaType->GetSelection() > 0; // Update vias minimum values for DRC - m_BrdSettings.m_ViasMinSize = ValueFromTextCtrl( *m_SetViasMinSizeCtrl ); - m_BrdSettings.m_ViasMinDrill = ValueFromTextCtrl( *m_SetViasMinDrillCtrl ); + m_BrdSettings->m_ViasMinSize = ValueFromTextCtrl( *m_SetViasMinSizeCtrl ); + m_BrdSettings->m_ViasMinDrill = ValueFromTextCtrl( *m_SetViasMinDrillCtrl ); - m_BrdSettings.m_MicroViasAllowed = m_AllowMicroViaCtrl->GetSelection() == 1; + m_BrdSettings->m_MicroViasAllowed = m_AllowMicroViaCtrl->GetSelection() == 1; // Update microvias minimum values for DRC - m_BrdSettings.m_MicroViasMinSize = ValueFromTextCtrl( *m_SetMicroViasMinSizeCtrl ); - m_BrdSettings.m_MicroViasMinDrill = ValueFromTextCtrl( *m_SetMicroViasMinDrillCtrl ); + m_BrdSettings->m_MicroViasMinSize = ValueFromTextCtrl( *m_SetMicroViasMinSizeCtrl ); + m_BrdSettings->m_MicroViasMinDrill = ValueFromTextCtrl( *m_SetMicroViasMinDrillCtrl ); // Update tracks minimum values for DRC - m_BrdSettings.m_TrackMinWidth = ValueFromTextCtrl( *m_SetTrackMinWidthCtrl ); + m_BrdSettings->m_TrackMinWidth = ValueFromTextCtrl( *m_SetTrackMinWidthCtrl ); } @@ -634,12 +629,12 @@ void DIALOG_DESIGN_RULES::CopyDimensionsListsToBoard() // Sort new list by by increasing value sort( m_ViasDimensionsList.begin(), m_ViasDimensionsList.end() ); - std::vector* tlist = &m_BrdSettings.m_TrackWidthList; + std::vector* tlist = &m_BrdSettings->m_TrackWidthList; tlist->erase( tlist->begin() + 1, tlist->end() ); // Remove old "custom" sizes tlist->insert( tlist->end(), m_TracksWidthList.begin(), m_TracksWidthList.end() ); //Add new "custom" sizes // Reinitialize m_ViaSizeList - std::vector* vialist = &m_BrdSettings.m_ViasDimensionsList; + std::vector* vialist = &m_BrdSettings->m_ViasDimensionsList; vialist->erase( vialist->begin() + 1, vialist->end() ); vialist->insert( vialist->end(), m_ViasDimensionsList.begin(), m_ViasDimensionsList.end() ); } @@ -671,11 +666,9 @@ void DIALOG_DESIGN_RULES::OnOkButtonClick( wxCommandEvent& event ) CopyGlobalRulesToBoard(); CopyDimensionsListsToBoard(); - m_Pcb->SetDesignSettings( m_BrdSettings ); - EndModal( wxID_OK ); - m_Pcb->SetCurrentNetClass( NETCLASS::Default ); + m_BrdSettings->SetCurrentNetClass( NETCLASS::Default ); } @@ -755,7 +748,7 @@ void DIALOG_DESIGN_RULES::OnRemoveNetclassClick( wxCommandEvent& event ) for( unsigned ii = 0; ii < select.GetCount(); ii++ ) { int grid_row = select[ii]; - if( grid_row != 0 ) // Do not remove the default class + if( grid_row != 0 ) // Do not remove the default class { wxString classname = m_grid->GetRowLabelValue( grid_row ); m_grid->DeleteRows( grid_row ); diff --git a/pcbnew/dialogs/dialog_design_rules.h b/pcbnew/dialogs/dialog_design_rules.h index 3bfbfd8d57..f7206b5175 100644 --- a/pcbnew/dialogs/dialog_design_rules.h +++ b/pcbnew/dialogs/dialog_design_rules.h @@ -40,7 +40,7 @@ private: PCB_EDIT_FRAME* m_Parent; BOARD* m_Pcb; - BOARD_DESIGN_SETTINGS m_BrdSettings; + BOARD_DESIGN_SETTINGS* m_BrdSettings; static int s_LastTabSelection; ///< which tab user had open last diff --git a/pcbnew/dialogs/dialog_global_edit_tracks_and_vias.cpp b/pcbnew/dialogs/dialog_global_edit_tracks_and_vias.cpp index 71904a927e..5f3afd55f1 100644 --- a/pcbnew/dialogs/dialog_global_edit_tracks_and_vias.cpp +++ b/pcbnew/dialogs/dialog_global_edit_tracks_and_vias.cpp @@ -46,21 +46,22 @@ void DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::MyInit() // Display current setup for tracks and vias BOARD* board = m_Parent->GetBoard(); - NETCLASSES& netclasses = board->m_NetClasses; - NETINFO_ITEM* net = board->FindNet( m_Netcode ); + BOARD_DESIGN_SETTINGS& dsnSettings = board->GetDesignSettings(); + NETCLASSES& netclasses = dsnSettings.m_NetClasses; NETCLASS* netclass = netclasses.GetDefault(); + NETINFO_ITEM* net = board->FindNet( m_Netcode ); if( net ) { m_CurrentNetName->SetLabel( net->GetNetname() ); - m_CurrentNetclassName->SetLabel( board->GetCurrentNetClassName() ); - netclass = netclasses.Find( board->GetCurrentNetClassName() ); + m_CurrentNetclassName->SetLabel( dsnSettings.GetCurrentNetClassName() ); + netclass = netclasses.Find( dsnSettings.GetCurrentNetClassName() ); } /* Disable the option "copy current to net" if we have only default netclass values * i.e. when m_TrackWidthSelector and m_ViaSizeSelector are set to 0 */ - if( !board->GetDesignSettings().GetTrackWidthIndex() && !board->GetDesignSettings().GetViaSizeIndex() ) + if( !dsnSettings.GetTrackWidthIndex() && !dsnSettings.GetViaSizeIndex() ) { m_Net2CurrValueButton->Enable( false ); m_OptionID = ID_NETCLASS_VALUES_TO_CURRENT_NET; @@ -77,9 +78,9 @@ void DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::MyInit() msg = StringFromValue( g_UserUnit, value, true ); m_gridDisplayCurrentSettings->SetCellValue( 0, 0, msg ); - if( board->GetDesignSettings().GetTrackWidthIndex() ) + if( dsnSettings.GetTrackWidthIndex() ) { - value = board->GetDesignSettings().GetCurrentTrackWidth(); + value = dsnSettings.GetCurrentTrackWidth(); msg = StringFromValue( g_UserUnit, value, true ); } else @@ -91,9 +92,9 @@ void DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::MyInit() msg = StringFromValue( g_UserUnit, value, true ); m_gridDisplayCurrentSettings->SetCellValue( 0, 1, msg ); - if( board->GetDesignSettings().GetViaSizeIndex() ) + if( dsnSettings.GetViaSizeIndex() ) { - value = board->GetDesignSettings().GetCurrentViaSize(); + value = dsnSettings.GetCurrentViaSize(); msg = StringFromValue( g_UserUnit, value, true ); } else @@ -103,7 +104,7 @@ void DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::MyInit() value = netclass->GetViaDrill(); // Display via drill msg = StringFromValue( g_UserUnit, value, true ); m_gridDisplayCurrentSettings->SetCellValue( 0, 2, msg ); - value = board->GetDesignSettings().GetCurrentViaDrill(); + value = dsnSettings.GetCurrentViaDrill(); if( value >= 0 ) msg = StringFromValue( g_UserUnit, value, true ); else diff --git a/pcbnew/dialogs/dialog_plot.cpp b/pcbnew/dialogs/dialog_plot.cpp index 3b2550e931..0c59845187 100644 --- a/pcbnew/dialogs/dialog_plot.cpp +++ b/pcbnew/dialogs/dialog_plot.cpp @@ -70,8 +70,8 @@ void DIALOG_PLOT::Init_Dialog() // The reasonable width correction value must be in a range of // [-(MinTrackWidth-1), +(MinClearanceValue-1)] decimils. - m_widthAdjustMinValue = -(m_board->GetDesignSettings().m_TrackMinWidth - 1); - m_widthAdjustMaxValue = m_board->GetSmallestClearanceValue() - 1; + m_widthAdjustMinValue = -( m_board->GetDesignSettings().m_TrackMinWidth - 1 ); + m_widthAdjustMaxValue = m_board->GetDesignSettings().GetSmallestClearanceValue() - 1; switch( m_plotOpts.GetFormat() ) { diff --git a/pcbnew/drc.cpp b/pcbnew/drc.cpp index b32ddb65b4..67c451c721 100644 --- a/pcbnew/drc.cpp +++ b/pcbnew/drc.cpp @@ -403,7 +403,7 @@ bool DRC::testNetClasses() { bool ret = true; - NETCLASSES& netclasses = m_pcb->m_NetClasses; + NETCLASSES& netclasses = m_pcb->GetDesignSettings().m_NetClasses; wxString msg; // construct this only once here, not in a loop, since somewhat expensive. diff --git a/pcbnew/drc_clearance_test_functions.cpp b/pcbnew/drc_clearance_test_functions.cpp index 04394d2d08..ed48f149ab 100644 --- a/pcbnew/drc_clearance_test_functions.cpp +++ b/pcbnew/drc_clearance_test_functions.cpp @@ -154,6 +154,7 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads ) wxPoint shape_pos; NETCLASS* netclass = aRefSeg->GetNetClass(); + BOARD_DESIGN_SETTINGS& dsnSettings = m_pcb->GetDesignSettings(); /* In order to make some calculations more easier or faster, * pads and tracks coordinates will be made relative to the reference segment origin @@ -173,7 +174,7 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads ) // test if the via size is smaller than minimum if( refvia->GetViaType() == VIA_MICROVIA ) { - if( refvia->GetWidth() < netclass->GetuViaMinDiameter() ) + if( refvia->GetWidth() < dsnSettings.m_MicroViasMinSize ) { m_currentMarker = fillMarker( refvia, NULL, DRCE_TOO_SMALL_MICROVIA, m_currentMarker ); @@ -182,7 +183,7 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads ) } else { - if( refvia->GetWidth() < netclass->GetViaMinDiameter() ) + if( refvia->GetWidth() < dsnSettings.m_ViasMinSize ) { m_currentMarker = fillMarker( refvia, NULL, DRCE_TOO_SMALL_VIA, m_currentMarker ); @@ -231,7 +232,7 @@ bool DRC::doTrackDrc( TRACK* aRefSeg, TRACK* aStart, bool testPads ) } else // This is a track segment { - if( aRefSeg->GetWidth() < netclass->GetTrackMinWidth() ) + if( aRefSeg->GetWidth() < dsnSettings.m_TrackMinWidth ) { m_currentMarker = fillMarker( aRefSeg, NULL, DRCE_TOO_SMALL_TRACK_WIDTH, m_currentMarker ); diff --git a/pcbnew/eagle_plugin.cpp b/pcbnew/eagle_plugin.cpp index 4f93574ab2..b1da39fc6f 100644 --- a/pcbnew/eagle_plugin.cpp +++ b/pcbnew/eagle_plugin.cpp @@ -1133,7 +1133,7 @@ BOARD* EAGLE_PLUGIN::Load( const wxString& aFileName, BOARD* aAppendToMe, const loadAllSections( doc ); - BOARD_DESIGN_SETTINGS& designSettings = m_board->GetDesignSettings(); + BOARD_DESIGN_SETTINGS& designSettings = m_board->GetDesignSettings(); if( m_min_trace < designSettings.m_TrackMinWidth ) designSettings.m_TrackMinWidth = m_min_trace; @@ -1146,7 +1146,7 @@ BOARD* EAGLE_PLUGIN::Load( const wxString& aFileName, BOARD* aAppendToMe, const if( m_rules->mdWireWire ) { - NETCLASS* defaultNetclass = m_board->m_NetClasses.GetDefault(); + NETCLASS* defaultNetclass = designSettings.m_NetClasses.GetDefault(); int clearance = KiROUND( m_rules->mdWireWire ); if( clearance < defaultNetclass->GetClearance() ) diff --git a/pcbnew/edit_track_width.cpp b/pcbnew/edit_track_width.cpp index f19c8216e1..b0ec02eb13 100644 --- a/pcbnew/edit_track_width.cpp +++ b/pcbnew/edit_track_width.cpp @@ -67,7 +67,7 @@ bool PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem, if( net ) new_width = net->GetMicroViaSize(); else - new_width = GetBoard()->GetCurrentMicroViaSize(); + new_width = GetDesignSettings().GetCurrentMicroViaSize(); } } diff --git a/pcbnew/editrack.cpp b/pcbnew/editrack.cpp index ddd1356705..715ac98f8d 100644 --- a/pcbnew/editrack.cpp +++ b/pcbnew/editrack.cpp @@ -167,7 +167,7 @@ TRACK* PCB_EDIT_FRAME::Begin_Route( TRACK* aTrack, wxDC* aDC ) // Display info about track Net class, and init track and vias sizes: g_CurrentTrackSegment->SetNetCode( GetBoard()->GetHighLightNetCode() ); - GetBoard()->SetCurrentNetClass( g_CurrentTrackSegment->GetNetClassName() ); + GetDesignSettings().SetCurrentNetClass( g_CurrentTrackSegment->GetNetClassName() ); g_CurrentTrackSegment->SetLayer( GetScreen()->m_Active_Layer ); g_CurrentTrackSegment->SetWidth( GetDesignSettings().GetCurrentTrackWidth() ); diff --git a/pcbnew/files.cpp b/pcbnew/files.cpp index 27262d6f38..89671c066b 100644 --- a/pcbnew/files.cpp +++ b/pcbnew/files.cpp @@ -356,7 +356,7 @@ bool PCB_EDIT_FRAME::OpenProjectFiles( const std::vector& aFileSet, in } else { - GetBoard()->m_NetClasses.Clear(); + GetDesignSettings().m_NetClasses.Clear(); } BOARD* loadedBoard = 0; // it will be set to non-NULL if loaded OK @@ -485,7 +485,7 @@ bool PCB_EDIT_FRAME::OpenProjectFiles( const std::vector& aFileSet, in #endif // Update info shown by the horizontal toolbars - GetBoard()->SetCurrentNetClass( NETCLASS::Default ); + GetDesignSettings().SetCurrentNetClass( NETCLASS::Default ); ReFillLayerWidget(); ReCreateLayerBox(); @@ -678,7 +678,7 @@ bool PCB_EDIT_FRAME::SavePcbFile( const wxString& aFileName, bool aCreateBackupF // Select default Netclass before writing file. // Useful to save default values in headers - GetBoard()->SetCurrentNetClass( GetBoard()->m_NetClasses.GetDefault()->GetName() ); + GetDesignSettings().SetCurrentNetClass( GetDesignSettings().m_NetClasses.GetDefault()->GetName() ); try { diff --git a/pcbnew/kicad_plugin.cpp b/pcbnew/kicad_plugin.cpp index fd2cf976dc..adf5ce76eb 100644 --- a/pcbnew/kicad_plugin.cpp +++ b/pcbnew/kicad_plugin.cpp @@ -60,6 +60,17 @@ */ static const wxString traceFootprintLibrary( wxT( "KicadFootprintLib" ) ); +///> Removes empty nets (i.e. with node count equal zero) from net classes +void filterNetClass( const BOARD& aBoard, NETCLASS& aNetClass ) +{ + for( NETCLASS::const_iterator it = aNetClass.begin(); it != aNetClass.end(); ++it ) + { + NETINFO_ITEM* netinfo = aBoard.FindNet( *it ); + + if( netinfo && netinfo->GetNodesCount() <= 0 ) // hopefully there are no nets with negative + aNetClass.Remove( it ); // node count, but you never know.. + } +} /** * Class FP_CACHE_ITEM @@ -483,6 +494,8 @@ void PCB_IO::formatLayer( const BOARD_ITEM* aItem ) const void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const throw( IO_ERROR ) { + const BOARD_DESIGN_SETTINGS& dsnSettings = aBoard->GetDesignSettings(); + m_out->Print( 0, "\n" ); m_out->Print( aNestLevel, "(general\n" ); @@ -496,7 +509,7 @@ void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const FMTIU( aBoard->GetBoundingBox().GetRight() ).c_str(), FMTIU( aBoard->GetBoundingBox().GetBottom() ).c_str() ); m_out->Print( aNestLevel+1, "(thickness %s)\n", - FMTIU( aBoard->GetDesignSettings().GetBoardThickness() ).c_str() ); + FMTIU( dsnSettings.GetBoardThickness() ).c_str() ); m_out->Print( aNestLevel+1, "(drawings %d)\n", aBoard->m_Drawings.GetCount() ); m_out->Print( aNestLevel+1, "(tracks %d)\n", aBoard->GetNumSegmTrack() ); @@ -551,15 +564,15 @@ void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const // Save current default track width, for compatibility with older Pcbnew version; m_out->Print( aNestLevel+1, "(last_trace_width %s)\n", - FMTIU( aBoard->GetDesignSettings().GetCurrentTrackWidth() ).c_str() ); + FMTIU( dsnSettings.GetCurrentTrackWidth() ).c_str() ); // Save custom tracks width list (the first is not saved here: this is the netclass value - for( unsigned ii = 1; ii < aBoard->GetDesignSettings().m_TrackWidthList.size(); ii++ ) + for( unsigned ii = 1; ii < dsnSettings.m_TrackWidthList.size(); ii++ ) m_out->Print( aNestLevel+1, "(user_trace_width %s)\n", - FMTIU( aBoard->GetDesignSettings().m_TrackWidthList[ii] ).c_str() ); + FMTIU( dsnSettings.m_TrackWidthList[ii] ).c_str() ); m_out->Print( aNestLevel+1, "(trace_clearance %s)\n", - FMTIU( aBoard->m_NetClasses.GetDefault()->GetClearance() ).c_str() ); + FMTIU( dsnSettings.m_NetClasses.GetDefault()->GetClearance() ).c_str() ); // ZONE_SETTINGS m_out->Print( aNestLevel+1, "(zone_clearance %s)\n", @@ -568,78 +581,79 @@ void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const aBoard->GetZoneSettings().m_Zone_45_Only ? "yes" : "no" ); m_out->Print( aNestLevel+1, "(trace_min %s)\n", - FMTIU( aBoard->GetDesignSettings().m_TrackMinWidth ).c_str() ); + FMTIU( dsnSettings.m_TrackMinWidth ).c_str() ); m_out->Print( aNestLevel+1, "(segment_width %s)\n", - FMTIU( aBoard->GetDesignSettings().m_DrawSegmentWidth ).c_str() ); + FMTIU( dsnSettings.m_DrawSegmentWidth ).c_str() ); m_out->Print( aNestLevel+1, "(edge_width %s)\n", - FMTIU( aBoard->GetDesignSettings().m_EdgeSegmentWidth ).c_str() ); + FMTIU( dsnSettings.m_EdgeSegmentWidth ).c_str() ); // Save current default via size, for compatibility with older Pcbnew version; m_out->Print( aNestLevel+1, "(via_size %s)\n", - FMTIU( aBoard->m_NetClasses.GetDefault()->GetViaDiameter() ).c_str() ); + FMTIU( dsnSettings.m_NetClasses.GetDefault()->GetViaDiameter() ).c_str() ); m_out->Print( aNestLevel+1, "(via_drill %s)\n", - FMTIU( aBoard->m_NetClasses.GetDefault()->GetViaDrill() ).c_str() ); + FMTIU( dsnSettings.m_NetClasses.GetDefault()->GetViaDrill() ).c_str() ); m_out->Print( aNestLevel+1, "(via_min_size %s)\n", - FMTIU( aBoard->GetDesignSettings().m_ViasMinSize ).c_str() ); + FMTIU( dsnSettings.m_ViasMinSize ).c_str() ); m_out->Print( aNestLevel+1, "(via_min_drill %s)\n", - FMTIU( aBoard->GetDesignSettings().m_ViasMinDrill ).c_str() ); + FMTIU( dsnSettings.m_ViasMinDrill ).c_str() ); // Save custom vias diameters list (the first is not saved here: this is // the netclass value - for( unsigned ii = 1; ii < aBoard->GetDesignSettings().m_ViasDimensionsList.size(); ii++ ) + for( unsigned ii = 1; ii < dsnSettings.m_ViasDimensionsList.size(); ii++ ) m_out->Print( aNestLevel+1, "(user_via %s %s)\n", - FMTIU( aBoard->GetDesignSettings().m_ViasDimensionsList[ii].m_Diameter ).c_str(), - FMTIU( aBoard->GetDesignSettings().m_ViasDimensionsList[ii].m_Drill ).c_str() ); + FMTIU( dsnSettings.m_ViasDimensionsList[ii].m_Diameter ).c_str(), + FMTIU( dsnSettings.m_ViasDimensionsList[ii].m_Drill ).c_str() ); // for old versions compatibility: - if( aBoard->GetDesignSettings().m_BlindBuriedViaAllowed ) + if( dsnSettings.m_BlindBuriedViaAllowed ) m_out->Print( aNestLevel+1, "(blind_buried_vias_allowed yes)\n" ); + m_out->Print( aNestLevel+1, "(uvia_size %s)\n", - FMTIU( aBoard->m_NetClasses.GetDefault()->GetuViaDiameter() ).c_str() ); + FMTIU( dsnSettings.m_NetClasses.GetDefault()->GetuViaDiameter() ).c_str() ); m_out->Print( aNestLevel+1, "(uvia_drill %s)\n", - FMTIU( aBoard->m_NetClasses.GetDefault()->GetuViaDrill() ).c_str() ); + FMTIU( dsnSettings.m_NetClasses.GetDefault()->GetuViaDrill() ).c_str() ); m_out->Print( aNestLevel+1, "(uvias_allowed %s)\n", - ( aBoard->GetDesignSettings().m_MicroViasAllowed ) ? "yes" : "no" ); + ( dsnSettings.m_MicroViasAllowed ) ? "yes" : "no" ); m_out->Print( aNestLevel+1, "(uvia_min_size %s)\n", - FMTIU( aBoard->GetDesignSettings().m_MicroViasMinSize ).c_str() ); + FMTIU( dsnSettings.m_MicroViasMinSize ).c_str() ); m_out->Print( aNestLevel+1, "(uvia_min_drill %s)\n", - FMTIU( aBoard->GetDesignSettings().m_MicroViasMinDrill ).c_str() ); + FMTIU( dsnSettings.m_MicroViasMinDrill ).c_str() ); m_out->Print( aNestLevel+1, "(pcb_text_width %s)\n", - FMTIU( aBoard->GetDesignSettings().m_PcbTextWidth ).c_str() ); + FMTIU( dsnSettings.m_PcbTextWidth ).c_str() ); m_out->Print( aNestLevel+1, "(pcb_text_size %s %s)\n", - FMTIU( aBoard->GetDesignSettings().m_PcbTextSize.x ).c_str(), - FMTIU( aBoard->GetDesignSettings().m_PcbTextSize.y ).c_str() ); + FMTIU( dsnSettings.m_PcbTextSize.x ).c_str(), + FMTIU( dsnSettings.m_PcbTextSize.y ).c_str() ); m_out->Print( aNestLevel+1, "(mod_edge_width %s)\n", - FMTIU( aBoard->GetDesignSettings().m_ModuleSegmentWidth ).c_str() ); + FMTIU( dsnSettings.m_ModuleSegmentWidth ).c_str() ); m_out->Print( aNestLevel+1, "(mod_text_size %s %s)\n", - FMTIU( aBoard->GetDesignSettings().m_ModuleTextSize.x ).c_str(), - FMTIU( aBoard->GetDesignSettings().m_ModuleTextSize.y ).c_str() ); + FMTIU( dsnSettings.m_ModuleTextSize.x ).c_str(), + FMTIU( dsnSettings.m_ModuleTextSize.y ).c_str() ); m_out->Print( aNestLevel+1, "(mod_text_width %s)\n", - FMTIU( aBoard->GetDesignSettings().m_ModuleTextWidth ).c_str() ); + FMTIU( dsnSettings.m_ModuleTextWidth ).c_str() ); m_out->Print( aNestLevel+1, "(pad_size %s %s)\n", - FMTIU( aBoard->GetDesignSettings().m_Pad_Master.GetSize().x ).c_str(), - FMTIU( aBoard->GetDesignSettings().m_Pad_Master.GetSize().y ).c_str() ); + FMTIU( dsnSettings.m_Pad_Master.GetSize().x ).c_str(), + FMTIU( dsnSettings.m_Pad_Master.GetSize().y ).c_str() ); m_out->Print( aNestLevel+1, "(pad_drill %s)\n", - FMTIU( aBoard->GetDesignSettings().m_Pad_Master.GetDrillSize().x ).c_str() ); + FMTIU( dsnSettings.m_Pad_Master.GetDrillSize().x ).c_str() ); m_out->Print( aNestLevel+1, "(pad_to_mask_clearance %s)\n", - FMTIU( aBoard->GetDesignSettings().m_SolderMaskMargin ).c_str() ); + FMTIU( dsnSettings.m_SolderMaskMargin ).c_str() ); - if( aBoard->GetDesignSettings().m_SolderMaskMinWidth ) + if( dsnSettings.m_SolderMaskMinWidth ) m_out->Print( aNestLevel+1, "(solder_mask_min_width %s)\n", - FMTIU( aBoard->GetDesignSettings().m_SolderMaskMinWidth ).c_str() ); + FMTIU( dsnSettings.m_SolderMaskMinWidth ).c_str() ); - if( aBoard->GetDesignSettings().m_SolderPasteMargin != 0 ) + if( dsnSettings.m_SolderPasteMargin != 0 ) m_out->Print( aNestLevel+1, "(pad_to_paste_clearance %s)\n", - FMTIU( aBoard->GetDesignSettings().m_SolderPasteMargin ).c_str() ); + FMTIU( dsnSettings.m_SolderPasteMargin ).c_str() ); - if( aBoard->GetDesignSettings().m_SolderPasteMarginRatio != 0 ) + if( dsnSettings.m_SolderPasteMarginRatio != 0 ) m_out->Print( aNestLevel+1, "(pad_to_paste_clearance_ratio %s)\n", - Double2Str( aBoard->GetDesignSettings().m_SolderPasteMarginRatio ).c_str() ); + Double2Str( dsnSettings.m_SolderPasteMarginRatio ).c_str() ); m_out->Print( aNestLevel+1, "(aux_axis_origin %s %s)\n", FMTIU( aBoard->GetAuxOrigin().x ).c_str(), @@ -651,7 +665,7 @@ void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const FMTIU( aBoard->GetGridOrigin().y ).c_str() ); m_out->Print( aNestLevel+1, "(visible_elements %X)\n", - aBoard->GetDesignSettings().GetVisibleElements() ); + dsnSettings.GetVisibleElements() ); aBoard->GetPlotOptions().Format( m_out, aNestLevel+1 ); @@ -669,15 +683,18 @@ void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const m_out->Print( 0, "\n" ); // Save the default net class first. - aBoard->m_NetClasses.GetDefault()->Format( m_out, aNestLevel, m_ctl ); + NETCLASS defaultNC = *dsnSettings.m_NetClasses.GetDefault(); + filterNetClass( *aBoard, defaultNC ); // Remove empty nets (from a copy of a netclass) + defaultNC.Format( m_out, aNestLevel, m_ctl ); // Save the rest of the net classes alphabetically. - for( NETCLASSES::const_iterator it = aBoard->m_NetClasses.begin(); - it != aBoard->m_NetClasses.end(); + for( NETCLASSES::const_iterator it = dsnSettings.m_NetClasses.begin(); + it != dsnSettings.m_NetClasses.end(); ++it ) { - NETCLASS* netclass = it->second; - netclass->Format( m_out, aNestLevel, m_ctl ); + NETCLASS netclass = *it->second; + filterNetClass( *aBoard, netclass ); // Remove empty nets (from a copy of a netclass) + netclass.Format( m_out, aNestLevel, m_ctl ); } // Save the modules. @@ -707,7 +724,7 @@ void PCB_IO::format( BOARD* aBoard, int aNestLevel ) const /// will not be saved. // Save the polygon (which are the newer technology) zones. - for( int i=0; i < aBoard->GetAreaCount(); ++i ) + for( int i = 0; i < aBoard->GetAreaCount(); ++i ) Format( aBoard->GetArea( i ), aNestLevel ); } diff --git a/pcbnew/legacy_plugin.cpp b/pcbnew/legacy_plugin.cpp index cf0aca69fe..77a4d14a0e 100644 --- a/pcbnew/legacy_plugin.cpp +++ b/pcbnew/legacy_plugin.cpp @@ -632,7 +632,7 @@ void LEGACY_PLUGIN::loadSHEET() void LEGACY_PLUGIN::loadSETUP() { - NETCLASS* netclass_default = m_board->m_NetClasses.GetDefault(); + NETCLASS* netclass_default = m_board->GetDesignSettings().m_NetClasses.GetDefault(); // TODO Orson: is it really necessary to first operate on a copy and then apply it? // would not it be better to use reference here and apply all the changes instantly? BOARD_DESIGN_SETTINGS bds = m_board->GetDesignSettings(); @@ -897,7 +897,7 @@ void LEGACY_PLUGIN::loadSETUP() // at all, the global defaults should go into a preferences // file instead so they are there to start new board // projects. - m_board->m_NetClasses.GetDefault()->SetParams(); + m_board->GetDesignSettings().m_NetClasses.GetDefault()->SetParams( m_board->GetDesignSettings() ); return; // preferred exit } @@ -2113,7 +2113,7 @@ void LEGACY_PLUGIN::loadNETCLASS() // yet since that would bypass duplicate netclass name checking within the BOARD. // store it temporarily in an auto_ptr until successfully inserted into the BOARD // just before returning. - auto_ptr nc( new NETCLASS( m_board, wxEmptyString ) ); + auto_ptr nc( new NETCLASS( wxEmptyString ) ); while( ( line = READLINE( m_reader ) ) != NULL ) { @@ -2175,7 +2175,7 @@ void LEGACY_PLUGIN::loadNETCLASS() else if( TESTLINE( "$EndNCLASS" ) ) { - if( m_board->m_NetClasses.Add( nc.get() ) ) + if( m_board->GetDesignSettings().m_NetClasses.Add( nc.get() ) ) { nc.release(); } @@ -2984,8 +2984,8 @@ void LEGACY_PLUGIN::saveSHEET( const BOARD* aBoard ) const void LEGACY_PLUGIN::saveSETUP( const BOARD* aBoard ) const { - NETCLASS* netclass_default = aBoard->m_NetClasses.GetDefault(); const BOARD_DESIGN_SETTINGS& bds = aBoard->GetDesignSettings(); + NETCLASS* netclass_default = bds.m_NetClasses.GetDefault(); fprintf( m_fp, "$SETUP\n" ); @@ -3098,7 +3098,7 @@ void LEGACY_PLUGIN::saveBOARD_ITEMS( const BOARD* aBoard ) const } // Saved nets do not include netclass names, so save netclasses after nets. - saveNETCLASSES( &aBoard->m_NetClasses ); + saveNETCLASSES( &aBoard->GetDesignSettings().m_NetClasses ); // save the modules for( MODULE* m = aBoard->m_Modules; m; m = (MODULE*) m->Next() ) @@ -3119,7 +3119,7 @@ void LEGACY_PLUGIN::saveBOARD_ITEMS( const BOARD* aBoard ) const savePCB_TARGET( (PCB_TARGET*) gr ); break; case PCB_DIMENSION_T: - saveDIMENTION( (DIMENSION*) gr ); + saveDIMENSION( (DIMENSION*) gr ); break; default: THROW_IO_ERROR( wxString::Format( UNKNOWN_GRAPHIC_FORMAT, gr->Type() ) ); @@ -3763,7 +3763,7 @@ void LEGACY_PLUGIN::saveZONE_CONTAINER( const ZONE_CONTAINER* me ) const } -void LEGACY_PLUGIN::saveDIMENTION( const DIMENSION* me ) const +void LEGACY_PLUGIN::saveDIMENSION( const DIMENSION* me ) const { // note: COTATION was the previous name of DIMENSION // this old keyword is used here for compatibility diff --git a/pcbnew/legacy_plugin.h b/pcbnew/legacy_plugin.h index dec3bfcbac..a9efbaa053 100644 --- a/pcbnew/legacy_plugin.h +++ b/pcbnew/legacy_plugin.h @@ -261,7 +261,7 @@ protected: void savePCB_TEXT( const TEXTE_PCB* aText ) const; void savePCB_TARGET( const PCB_TARGET* aTarget ) const; void savePCB_LINE( const DRAWSEGMENT* aStroke ) const; - void saveDIMENTION( const DIMENSION* aDimension ) const; + void saveDIMENSION( const DIMENSION* aDimension ) const; void saveTRACK( const TRACK* aTrack ) const; /** diff --git a/pcbnew/onleftclick.cpp b/pcbnew/onleftclick.cpp index dc5b0b97ee..922d04e727 100644 --- a/pcbnew/onleftclick.cpp +++ b/pcbnew/onleftclick.cpp @@ -161,7 +161,7 @@ void PCB_EDIT_FRAME::OnLeftClick( wxDC* aDC, const wxPoint& aPosition ) case PCB_TRACE_T: case PCB_VIA_T: case PCB_PAD_T: - GetBoard()->SetCurrentNetClass( + GetDesignSettings().SetCurrentNetClass( ((BOARD_CONNECTED_ITEM*)DrawStruct)->GetNetClassName() ); updateTraceWidthSelectBox(); updateViaSizeSelectBox(); diff --git a/pcbnew/onrightclick.cpp b/pcbnew/onrightclick.cpp index ec8157d17e..ffb14ac90a 100644 --- a/pcbnew/onrightclick.cpp +++ b/pcbnew/onrightclick.cpp @@ -464,7 +464,7 @@ void PCB_EDIT_FRAME::createPopupMenuForTracks( TRACK* Track, wxMenu* PopMenu ) wxPoint cursorPosition = GetCrossHairPosition(); wxString msg; - GetBoard()->SetCurrentNetClass( Track->GetNetClassName() ); + GetDesignSettings().SetCurrentNetClass( Track->GetNetClassName() ); updateTraceWidthSelectBox(); updateViaSizeSelectBox(); @@ -834,9 +834,9 @@ void PCB_EDIT_FRAME::createPopUpMenuForFpPads( D_PAD* Pad, wxMenu* menu ) if( flags ) // Currently in edit, no others commands possible return; - if( GetBoard()->GetCurrentNetClassName() != Pad->GetNetClassName() ) + if( GetDesignSettings().GetCurrentNetClassName() != Pad->GetNetClassName() ) { - GetBoard()->SetCurrentNetClass( Pad->GetNetClassName() ); + GetDesignSettings().SetCurrentNetClass( Pad->GetNetClassName() ); updateTraceWidthSelectBox(); updateViaSizeSelectBox(); } diff --git a/pcbnew/pcb_parser.cpp b/pcbnew/pcb_parser.cpp index 59ef3cb88f..77586e843f 100644 --- a/pcbnew/pcb_parser.cpp +++ b/pcbnew/pcb_parser.cpp @@ -808,7 +808,7 @@ void PCB_PARSER::parseSetup() throw( IO_ERROR, PARSE_ERROR ) wxT( "Cannot parse " ) + GetTokenString( CurTok() ) + wxT( " as setup." ) ); T token; - NETCLASS* defaultNetclass = m_board->m_NetClasses.GetDefault(); + NETCLASS* defaultNetClass = m_board->GetDesignSettings().m_NetClasses.GetDefault(); // TODO Orson: is it really necessary to first operate on a copy and then apply it? // would not it be better to use reference here and apply all the changes instantly? BOARD_DESIGN_SETTINGS designSettings = m_board->GetDesignSettings(); @@ -834,7 +834,7 @@ void PCB_PARSER::parseSetup() throw( IO_ERROR, PARSE_ERROR ) break; case T_trace_clearance: - defaultNetclass->SetClearance( parseBoardUnits( T_trace_clearance ) ); + defaultNetClass->SetClearance( parseBoardUnits( T_trace_clearance ) ); NeedRIGHT(); break; @@ -864,12 +864,12 @@ void PCB_PARSER::parseSetup() throw( IO_ERROR, PARSE_ERROR ) break; case T_via_size: - defaultNetclass->SetViaDiameter( parseBoardUnits( T_via_size ) ); + defaultNetClass->SetViaDiameter( parseBoardUnits( T_via_size ) ); NeedRIGHT(); break; case T_via_drill: - defaultNetclass->SetViaDrill( parseBoardUnits( T_via_drill ) ); + defaultNetClass->SetViaDrill( parseBoardUnits( T_via_drill ) ); NeedRIGHT(); break; @@ -893,12 +893,12 @@ void PCB_PARSER::parseSetup() throw( IO_ERROR, PARSE_ERROR ) break; case T_uvia_size: - defaultNetclass->SetuViaDiameter( parseBoardUnits( T_uvia_size ) ); + defaultNetClass->SetuViaDiameter( parseBoardUnits( T_uvia_size ) ); NeedRIGHT(); break; case T_uvia_drill: - defaultNetclass->SetuViaDrill( parseBoardUnits( T_uvia_drill ) ); + defaultNetClass->SetuViaDrill( parseBoardUnits( T_uvia_drill ) ); NeedRIGHT(); break; @@ -1048,7 +1048,7 @@ void PCB_PARSER::parseSetup() throw( IO_ERROR, PARSE_ERROR ) // at all, the global defaults should go into a preferences // file instead so they are there to start new board // projects. - m_board->m_NetClasses.GetDefault()->SetParams(); + defaultNetClass->SetParams( m_board->GetDesignSettings() ); } @@ -1082,7 +1082,7 @@ void PCB_PARSER::parseNETCLASS() throw( IO_ERROR, PARSE_ERROR ) T token; - std::auto_ptr nc( new NETCLASS( m_board, wxEmptyString ) ); + std::auto_ptr nc( new NETCLASS( wxEmptyString ) ); // Read netclass name (can be a name or just a number like track width) NeedSYMBOLorNUMBER(); @@ -1135,7 +1135,7 @@ void PCB_PARSER::parseNETCLASS() throw( IO_ERROR, PARSE_ERROR ) NeedRIGHT(); } - if( m_board->m_NetClasses.Add( nc.get() ) ) + if( m_board->GetDesignSettings().m_NetClasses.Add( nc.get() ) ) { nc.release(); } diff --git a/pcbnew/router/pns_router.cpp b/pcbnew/router/pns_router.cpp index 9a57b50b16..104aeaa05e 100644 --- a/pcbnew/router/pns_router.cpp +++ b/pcbnew/router/pns_router.cpp @@ -70,7 +70,7 @@ public: continue; wxString netClassName = ni->GetClassName(); - NETCLASS* nc = aBoard->m_NetClasses.Find( netClassName ); + NETCLASS* nc = aBoard->GetDesignSettings().m_NetClasses.Find( netClassName ); int clearance = nc->GetClearance(); m_clearanceCache[i] = clearance; TRACE( 1, "Add net %d netclass %s clearance %d", i % netClassName.mb_str() % diff --git a/pcbnew/router/router_tool.cpp b/pcbnew/router/router_tool.cpp index 8fe733fb8c..e270a0a5e8 100644 --- a/pcbnew/router/router_tool.cpp +++ b/pcbnew/router/router_tool.cpp @@ -115,11 +115,11 @@ void ROUTER_TOOL::getNetclassDimensions( int aNetCode, int& aWidth, if( ni ) { wxString netClassName = ni->GetClassName(); - netClass = board->m_NetClasses.Find( netClassName ); + netClass = board->GetDesignSettings().m_NetClasses.Find( netClassName ); } if( !netClass ) - netClass = board->m_NetClasses.GetDefault(); + netClass = board->GetDesignSettings().m_NetClasses.GetDefault(); aWidth = netClass->GetTrackWidth(); aViaDiameter = netClass->GetViaDiameter(); diff --git a/pcbnew/specctra_export.cpp b/pcbnew/specctra_export.cpp index ef452ce66d..089925576c 100644 --- a/pcbnew/specctra_export.cpp +++ b/pcbnew/specctra_export.cpp @@ -1476,9 +1476,10 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard ) throw( IO_ERROR ) //------------------------------------------------------------- { char rule[80]; + NETCLASS* defaultClass = aBoard->GetDesignSettings().m_NetClasses.GetDefault(); - int defaultTrackWidth = aBoard->m_NetClasses.GetDefault()->GetTrackWidth(); - int defaultClearance = aBoard->m_NetClasses.GetDefault()->GetClearance(); + int defaultTrackWidth = defaultClass->GetTrackWidth(); + int defaultClearance = defaultClass->GetClearance(); double clearance = scale( defaultClearance ); @@ -1829,7 +1830,7 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard ) throw( IO_ERROR ) //-----< output vias used in netclasses >----------------------------------- { - NETCLASSES& nclasses = aBoard->m_NetClasses; + NETCLASSES& nclasses = aBoard->GetDesignSettings().m_NetClasses; // Assume the netclass vias are all the same kind of thru, blind, or buried vias. // This is in lieu of either having each netclass via have its own layer pair in @@ -2039,7 +2040,7 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard ) throw( IO_ERROR ) //--------------------------------------------------------- - NETCLASSES& nclasses = aBoard->m_NetClasses; + NETCLASSES& nclasses = aBoard->GetDesignSettings().m_NetClasses; exportNETCLASS( nclasses.GetDefault(), aBoard ); diff --git a/pcbnew/zones_convert_brd_items_to_polygons_with_Boost.cpp b/pcbnew/zones_convert_brd_items_to_polygons_with_Boost.cpp index c51da1fc1c..b41d859b65 100644 --- a/pcbnew/zones_convert_brd_items_to_polygons_with_Boost.cpp +++ b/pcbnew/zones_convert_brd_items_to_polygons_with_Boost.cpp @@ -176,7 +176,7 @@ void ZONE_CONTAINER::AddClearanceAreasPolygonsToPolysList( BOARD* aPcb ) */ EDA_RECT item_boundingbox; EDA_RECT zone_boundingbox = GetBoundingBox(); - int biggest_clearance = aPcb->GetBiggestClearanceValue(); + int biggest_clearance = aPcb->GetDesignSettings().GetBiggestClearanceValue(); biggest_clearance = std::max( biggest_clearance, zone_clearance ); zone_boundingbox.Inflate( biggest_clearance ); diff --git a/pcbnew/zones_convert_to_polygons_aux_functions.cpp b/pcbnew/zones_convert_to_polygons_aux_functions.cpp index be02fd0d40..9861b0d120 100644 --- a/pcbnew/zones_convert_to_polygons_aux_functions.cpp +++ b/pcbnew/zones_convert_to_polygons_aux_functions.cpp @@ -138,7 +138,7 @@ void BuildUnconnectedThermalStubsPolygonList( CPOLYGONS_LIST& aCornerBuffer, EDA_RECT item_boundingbox; EDA_RECT zone_boundingbox = aZone->GetBoundingBox(); - int biggest_clearance = aPcb->GetBiggestClearanceValue(); + int biggest_clearance = aPcb->GetDesignSettings().GetBiggestClearanceValue(); biggest_clearance = std::max( biggest_clearance, zone_clearance ); zone_boundingbox.Inflate( biggest_clearance );