From e03257b55fdf1f7f46ff7fcd52e4f6531ad66379 Mon Sep 17 00:00:00 2001
From: Seth Hillbrand <seth@kipro-pcb.com>
Date: Wed, 1 Sep 2021 15:52:35 -0700
Subject: [PATCH] Allow close placement of stitching vias

When placing a stitching via for a bypass capacitor, it is common to
place it close to the relevant pad.  If the via does not have the
correct net, this will violate DRC and be prevented.

Checking for zone-based net assignments allows the workflow to proceed
---
 pcbnew/tools/drawing_tool.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/pcbnew/tools/drawing_tool.cpp b/pcbnew/tools/drawing_tool.cpp
index 61c07c6d28..733815a7d1 100644
--- a/pcbnew/tools/drawing_tool.cpp
+++ b/pcbnew/tools/drawing_tool.cpp
@@ -2553,6 +2553,8 @@ int DRAWING_TOOL::DrawVia( const TOOL_EVENT& aEvent )
                 via->SetNetCode( track->GetNetCode() );
             else if( pad )
                 via->SetNetCode( pad->GetNetCode() );
+            else
+                via->SetNetCode( findStitchedZoneNet( via ) );
 
             if( !m_allowDRCViolations && checkDRCViolation( via ) )
             {