diff --git a/pcbnew/scripting/board.i b/pcbnew/scripting/board.i index 7c6f8e1985..095a285bc0 100644 --- a/pcbnew/scripting/board.i +++ b/pcbnew/scripting/board.i @@ -35,22 +35,11 @@ def GetModules(self): return self.m_Modules def GetDrawings(self): return self.m_Drawings def GetTracks(self): return self.m_Track - def GetSegZones(self): return self.m_Zone def GetFullRatsnest(self): return self.m_FullRatsnest - def GetLocalRatsnest(self): return self.m_LocalRatsnest - def GetNetClasses(self): return self.m_NetClasses - def GetCurrentNetClassName(self): return self.m_CurrentNetClassName - def GetViasDimensionsList(self): return self.m_ViasDimensionsList - def GetTrackWidthList(self): return self.m_TrackWidthList + def GetZones(self): return self.m_ZoneDescriptorList - def Save(self,filename,format = None): - if format is None: - str_filename = str(filename) - if str_filename.endswith(".brd"): - format = IO_MGR.LEGACY - if str_filename.endswith(".kicad_pcb"): - format = IO_MGR.KICAD - return SaveBoard(filename,self,format) + def Save(self,filename): + return SaveBoard(filename,self,IO_MGR.KICAD) # # add function, clears the thisown to avoid python from deleting @@ -70,14 +59,12 @@ %rename(Get) operator TRACK*; %rename(Get) operator D_PAD*; %rename(Get) operator MODULE*; -%rename(Get) operator SEGZONE*; // we must translate C++ templates to scripting languages %template(BOARD_ITEM_List) DLIST; %template(MODULE_List) DLIST; -%template(SEGZONE_List) DLIST; %template(TRACK_List) DLIST; %template(PAD_List) DLIST; @@ -86,6 +73,25 @@ %template(VIA_DIMENSION_Vector) std::vector; %template (RASTNET_Vector) std::vector; +%extend BOARD +{ + %pythoncode + { + def GetNetClasses(self): + return self.GetDesignSettings().m_NetClasses + + def GetCurrentNetClassName(self): + return self.GetDesignSettings().m_CurrentNetClassName + + def GetViasDimensionsList(self): + return self.GetDesignSettings().m_ViasDimensionsList + + def GetTrackWidthList(self): + return self.GetDesignSettings().m_TrackWidthList + } +} + + %extend DRAWSEGMENT { %pythoncode diff --git a/pcbnew/scripting/board_item.i b/pcbnew/scripting/board_item.i index 1671c10da2..07384e2e6e 100644 --- a/pcbnew/scripting/board_item.i +++ b/pcbnew/scripting/board_item.i @@ -37,18 +37,18 @@ %extend BOARD_ITEM { - TEXTE_PCB* Cast_to_TEXTE_PCB() { return dynamic_cast(self); } - DIMENSION* Cast_to_DIMENSION() { return dynamic_cast(self); } - MODULE* Cast_to_MODULE() { return dynamic_cast(self); } - TEXTE_MODULE* Cast_to_TEXTE_MODULE() { return dynamic_cast(self); } - DRAWSEGMENT* Cast_to_DRAWSEGMENT() { return dynamic_cast(self); } - MARKER_PCB* Cast_to_MARKER_PCB() { return dynamic_cast(self); } - BOARD* Cast_to_BOARD() { return dynamic_cast(self); } - EDGE_MODULE* Cast_to_EDGE_MODULE() { return dynamic_cast(self); } - D_PAD* Cast_to_D_PAD() { return dynamic_cast(self); } - TRACK* Cast_to_TRACK() { return dynamic_cast(self); } - SEGZONE* Cast_to_SEGZONE() { return dynamic_cast(self); } - VIA* Cast_to_VIA() { return dynamic_cast(self); } + TEXTE_PCB* Cast_to_TEXTE_PCB() { return dynamic_cast(self); } + DIMENSION* Cast_to_DIMENSION() { return dynamic_cast(self); } + MODULE* Cast_to_MODULE() { return dynamic_cast(self); } + TEXTE_MODULE* Cast_to_TEXTE_MODULE() { return dynamic_cast(self); } + DRAWSEGMENT* Cast_to_DRAWSEGMENT() { return dynamic_cast(self); } + MARKER_PCB* Cast_to_MARKER_PCB() { return dynamic_cast(self); } + BOARD* Cast_to_BOARD() { return dynamic_cast(self); } + EDGE_MODULE* Cast_to_EDGE_MODULE() { return dynamic_cast(self); } + D_PAD* Cast_to_D_PAD() { return dynamic_cast(self); } + TRACK* Cast_to_TRACK() { return dynamic_cast(self); } + ZONE_CONTAINER* Cast_to_ZONE_CONTAINER() { return dynamic_cast(self);} + VIA* Cast_to_VIA() { return dynamic_cast(self); } %pythoncode @@ -73,12 +73,12 @@ return self.Cast_to_D_PAD() elif ct=="MTEXT": return self.Cast_to_TEXTE_MODULE() - elif ct=="ZONE": - return self.Cast_to_SEGZONE() elif ct=="VIA": return self.Cast_to_VIA() elif ct=="TRACK": return self.Cast_to_TRACK() + elif ct=="ZONE_CONTAINER": + return self.Cast_to_ZONE_CONTAINER() else: return None } diff --git a/pcbnew/scripting/examples/listPcb.py b/pcbnew/scripting/examples/listPcb.py index 92ab11a892..c1904ad7a6 100755 --- a/pcbnew/scripting/examples/listPcb.py +++ b/pcbnew/scripting/examples/listPcb.py @@ -6,34 +6,34 @@ filename=sys.argv[1] pcb = LoadBoard(filename) -#ToUnits = ToMM -#FromUnits = FromMM -ToUnits=ToMils -FromUnits=FromMils +ToUnits = ToMM +FromUnits = FromMM +#ToUnits=ToMils +#FromUnits=FromMils print "LISTING VIAS:" for item in pcb.GetTracks(): - if type(item) is SEGVIA: - + if type(item) is VIA: + pos = item.GetPosition() drill = item.GetDrillValue() width = item.GetWidth() print " * Via: %s - %f/%f "%(ToUnits(pos),ToUnits(drill),ToUnits(width)) - + elif type(item) is TRACK: - + start = item.GetStart() end = item.GetEnd() width = item.GetWidth() - + print " * Track: %s to %s, width %f" % (ToUnits(start),ToUnits(end),ToUnits(width)) - + else: print "Unknown type %s" % type(item) print "" -print "LISTING DRAWINGS:" +print "LIST DRAWINGS:" for item in pcb.GetDrawings(): if type(item) is TEXTE_PCB: @@ -42,22 +42,25 @@ for item in pcb.GetDrawings(): print "* Drawing: %s"%item.GetShapeStr() # dir(item) else: print type(item) - + print "" print "LIST MODULES:" for module in pcb.GetModules(): print "* Module: %s at %s"%(module.GetReference(),ToUnits(module.GetPosition())) - -print "" + +print "" +print "Ratsnest cnt:",len(pcb.GetFullRatsnest()) +print "track w cnt:",len(pcb.GetTrackWidthList()) +print "via s cnt:",len(pcb.GetViasDimensionsList()) + +print "" print "LIST ZONES:" -for zone in pcb.GetSegZones(): - print zone - - -print "" -print "RATSNEST:",len(pcb.GetFullRatsnest()) +for idx in range(0, pcb.GetAreaCount()): + zone=pcb.GetArea(idx) + print "zone:", idx, "priority:", zone.GetPriority(), "netname", zone.GetNetname() + +print "" +print "NetClasses:", pcb.GetNetClasses().GetCount() -print dir(pcb.GetNetClasses()) - diff --git a/pcbnew/scripting/pcbnew.i b/pcbnew/scripting/pcbnew.i index e893a55859..376028711b 100644 --- a/pcbnew/scripting/pcbnew.i +++ b/pcbnew/scripting/pcbnew.i @@ -88,6 +88,7 @@ #include #include #include + #include #include #include #include @@ -123,6 +124,7 @@ %include %include %include +%include %include %include %include diff --git a/pcbnew/scripting/units.i b/pcbnew/scripting/units.i index d34d58be5f..56ea213e3e 100644 --- a/pcbnew/scripting/units.i +++ b/pcbnew/scripting/units.i @@ -27,7 +27,7 @@ * @brief unit conversion code */ -// Unit conversion, between internal +// Unit conversion, between internal units and mm or mils %pythoncode { diff --git a/pcbnew/tracepcb.cpp b/pcbnew/tracepcb.cpp index ae15213d9f..190dd6969c 100644 --- a/pcbnew/tracepcb.cpp +++ b/pcbnew/tracepcb.cpp @@ -255,14 +255,14 @@ void BOARD::DrawHighLight( EDA_DRAW_PANEL* am_canvas, wxDC* DC, int aNetCode ) else draw_mode = GR_AND | GR_HIGHLIGHT; - // Redraw ZONE_CONTAINERS - BOARD::ZONE_CONTAINERS& zones = m_ZoneDescriptorList; - - for( BOARD::ZONE_CONTAINERS::iterator zc = zones.begin(); zc!=zones.end(); ++zc ) + // Redraw zones + for( int ii = 0; ii < GetAreaCount(); ii++ ) { - if( (*zc)->GetNetCode() == aNetCode ) + ZONE_CONTAINER* zone = GetArea( ii ); + + if( zone->GetNetCode() == aNetCode ) { - (*zc)->Draw( am_canvas, DC, draw_mode ); + zone->Draw( am_canvas, DC, draw_mode ); } }