From f220e83de621c9afa2745ef7f7cc70ac4524f166 Mon Sep 17 00:00:00 2001
From: Jeff Young <jeff@rokeby.ie>
Date: Wed, 14 Oct 2020 11:06:04 +0100
Subject: [PATCH] Board edges have no width.

Fixes https://gitlab.com/kicad/code/kicad/issues/5990
---
 common/rc_item.h                              |  4 +--
 .../drc/drc_test_provider_edge_clearance.cpp  | 27 ++++++++++---------
 2 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/common/rc_item.h b/common/rc_item.h
index 3fc5e29cfd..7297797dfc 100644
--- a/common/rc_item.h
+++ b/common/rc_item.h
@@ -115,8 +115,8 @@ public:
         m_ids.push_back( aItem->m_Uuid );
     }
 
-    void SetItems( EDA_ITEM* aItem, EDA_ITEM* bItem = nullptr, EDA_ITEM* cItem = nullptr,
-                   EDA_ITEM* dItem = nullptr )
+    void SetItems( const EDA_ITEM* aItem, const EDA_ITEM* bItem = nullptr,
+                   const EDA_ITEM* cItem = nullptr, const EDA_ITEM* dItem = nullptr )
     {
         m_ids.clear();
 
diff --git a/pcbnew/drc/drc_test_provider_edge_clearance.cpp b/pcbnew/drc/drc_test_provider_edge_clearance.cpp
index 4dcc28a1cd..c5201dba5c 100644
--- a/pcbnew/drc/drc_test_provider_edge_clearance.cpp
+++ b/pcbnew/drc/drc_test_provider_edge_clearance.cpp
@@ -90,13 +90,14 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
     if( !reportPhase( _( "Checking board edge clearances..." ) ) )
         return false;
     
-    std::vector<PCB_SHAPE*>  boardOutline;
+    std::vector<PCB_SHAPE>   boardOutline;
     std::vector<BOARD_ITEM*> boardItems;
 
     auto queryBoardOutlineItems =
             [&]( BOARD_ITEM *item ) -> bool
             {
                 boardOutline.push_back( dyn_cast<PCB_SHAPE*>( item ) );
+                boardOutline.back().SetWidth( 0 );
                 return true;
             };
 
@@ -116,20 +117,20 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
     drc_dbg( 2, "outline: %d items, board: %d items\n",
             (int) boardOutline.size(), (int) boardItems.size() );
 
-    for( PCB_SHAPE* outlineItem : boardOutline )
+    for( const PCB_SHAPE& outlineItem : boardOutline )
     {
         if( m_drcEngine->IsErrorLimitExceeded( DRCE_COPPER_EDGE_CLEARANCE ) )
             break;
 
-        const std::shared_ptr<SHAPE>& refShape = outlineItem->GetEffectiveShape();
+        const std::shared_ptr<SHAPE>& refShape = outlineItem.GetEffectiveShape();
 
         for( BOARD_ITEM* boardItem : boardItems )
         {
             if( m_drcEngine->IsErrorLimitExceeded( DRCE_COPPER_EDGE_CLEARANCE ) )
                 break;
 
-            drc_dbg( 10, "RefT %d %p %s %d\n", outlineItem->Type(), outlineItem,
-                     outlineItem->GetClass(), outlineItem->GetLayer() );
+            drc_dbg( 10, "RefT %d %p %s %d\n", outlineItem.Type(), &outlineItem,
+                     outlineItem.GetClass(), outlineItem.GetLayer() );
             drc_dbg( 10, "BoardT %d %p %s %d\n", boardItem->Type(), boardItem,
                      boardItem->GetClass(), boardItem->GetLayer() );
 
@@ -139,7 +140,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
             const std::shared_ptr<SHAPE>& shape = boardItem->GetEffectiveShape();
 
             auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_EDGE_CLEARANCE,
-                                                              outlineItem, boardItem );
+                                                              &outlineItem, boardItem );
 
             int      minClearance = constraint.GetValue().Min();
             int      actual;
@@ -157,7 +158,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
                               MessageTextFromValue( userUnits(), actual ) );
 
                 drcItem->SetErrorMessage( m_msg );
-                drcItem->SetItems( outlineItem, boardItem );
+                drcItem->SetItems( &outlineItem, boardItem );
                 drcItem->SetViolatingRule( constraint.GetParentRule() );
 
                 reportViolation( drcItem, (wxPoint) pos );
@@ -171,20 +172,20 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
     boardItems.clear();
     forEachGeometryItem( {}, LSET( 2, F_SilkS, B_SilkS ), queryBoardGeometryItems );
 
-    for( PCB_SHAPE* outlineItem : boardOutline )
+    for( const PCB_SHAPE& outlineItem : boardOutline )
     {
         if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_MASK_CLEARANCE ) )
             break;
 
-        const std::shared_ptr<SHAPE>& refShape = outlineItem->GetEffectiveShape();
+        const std::shared_ptr<SHAPE>& refShape = outlineItem.GetEffectiveShape();
 
         for( BOARD_ITEM* boardItem : boardItems )
         {
             if( m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_MASK_CLEARANCE ) )
                 break;
 
-            drc_dbg( 10, "RefT %d %p %s %d\n", outlineItem->Type(), outlineItem,
-                     outlineItem->GetClass(), outlineItem->GetLayer() );
+            drc_dbg( 10, "RefT %d %p %s %d\n", outlineItem.Type(), &outlineItem,
+                     outlineItem.GetClass(), outlineItem.GetLayer() );
             drc_dbg( 10, "BoardT %d %p %s %d\n", boardItem->Type(), boardItem,
                      boardItem->GetClass(), boardItem->GetLayer() );
 
@@ -194,7 +195,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
             const std::shared_ptr<SHAPE>& shape = boardItem->GetEffectiveShape();
 
             auto constraint = m_drcEngine->EvalRulesForItems( DRC_CONSTRAINT_TYPE_SILK_CLEARANCE,
-                                                              outlineItem, boardItem );
+                                                              &outlineItem, boardItem );
 
             int      minClearance = constraint.GetValue().Min();
             int      actual;
@@ -216,7 +217,7 @@ bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
                     drcItem->SetErrorMessage( m_msg );
                 }
 
-                drcItem->SetItems( outlineItem, boardItem );
+                drcItem->SetItems( &outlineItem, boardItem );
                 drcItem->SetViolatingRule( constraint.GetParentRule() );
 
                 reportViolation( drcItem, (wxPoint) pos );