From f61d400d88e80b05ce3a71bf8ec3376793565806 Mon Sep 17 00:00:00 2001 From: Seth Hillbrand Date: Mon, 15 Apr 2024 17:40:04 -0700 Subject: [PATCH] Allow non-identical schematic/pcb nets The schematic net names are fully unique but if we have multiple pads that are mapped to a NC pin, they need to have unique net names so that they do not get connected to each other in the ratsnest. This breaks the schematic parity check as we have modified the netname for some pads. To work around this, we first maintain the zero-th net without suffix and then add an additional check in DRC to ensure that we allow unconnected nets as long as the share a common prefix with the schematic netname. --- .../drc_test_provider_schematic_parity.cpp | 5 +- .../netlist_reader/board_netlist_updater.cpp | 4 +- .../unconnected-netnames.kicad_pcb | 312 ++++++++++ .../unconnected-netnames.kicad_pro | 582 ++++++++++++++++++ .../unconnected-netnames.kicad_sch | 187 ++++++ qa/tests/pcbnew/drc/test_drc_regressions.cpp | 3 +- 6 files changed, 1090 insertions(+), 3 deletions(-) create mode 100644 qa/data/pcbnew/unconnected-netnames/unconnected-netnames.kicad_pcb create mode 100644 qa/data/pcbnew/unconnected-netnames/unconnected-netnames.kicad_pro create mode 100644 qa/data/pcbnew/unconnected-netnames/unconnected-netnames.kicad_sch diff --git a/pcbnew/drc/drc_test_provider_schematic_parity.cpp b/pcbnew/drc/drc_test_provider_schematic_parity.cpp index a975043071..4fe37b4a8a 100644 --- a/pcbnew/drc/drc_test_provider_schematic_parity.cpp +++ b/pcbnew/drc/drc_test_provider_schematic_parity.cpp @@ -213,7 +213,10 @@ void DRC_TEST_PROVIDER_SCHEMATIC_PARITY::testNetlist( NETLIST& aNetlist ) drcItem->SetItems( pad ); reportViolation( drcItem, footprint->GetPosition(), UNDEFINED_LAYER ); } - else if( pcb_netname != sch_net.GetNetName() ) + else if( pcb_netname != sch_net.GetNetName() + && !( pcb_netname.starts_with( + wxT( "unconnected-" ) ) + && pcb_netname.starts_with( sch_net.GetNetName() ) ) ) { wxString msg; msg.Printf( _( "Pad net (%s) doesn't match net given by schematic (%s)." ), diff --git a/pcbnew/netlist_reader/board_netlist_updater.cpp b/pcbnew/netlist_reader/board_netlist_updater.cpp index 88b2ac37ec..d2047a7ed8 100644 --- a/pcbnew/netlist_reader/board_netlist_updater.cpp +++ b/pcbnew/netlist_reader/board_netlist_updater.cpp @@ -774,7 +774,9 @@ bool BOARD_NETLIST_UPDATER::updateComponentPadConnections( FOOTPRINT* aFootprint if( pad->IsNoConnectPad() ) { - for( int jj = 0; !padNetnames.insert( netName ).second; jj++ ) + netName = wxString::Format( wxS( "%s" ), net.GetNetName() ); + + for( int jj = 1; !padNetnames.insert( netName ).second; jj++ ) netName = wxString::Format( wxS( "%s_%d" ), net.GetNetName(), jj ); } diff --git a/qa/data/pcbnew/unconnected-netnames/unconnected-netnames.kicad_pcb b/qa/data/pcbnew/unconnected-netnames/unconnected-netnames.kicad_pcb new file mode 100644 index 0000000000..319b494df4 --- /dev/null +++ b/qa/data/pcbnew/unconnected-netnames/unconnected-netnames.kicad_pcb @@ -0,0 +1,312 @@ +(kicad_pcb + (version 20240108) + (generator "pcbnew") + (generator_version "8.0") + (general + (thickness 1.6) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + (50 "User.1" user) + (51 "User.2" user) + (52 "User.3" user) + (53 "User.4" user) + (54 "User.5" user) + (55 "User.6" user) + (56 "User.7" user) + (57 "User.8" user) + (58 "User.9" user) + ) + (setup + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (pcbplotparams + (layerselection 0x00010fc_ffffffff) + (plot_on_all_layers_selection 0x0000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (viasonmask no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plotreference yes) + (plotvalue yes) + (plotfptext yes) + (plotinvisibletext no) + (sketchpadsonfab no) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "unconnected-(TP1-Pad1)") + (net 2 "unconnected-(TP1-Pad1)_0") + (footprint "TestPoint:TestPoint_Bridge_Pitch2.0mm_Drill0.7mm" + (layer "F.Cu") + (uuid "5680b68d-7137-4930-9dd5-5f4fafc5da8a") + (at 138.030698 95.032002) + (descr "wire loop as test point, pitch 2.0mm, hole diameter 0.7mm, wire diameter 0.5mm") + (tags "test point wire loop") + (property "Reference" "TP1" + (at 1.1 1.7 0) + (layer "F.SilkS") + (uuid "11d7e369-d660-47fd-b0a6-a75a951bd9c1") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "TestPoint" + (at 1 -1.7 0) + (layer "F.Fab") + (uuid "2eb9ba42-d796-4602-a8f0-fde3acb50d6e") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Footprint" "TestPoint:TestPoint_Bridge_Pitch2.0mm_Drill0.7mm" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "6c96debe-73f8-4b61-be48-a4e8041cff18") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "184f7e85-ad7b-4b59-937b-3d4d83be1bf6") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "test point" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "d0d1b28c-4db5-4f05-827c-fd0be8adb39e") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property ki_fp_filters "Pin* Test*") + (path "/b198df71-7d13-4632-9ab4-7f217c917f8e") + (sheetname "Root") + (sheetfile "unconnected-netnames.kicad_sch") + (attr through_hole) + (fp_line + (start -0.9 -0.9) + (end -0.9 0.9) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "2fe3d8a9-dc64-48f4-aaf4-fe3103931d68") + ) + (fp_line + (start -0.9 0.9) + (end 2.9 0.9) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "138aaf38-c051-46e9-ad38-138884916c01") + ) + (fp_line + (start 2.9 -0.9) + (end -0.9 -0.9) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "e06fafc6-4b7a-4ed3-8a80-e4feea1bfd93") + ) + (fp_line + (start 2.9 0.9) + (end 2.9 -0.9) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "4b1513ef-3a66-48c5-a1aa-1c7c8ba3bbd4") + ) + (fp_line + (start -1.2 1.2) + (end -1.2 -1.2) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "0059a420-bbf7-4e65-9f77-86799f6138e6") + ) + (fp_line + (start -1.2 1.2) + (end 3.2 1.2) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "33a7f956-1108-4fde-9cfb-0ef4b812e0ef") + ) + (fp_line + (start 3.2 -1.2) + (end -1.2 -1.2) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "5dfad35d-845b-4737-a5c9-97b1dc8ff81c") + ) + (fp_line + (start 3.2 -1.2) + (end 3.2 1.2) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "97e9c191-1b39-4899-801d-c217ef903a17") + ) + (fp_line + (start 2 0) + (end 0 0) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.Fab") + (uuid "2f4282e9-3e81-4d51-abb4-e88b82550105") + ) + (fp_text user "${REFERENCE}" + (at 1.1 1.7 0) + (layer "F.Fab") + (uuid "32926f2f-12bb-47bd-8d01-164977f77338") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (pad "1" thru_hole circle + (at 0 0) + (size 1.4 1.4) + (drill 0.7) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (net 2 "unconnected-(TP1-Pad1)_0") + (pinfunction "1") + (pintype "passive+no_connect") + (uuid "891be13e-e841-49df-9fe9-aa0803a01c48") + ) + (pad "1" thru_hole circle + (at 2 0) + (size 1.4 1.4) + (drill 0.7) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (net 1 "unconnected-(TP1-Pad1)") + (pinfunction "1") + (pintype "passive+no_connect") + (uuid "7f73b514-d3e4-4e9b-aa32-6a472854c04b") + ) + (model "${KICAD6_3DMODEL_DIR}/TestPoint.3dshapes/TestPoint_Bridge_Pitch2.0mm_Drill0.7mm.wrl" + (offset + (xyz 0 0 0) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 0) + ) + ) + ) + (gr_rect + (start 134.659755 91.720974) + (end 144.39064 98.204018) + (stroke + (width 0.05) + (type default) + ) + (fill none) + (layer "Edge.Cuts") + (uuid "d39fdf5e-1d58-48ca-93a7-ec96883ae32a") + ) + (gr_text "There should be no schematic parity errors\nhere because NC pads share a common \nprefix with the test point" + (at 128.318133 89.631558 0) + (layer "F.Fab") + (uuid "93b20610-b7a1-4193-abe4-582a88122aa9") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + (justify left bottom) + ) + ) +) diff --git a/qa/data/pcbnew/unconnected-netnames/unconnected-netnames.kicad_pro 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a/qa/data/pcbnew/unconnected-netnames/unconnected-netnames.kicad_sch b/qa/data/pcbnew/unconnected-netnames/unconnected-netnames.kicad_sch new file mode 100644 index 0000000000..6b00d1a788 --- /dev/null +++ b/qa/data/pcbnew/unconnected-netnames/unconnected-netnames.kicad_sch @@ -0,0 +1,187 @@ +(kicad_sch + (version 20231120) + (generator "eeschema") + (generator_version "8.0") + (uuid "cfc6d250-9e5a-468d-b657-8add217d4593") + (paper "A4") + (lib_symbols + (symbol "Connector:TestPoint" + (pin_numbers hide) + (pin_names + (offset 0.762) hide) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (property "Reference" "TP" + (at 0 6.858 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "TestPoint" + (at 0 5.08 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "" + (at 5.08 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 5.08 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "test point" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "ki_keywords" "test point tp" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "ki_fp_filters" "Pin* Test*" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (symbol "TestPoint_0_1" + (circle + (center 0 3.302) + (radius 0.762) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + ) + (symbol "TestPoint_1_1" + (pin passive line + (at 0 0 90) + (length 2.54) + (name "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + ) + ) + ) + (no_connect + (at 91.44 63.5) + (uuid "28c6e503-9939-43fd-a3cf-6ff1f45e7b12") + ) + (symbol + (lib_id "Connector:TestPoint") + (at 91.44 63.5 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (fields_autoplaced yes) + (uuid "b198df71-7d13-4632-9ab4-7f217c917f8e") + (property "Reference" "TP1" + (at 93.98 58.9279 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Value" "TestPoint" + (at 93.98 61.4679 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "TestPoint:TestPoint_Bridge_Pitch2.0mm_Drill0.7mm" + (at 96.52 63.5 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 96.52 63.5 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "test point" + (at 91.44 63.5 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "9edaec62-6ceb-4783-bd76-03a1786b60f5") + ) + (instances + (project "unconnected-netnames" + (path "/cfc6d250-9e5a-468d-b657-8add217d4593" + (reference "TP1") + (unit 1) + ) + ) + ) + ) + (sheet_instances + (path "/" + (page "1") + ) + ) +) diff --git a/qa/tests/pcbnew/drc/test_drc_regressions.cpp b/qa/tests/pcbnew/drc/test_drc_regressions.cpp index 041923c569..f4ee2fbae2 100644 --- a/qa/tests/pcbnew/drc/test_drc_regressions.cpp +++ b/qa/tests/pcbnew/drc/test_drc_regressions.cpp @@ -62,7 +62,8 @@ BOOST_FIXTURE_TEST_CASE( DRCFalsePositiveRegressions, DRC_REGRESSION_TEST_FIXTUR "issue11814", // Bad cache hit in isInsideArea "issue12609", // Arc collison edge case "issue14412", // Solder mask bridge between pads in a net-tie pad group - "issue15280" // Very wide spokes mis-counted as being single spoke + "issue15280", // Very wide spokes mis-counted as being single spoke + "unconnected-netnames/unconnected-netnames", // Raised false schematic partity error }; for( const wxString& relPath : tests )