From f97c50bfde5b8a8a99b4ae681155e32710beb080 Mon Sep 17 00:00:00 2001 From: Jeff Young Date: Fri, 24 Jul 2020 01:25:34 +0100 Subject: [PATCH] Give excluded DRC items their own layer. (And fix a bug with the new mulit-layer zones and rule-based keepouts at the same time which prevented me from testing it.) Fixes https://gitlab.com/kicad/code/kicad/issues/4954 --- common/layer_id.cpp | 3 +++ common/settings/color_settings.cpp | 1 + include/layers_id_colors_and_visibility.h | 1 + pcbnew/class_marker_pcb.cpp | 8 +++++++- pcbnew/class_zone.h | 5 +++++ pcbnew/drc/drc.cpp | 2 +- pcbnew/drc/drc_rule.cpp | 8 ++++++++ pcbnew/pcb_draw_panel_gal.cpp | 10 +++++----- pcbnew/pcb_layer_widget.cpp | 1 + 9 files changed, 32 insertions(+), 7 deletions(-) diff --git a/common/layer_id.cpp b/common/layer_id.cpp index 1c569c62ff..7ba630ccc3 100644 --- a/common/layer_id.cpp +++ b/common/layer_id.cpp @@ -188,6 +188,9 @@ wxString LayerName( int aLayer ) case LAYER_DRC_ERROR: return _( "DRC Errors" ); + case LAYER_DRC_EXCLUSION: + return _( "DRC Exclusions" ); + case LAYER_ANCHOR: return _( "Anchors" ); diff --git a/common/settings/color_settings.cpp b/common/settings/color_settings.cpp index 0e6b4de1f4..192be8dfa4 100644 --- a/common/settings/color_settings.cpp +++ b/common/settings/color_settings.cpp @@ -126,6 +126,7 @@ COLOR_SETTINGS::COLOR_SETTINGS( std::string aFilename ) : CLR( "board.cursor", LAYER_CURSOR, COLOR4D( WHITE ) ); CLR( "board.drc_error", LAYER_DRC_ERROR, COLOR4D( PURERED ) ); CLR( "board.drc_warning", LAYER_DRC_WARNING, COLOR4D( PUREYELLOW ) ); + CLR( "board.drc_exclusion", LAYER_DRC_EXCLUSION, COLOR4D( WHITE ) ); CLR( "board.footprint_text_back", LAYER_MOD_TEXT_BK, COLOR4D( BLUE ) ); CLR( "board.footprint_text_front", LAYER_MOD_TEXT_FR, COLOR4D( LIGHTGRAY ) ); CLR( "board.footprint_text_invisible", LAYER_MOD_TEXT_INVISIBLE, COLOR4D( LIGHTGRAY ) ); diff --git a/include/layers_id_colors_and_visibility.h b/include/layers_id_colors_and_visibility.h index 7c5499c4a0..41cbde3e29 100644 --- a/include/layers_id_colors_and_visibility.h +++ b/include/layers_id_colors_and_visibility.h @@ -195,6 +195,7 @@ enum GAL_LAYER_ID: int LAYER_VIAS_HOLES, ///< to draw via holes (pad holes do not use this layer) LAYER_DRC_ERROR, ///< layer for drc markers with SEVERITY_ERROR LAYER_DRC_WARNING, ///< layer for drc markers with SEVERITY_WARNING + LAYER_DRC_EXCLUSION, ///< layer for drc markers which have been individually excluded LAYER_WORKSHEET, ///< worksheet frame LAYER_GP_OVERLAY, ///< general purpose overlay LAYER_SELECT_OVERLAY, ///< currently selected items overlay diff --git a/pcbnew/class_marker_pcb.cpp b/pcbnew/class_marker_pcb.cpp index 1a17bf6cbb..8732327bc3 100644 --- a/pcbnew/class_marker_pcb.cpp +++ b/pcbnew/class_marker_pcb.cpp @@ -159,6 +159,12 @@ void MARKER_PCB::ViewGetLayers( int aLayers[], int& aCount ) const { aCount = 1; + if( IsExcluded() ) + { + aLayers[0] = LAYER_DRC_EXCLUSION; + return; + } + BOARD_ITEM_CONTAINER* ancestor = GetParent(); while( ancestor->GetParent() ) @@ -178,7 +184,7 @@ void MARKER_PCB::ViewGetLayers( int aLayers[], int& aCount ) const GAL_LAYER_ID MARKER_PCB::GetColorLayer() const { if( IsExcluded() ) - return LAYER_AUX_ITEMS; + return LAYER_DRC_EXCLUSION; BOARD_ITEM_CONTAINER* ancestor = GetParent(); diff --git a/pcbnew/class_zone.h b/pcbnew/class_zone.h index b169f0fa67..e8aac5ba43 100644 --- a/pcbnew/class_zone.h +++ b/pcbnew/class_zone.h @@ -594,6 +594,11 @@ public: } } + bool HasFilledPolysForLayer( PCB_LAYER_ID aLayer ) const + { + return m_FilledPolysList.count( aLayer ) > 0; + } + /** * Function GetFilledPolysList * returns a reference to the list of filled polygons. diff --git a/pcbnew/drc/drc.cpp b/pcbnew/drc/drc.cpp index 320ce03be0..bb1b431696 100644 --- a/pcbnew/drc/drc.cpp +++ b/pcbnew/drc/drc.cpp @@ -1251,7 +1251,7 @@ wxPoint DRC::GetLocation( TRACK* aTrack, ZONE_CONTAINER* aConflictZone ) PCB_LAYER_ID l = aTrack->GetLayer(); - if( aConflictZone->IsFilled() ) + if( aConflictZone->IsFilled() && aConflictZone->HasFilledPolysForLayer( l ) ) conflictOutline = const_cast( &aConflictZone->GetFilledPolysList( l ) ); else conflictOutline = aConflictZone->Outline(); diff --git a/pcbnew/drc/drc_rule.cpp b/pcbnew/drc/drc_rule.cpp index 7ffe21625e..8df921ca30 100644 --- a/pcbnew/drc/drc_rule.cpp +++ b/pcbnew/drc/drc_rule.cpp @@ -113,6 +113,14 @@ DRC_RULE_CONDITION::~DRC_RULE_CONDITION() bool DRC_RULE_CONDITION::EvaluateFor( const BOARD_ITEM* aItemA, const BOARD_ITEM* aItemB ) { + // An unconditional rule is always true + if( m_Expression.IsEmpty() ) + return true; + + // A rule which failed to compile is always false + if( !m_ucode ) + return false; + BOARD_ITEM* a = const_cast( aItemA ); BOARD_ITEM* b = aItemB ? const_cast( aItemB ) : DELETED_BOARD_ITEM::GetInstance(); diff --git a/pcbnew/pcb_draw_panel_gal.cpp b/pcbnew/pcb_draw_panel_gal.cpp index 077373c719..38efddf56a 100644 --- a/pcbnew/pcb_draw_panel_gal.cpp +++ b/pcbnew/pcb_draw_panel_gal.cpp @@ -53,7 +53,7 @@ const LAYER_NUM GAL_LAYER_ORDER[] = { LAYER_GP_OVERLAY, LAYER_SELECT_OVERLAY, - LAYER_DRC_ERROR, LAYER_DRC_WARNING, + LAYER_DRC_ERROR, LAYER_DRC_WARNING, LAYER_DRC_EXCLUSION, LAYER_PADS_NETNAMES, LAYER_VIAS_NETNAMES, Dwgs_User, Cmts_User, Eco1_User, Eco2_User, Edge_Cuts, @@ -289,10 +289,10 @@ void PCB_DRAW_PANEL_GAL::SetTopLayer( PCB_LAYER_ID aLayer ) // Layers that should always have on-top attribute enabled const std::vector layers = { - LAYER_VIA_THROUGH, LAYER_VIAS_HOLES, LAYER_VIAS_NETNAMES, - LAYER_PADS_TH, LAYER_PADS_PLATEDHOLES, LAYER_PADS_NETNAMES, - LAYER_NON_PLATEDHOLES, LAYER_SELECT_OVERLAY, LAYER_GP_OVERLAY, - LAYER_RATSNEST, LAYER_DRC_ERROR, LAYER_DRC_WARNING + LAYER_VIA_THROUGH, LAYER_VIAS_HOLES, LAYER_VIAS_NETNAMES, LAYER_PADS_TH, + LAYER_PADS_PLATEDHOLES, LAYER_PADS_NETNAMES, LAYER_NON_PLATEDHOLES, + LAYER_SELECT_OVERLAY, LAYER_GP_OVERLAY, LAYER_RATSNEST, LAYER_DRC_ERROR, + LAYER_DRC_WARNING, LAYER_DRC_EXCLUSION }; for( auto layer : layers ) diff --git a/pcbnew/pcb_layer_widget.cpp b/pcbnew/pcb_layer_widget.cpp index 896f3c0bf6..c0bcb85313 100644 --- a/pcbnew/pcb_layer_widget.cpp +++ b/pcbnew/pcb_layer_widget.cpp @@ -71,6 +71,7 @@ const LAYER_WIDGET::ROW PCB_LAYER_WIDGET::s_render_rows[] = { RR( _( "No-Connects" ), LAYER_NO_CONNECTS, BLUE, _( "Show a marker on pads which have no net connected" ) ), RR( _( "DRC Warnings" ), LAYER_DRC_WARNING, YELLOW, _( "DRC violations with a Warning severity" ) ), RR( _( "DRC Errors" ), LAYER_DRC_ERROR, PURERED, _( "DRC violations with an Error severity" ) ), + RR( _( "DRC Exclusions" ), LAYER_DRC_EXCLUSION, WHITE, _( "DRC violations which have been individually excluded" ) ), RR( _( "Anchors" ), LAYER_ANCHOR, WHITE, _( "Show footprint and text origins as a cross" ) ), RR( _( "Worksheet" ), LAYER_WORKSHEET, DARKRED, _( "Show worksheet") ), RR( _( "Cursor" ), LAYER_CURSOR, WHITE, _( "PCB Cursor" ), true, false ),