Jeff Young
d16b23d16e
Name shortening and line-break reduction.
2022-10-21 18:41:39 +01:00
Roberto Fernandez Bautista
fa5dc23797
CADSTAR PCB: Fix regression when loading pads in footprints
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Zero sized pads can be valid - e.g. a through hole pad
2022-09-04 00:59:57 +02:00
Roberto Fernandez Bautista
9abf3438b8
CADSTAR PCB: Invert logic for guessing which layer is top / bottom
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Ensures correct automatic layer mapping is applied to the design in
https://gitlab.com/kicad/code/kicad/-/issues/12349
2022-09-04 00:59:57 +02:00
Roberto Fernandez Bautista
c961624d43
CADSTAR PCB: Load 2-point polygons as line segments
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Fixes asserts when loading design from https://gitlab.com/kicad/code/kicad/-/issues/12349
2022-09-04 00:59:57 +02:00
Roberto Fernandez Bautista
21b3753e9b
CADSTAR PCB: Parse Teardrops
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Todo: We need to figure out how we will load teardrops. For now
just drop them on import.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/12349
2022-09-04 00:59:56 +02:00
Jeff Young
ec51955dad
Remove vestiges of old pad locking system.
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We now use a session preference (Allow free pads) in the board editor,
and we never supported pad locking in the footprint editor.
2022-08-23 18:02:16 +01:00
Seth Hillbrand
4b63c7012d
Silence some clang warnings
2022-08-22 12:54:00 -07:00
Jeff Young
a9536b5de9
CHANGED netclass assignments now done via canvas or via patterns.
2022-08-14 22:56:29 +01:00
Roberto Fernandez Bautista
6b349fdb0a
CADSTAR PCB: Allow remapping all non-electrical layers
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/12196
2022-08-14 22:24:17 +01:00
Roberto Fernandez Bautista
69d696660b
cadstar: Report warning that imported text may be different
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/12195
2022-08-14 22:24:16 +01:00
Seth Hillbrand
2ee65b2d83
Force removal of zero-sized pads on load.
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Pads with zero width or height cause issues when rendering and
selecting. KiCad has never allowed these elements but hasn't prevented
importing systems where they exist. This prevents their import and
cleans existing designs where the pads are placed
Fixes https://gitlab.com/kicad/code/kicad/issues/12200
2022-08-13 19:10:48 -07:00
luz paz
af6ba1a16e
Fix typos in pcbnew sub-directory
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Found via `codespell -q 3 -S *.po,./thirdparty,./Documentation/changelogs -L aactual,acount,aline,alocation,alog,anormal,anumber,aother,apoints,aparent,aray,ba,busses,dout,einstance,leaded,modul,ontext,ot,overide,serie,te,,tesselate,tesselator,tht`
2022-06-30 09:39:45 -04:00
Jeff Young
843a56c4e4
Implement two-staged zone priority: assigned priority followed by UUID.
2022-03-01 14:53:35 +00:00
Jeff Young
327ddad79f
Performance: get rid of rawPolys / finalPolys distinction.
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(The final fractured polys are required, and we don't really ever use
the raw polys anyway, so they were removed.)
2022-02-16 15:33:12 +00:00
Jeff Young
2172810600
Performance: better sharing of zone fills.
2022-02-15 19:19:03 +00:00
Jeff Young
3deaf902bb
Retire the V5 zone fill algorithm.
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Fixes https://gitlab.com/kicad/code/kicad/issues/10578
2022-02-11 13:10:52 +00:00
Jeff Young
b2e3f03222
More wide-string declarations.
2022-02-05 22:03:04 +00:00
Jeff Young
9582457fef
Be explicit about literal wide-strings.
2022-02-05 20:40:21 +00:00
Roberto Fernandez Bautista
290354e3f6
CADSTAR: Fix potential nullptr dereferencing bug
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Don't assume the footprint will have the pad index that the file references.
2022-02-05 19:20:56 +00:00
Jeff Young
4a05b36bc6
Prefer EDA_ANGLE to naked radians.
2022-01-20 21:10:04 +00:00
Jeff Young
038db715a3
Move zone hatch orientation to EDA_ANGLE.
2022-01-19 00:34:03 +00:00
Jeff Young
e84c574830
Some more EDA_ANGLE cleanup.
2022-01-16 19:16:18 +00:00
Jeff Young
07013d00e1
More EDA_ANGLE.
2022-01-14 16:08:19 +00:00
Jeff Young
1b19ff5f42
More EDA_ANGLE changes.
2022-01-14 16:08:19 +00:00
Jeff Young
c9487bad18
Move BOARD_ITEM::Rotate() to EDA_ANGLE.
2022-01-14 16:08:19 +00:00
Jeff Young
abd3f5bc2b
Move footprints to EDA_ANGLE.
2022-01-14 16:08:18 +00:00
Jeff Young
d485eb2514
Move pads to EDA_ANGLE.
2022-01-14 16:08:18 +00:00
Marek Roszko
726d873c53
Tear down the wxPoint trigo helpers
2022-01-04 21:23:11 -05:00
Marek Roszko
c4c56de708
Neurotically update position wxPoint usages
2022-01-01 11:55:51 -05:00
Jeff Young
86cb57f4a7
Cherry-pick TEXT_ATTRIBUTES and EDA_ANGLE from rockola/kicad-strokefont
2021-12-28 22:15:20 +00:00
Jeff Young
fa908e1f98
Dimensions for footprints.
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Fixes https://gitlab.com/kicad/code/kicad/issues/8441
2021-12-24 21:10:28 +00:00
Jeff Young
2bc86fa0a8
Shapes for schematic.
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ADDED arc, circle and rectangle shapes for schematic. Shapes support
line styles and fill colors.
CHANGED sheet background color in Edit Text & Graphics Properties to
fill color (and it now affects shapes).
Pushed STROKE_PARAMS down into common and moved all shapes to using it
for stroke descriptions.
2021-12-23 20:36:07 +00:00
Roberto Fernandez Bautista
13f081549c
CADSTAR PCB: Use all User layers when mapping documentation layers
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/9577
2021-11-10 21:47:22 +00:00
Roberto Fernandez Bautista
ad2e780a2c
CADSTAR PCB: Correctly load pads with holes
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If the THROUGH_HOLE attribute isn't set, it just means that the pads
are only present on one side of the board, but there can still be a
plated / non-plated hole.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/9579
2021-11-10 21:21:32 +00:00
Seth Hillbrand
6cc6f06a9a
Millimetres -> Millimeters
2021-11-08 15:56:51 -08:00
Seth Hillbrand
6569337d27
Haching -> Hatching
2021-11-08 15:56:51 -08:00
Roberto Fernandez Bautista
6aa7602c32
CADSTAR PCB: Reverse anticlockwise arcs before adding to the chain
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/9533
2021-11-05 17:13:02 +00:00
Roberto Fernandez Bautista
8314251fa1
CADSTAR PCB: Force white silkscreen and green soldermask
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We don't know the actual colour from the design, but this is the most
common used in the industry.
2021-11-05 17:13:02 +00:00
Roberto Fernandez Bautista
b2db24f275
CADSTAR PCB: Don't invert Text Angle for mirrored text
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It matches the original cadstar when we don't invert
2021-10-30 18:14:23 +01:00
Roberto Fernandez Bautista
99442350a4
CADSTAR PCB: Fix loading of arc tracks following recent PCB_ARC changes
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We no longer have any knowledge of the original start/end of the arc,
since SetArcAngleAndEnd swaps the start and end to ensure the arc is
always clockwise at the end.
Adds a method EDA_SHAPE::EndsSwapped() to notify whether the start/end
point of the shape were swapped.
2021-10-17 17:57:51 +01:00
Roberto Fernandez Bautista
e867a4fd27
CADSTAR PCB: Fix Zone fill priorities
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The algorithm now correctly determines fill priorities when the zone
outlines are close together and within the minimum clearance between
zones.
2021-10-16 21:50:56 +01:00
Jeff Young
9b9e379aa0
Overhaul arc internal model to not over-specify information.
2021-10-15 12:45:43 +01:00
Jeff Young
8b08c9e53f
Shorter names before things get out of hand.
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Also, remove comments indicating CURVE is a Bezier. Just call it a
BEZIER.
2021-10-15 12:45:43 +01:00
Jeff Young
a41944020d
Push most of PCB_SHAPE impl down in to EDA_SHAPE.
2021-10-15 12:45:43 +01:00
Roberto Fernandez Bautista
43e59b0ea7
CADSTAR PCB: Correctly handle associated pad ids and PCB Only pads
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Fixes https://gitlab.com/kicad/code/kicad/-/issues/9372
2021-10-11 18:30:20 +01:00
Roberto Fernandez Bautista
7a71ebf9ac
CADSTAR PCB: Load all three net properties into a single Netclass
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The final netclass name will be a bit long but it will allow for custom
DRC rules to individually target each of the three properties available
in CADSTAR:
- Route Code (which specifies width of the track in min, max, opt)
- Net class (only used in signal integrity analysis)
- Spacing class (for specifying clearance requirements between classes)
2021-10-10 22:16:08 +01:00
Roberto Fernandez Bautista
ac3ade874e
CADSTAR PCB: Set Copper-to-Hole clearance as 0
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Testing suggests that CADSTAR doesn't actually have any clearance to the
hole (other than electrical clearance to the barrel of the padstack/
viastack).
This removes a large amount of DRC violations on imported designs.
2021-10-10 00:20:13 +01:00
Roberto Fernandez Bautista
eb7d0fdf8a
CADSTAR PCB: Use board clearance + additional isolation as zone clearance
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Copper-to-copper clearance is too onerous and results in large amount
of DRC errors for the majority of imported designs.
2021-10-10 00:18:36 +01:00
Roberto Fernandez Bautista
f4ff01a5ab
CADSTAR PCB: Copy default netclass settings when creating new ones
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Ensures that the global clearance is preserved in the newly created
netclass.
2021-10-09 23:10:55 +01:00
Roberto Fernandez Bautista
8f74085ca4
CADSTAR PCB: Handle older boards without construction layers
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Use KiCad default stackup for older CADSTAR boards that do not
define any dielectric layers between the electrical layers.
Also fix default stackup calculation to ensure finished board thickness
is 1.6mm
2021-10-09 21:26:16 +01:00