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150 Commits

Author SHA1 Message Date
Roberto Fernandez Bautista 99442350a4 CADSTAR PCB: Fix loading of arc tracks following recent PCB_ARC changes 
We no longer have any knowledge of the original start/end of the arc,
since SetArcAngleAndEnd swaps the start and end to ensure the arc is
always clockwise at the end.

Adds a method EDA_SHAPE::EndsSwapped() to notify whether the start/end
point of the shape were swapped.
 2021-10-17 17:57:51 +01:00
Roberto Fernandez Bautista e867a4fd27 CADSTAR PCB: Fix Zone fill priorities 
The algorithm now correctly determines fill priorities when the zone
outlines are close together and within the minimum clearance between
zones.
 2021-10-16 21:50:56 +01:00
Jeff Young 9b9e379aa0 Overhaul arc internal model to not over-specify information. 2021-10-15 12:45:43 +01:00
Jeff Young 8b08c9e53f Shorter names before things get out of hand. 
Also, remove comments indicating CURVE is a Bezier.  Just call it a
BEZIER.
 2021-10-15 12:45:43 +01:00
Jeff Young a41944020d Push most of PCB_SHAPE impl down in to EDA_SHAPE. 2021-10-15 12:45:43 +01:00
Roberto Fernandez Bautista 43e59b0ea7 CADSTAR PCB: Correctly handle associated pad ids and PCB Only pads 
Fixes https://gitlab.com/kicad/code/kicad/-/issues/9372
 2021-10-11 18:30:20 +01:00
Roberto Fernandez Bautista 7a71ebf9ac CADSTAR PCB: Load all three net properties into a single Netclass 
The final netclass name will be a bit long but it will allow for custom
DRC rules to individually target each of the three properties available
in CADSTAR:
- Route Code (which specifies width of the track in min, max, opt)
- Net class (only used in signal integrity analysis)
- Spacing class (for specifying clearance requirements between classes)
 2021-10-10 22:16:08 +01:00
Roberto Fernandez Bautista ac3ade874e CADSTAR PCB: Set Copper-to-Hole clearance as 0 
Testing suggests that CADSTAR doesn't actually have any clearance to the
hole (other than electrical clearance to the barrel of the padstack/
viastack).

This removes a large amount of DRC violations on imported designs.
 2021-10-10 00:20:13 +01:00
Roberto Fernandez Bautista eb7d0fdf8a CADSTAR PCB: Use board clearance + additional isolation as zone clearance 
Copper-to-copper clearance is too onerous and results in large amount
of DRC errors for the majority of imported designs.
 2021-10-10 00:18:36 +01:00
Roberto Fernandez Bautista f4ff01a5ab CADSTAR PCB: Copy default netclass settings when creating new ones 
Ensures that the global clearance is preserved in the newly created
netclass.
 2021-10-09 23:10:55 +01:00
Roberto Fernandez Bautista 8f74085ca4 CADSTAR PCB: Handle older boards without construction layers 
Use KiCad default stackup for older CADSTAR boards that do not
define any dielectric layers between the electrical layers.

Also fix default stackup calculation to ensure finished board thickness
is 1.6mm
 2021-10-09 21:26:16 +01:00
Roberto Fernandez Bautista 33a3cfc87b CADSTAR PCB: Update Board Design Settings to notify that a stackup exists 
Also update thickness of the PCB

Fixes https://gitlab.com/kicad/code/kicad/-/issues/9307
 2021-10-09 20:33:14 +01:00
Roberto Fernandez Bautista e80a1c2679 CADSTAR PCB: Don't load items on invalid layers 
This was happening in two cases:
- Loading documentation symbols (CADSTAR on purpose defines these in an
  invalid layer)
- When an item was in a "layer set" such as ALLELEC or ALLLAYER - need to
  make sure we remove the copper layers that are not active in the design
 2021-10-09 20:07:23 +01:00
Roberto Fernandez Bautista 677166f0b8 CADSTAR PCB: Rule Areas have zero width 
Cadstar areas have a line width but this is only for display purposes.
Instead CADSTAR uses the center line when determining whether a DRC
violation occurred.
 2021-10-08 21:27:32 +01:00
Roberto Fernandez Bautista 2dfbd42be6 CADSTAR PCB: Legacy netclass and design settings loading is required 2021-10-08 20:48:10 +01:00
Roberto Fernandez Bautista ae0229b7c9 CADSTAR PCB: Add imported nets to the imported netclass. 2021-10-08 20:25:09 +01:00
Roberto Fernandez Bautista 58fc4f512d CADSTAR PCB: Don't create zero width tracks 
Fixes a bug in the route offsetting part of the import
that was resulting in zero-width tracks being imported.
 2021-10-08 20:25:09 +01:00
Roberto Fernandez Bautista 16b61e47cd CADSTAR PCB: Clear arcs from polys before boolean ops (e.g. zone fills) 2021-10-08 20:25:09 +01:00
Roberto Fernandez Bautista fb588da875 CADSTAR PCB: Fix loading of thermal relief gap in zones 
We were loading as solid fill when the relief gap was exactly the
same as the minimum width.

Also we can do better than just load as solid fill when it is smaller:
we can instead just use the minimum width and at least it still will
have thermal reliefs.
 2021-10-08 17:39:08 +01:00
Roberto Fernandez Bautista cb47bf25c0 CADSTAR PCB: Actually load the original route code as a KiCad NETCLASS 
We weren't actually loading it into the design settings even though
everything else was already being correctly loaded.
 2021-10-07 22:13:06 +01:00
Roberto Fernandez Bautista 625e56676a Add progress reporting to CADSTAR Schematic & PCB importers 
Fixes https://gitlab.com/kicad/code/kicad/-/issues/8685
 2021-09-11 17:50:19 +01:00
Jeff Young e6ca9837a2 Clear numbers from non-numberable pads and don't run DRC on them. 
This was also the last straw on the misnamed PAD::GetName() and
PAD::SetName(), which are now PAD::GetNumber() and PAD::SetNumber().

Fixes https://gitlab.com/kicad/code/kicad/issues/9017
 2021-08-24 01:03:06 +01:00
Jeff Young f221220fe2 Rename layer ids file. 
It hasn't had anything to do with colors or visibility for some time
now.
 2021-07-29 16:03:25 +01:00
Wayne Stambaugh 37b200cb3e Pass wxString objects by reference instead of on the stack. 2021-07-27 08:41:27 -04:00
Wayne Stambaugh 8fd83cbb95 Pass wxPoint objects by reference instead of on the stack. 2021-07-26 15:35:33 -04:00
Jeff Young 0fb864d596 Pull some name changes back from 7.0 to ease merging. 2021-07-21 20:58:59 +01:00
Wayne Stambaugh cf00319c85 More NULL expunging. 2021-07-20 07:27:18 -04:00
Jeff Young e61822c9e0 Naming conventions and a bug fix on arc points. 2021-07-19 13:17:12 +01:00
Jeff Young 062c4fda62 More error message regularization (and translatability improvements). 2021-06-28 00:45:24 +01:00
Jeff Young 0dfb5fcaf9 Error message cleanup. 
wxString::Format is redundant in a wxLogXXX call.
Error messages should generally be translatable.
Error messages should use generally consistent sentence forms.
 2021-06-26 22:53:24 +01:00
Jeff Young 81fc710a5d Use consistent terminology. 
Fixes https://gitlab.com/kicad/code/kicad/issues/8681
 2021-06-26 10:11:41 +01:00
Jeff Young 5fa5a73c6d File open/import progress dialogs. 
Fixes https://gitlab.com/kicad/code/kicad/issues/6864

Fixes https://gitlab.com/kicad/code/kicad/issues/2166
 2021-06-23 23:55:54 +01:00
Jeff Young 096e342386 Prefix TRACK, ARC and VIA. 2021-06-11 22:07:02 +01:00
Jeff Young 16b0147af8 Prefix DIMENSION types. 2021-06-11 17:59:44 +01:00
luz paz f968fc8719 Fix source comment / documentation typos 2021-06-09 19:32:58 +00:00
Marek Roszko 10e60acf34 Clean up including of board_design_settings.h 2021-06-06 15:03:42 -04:00
Marek Roszko 581ba21865 Remove wx includes out of cadstar_archive_loader.h 2021-06-06 09:28:02 -04:00
Ian McInerney 4f05262705 Cleanup includes in board.h and footprint.h 2021-06-03 20:19:52 +01:00
Ian McInerney 23f8851409 Remove pcb_group include from board header 2021-06-03 20:03:31 +01:00
Marek Roszko af2707929d Don't leak a wx header via eda_item.h 
Turns out this provided the translation header globally :D
 2021-06-02 19:18:48 -04:00
Marek Roszko a7d1ef9927 Fix some more uninitialized warnings 
From PVS Studio
 2021-05-30 20:05:37 -04:00
Marek Roszko 03cf2b517f Enum class PAD_ATTR_T 
Renamed such that python stays the same
 2021-05-01 10:51:54 -04:00
Marek Roszko b243c2280d enum class PAD_SHAPE_T 2021-05-01 08:22:35 -04:00
Marek Roszko 21fde9b629 enum class PCB_SHAPE_TYPE_T 2021-04-30 22:36:12 -04:00
jean-pierre charras e27733587d Fix 2 minor Coverity warnings. 2021-04-23 19:57:36 +02:00
Roberto Fernandez Bautista edb2136a0d CADSTAR PCB: KiCad's minimum permitted Through Drill is 0.0508mm(2mils) 2021-04-12 20:25:05 +01:00
Roberto Fernandez Bautista a3196a11a7 CADSTAR PCB: Be more specific with "allow thermal pads" DRC hack 
Only tag the footprint as such when we know it has overlaping copper
over the pads with different pad numbers
 2021-04-12 20:25:05 +01:00
Roberto Fernandez Bautista b5edd5f6a5 CADSTAR PCB: Fix loading of thermal pads 
- Create a pad if a component copper is associated with any other pads
  in the footprint.
- Rename/renumber 'PCB Only' pads that are associated with a component
  copper and make them all use the same pad name/number.
 2021-04-12 20:25:05 +01:00
Jeff Young 2cde76a191 Don't do any hole clearance testing within a single footprint. 
Fixes https://gitlab.com/kicad/code/kicad/issues/8141
 2021-04-11 16:03:16 +01:00
Jeff Young 3450610977 Add ability to allow thermal vias to be implemented as pads. 
This is mostly just for CADSTAR.  Since we don't (yet) have general
purpose footprint attributes, this reuses the "net tie" hack.

Fixes https://gitlab.com/kicad/code/kicad/issues/8141
 2021-04-09 14:02:13 +01:00