fd62c42ded
Update demos
2020-10-25 18:50:20 +01:00
515e57c02f
demo update.
2020-04-15 15:31:40 +02:00
2b3451ff6d
demo update
2020-01-19 20:29:29 +01:00
37f06eb2b7
Update demo
2019-09-19 18:05:29 +02:00
e7adb92930
Update demo
2019-09-17 18:54:06 +02:00
196ddec81c
Update demos to use recent footprints.
2019-04-07 16:06:53 +02:00
2121142d3c
Demo pic_programmer: remove unused schematic library from list.
2019-03-17 08:44:52 +01:00
03fa645743
pic_programmer demo: fix a typo in a symbol name.
2018-06-18 08:12:17 +02:00
ae02039ed4
Update pic_programmer demo
2018-06-17 09:28:36 +02:00
0d4d24ed22
Update demos.
2018-06-14 09:52:23 +02:00
8a70acb821
Update demos to use V5 libraries.
2018-05-08 15:29:21 +02:00
cb134fd065
Update demos
2018-04-09 19:37:17 +02:00
e926ec42f8
Update demo
2018-01-11 11:45:43 +01:00
81357eb584
Update demo to use latest libraries.
2017-12-07 18:28:11 +01:00
687444b973
update demo
2017-12-02 09:52:02 +01:00
353e91a6f8
Update demos
2017-11-21 21:26:06 +01:00
9a0d346afa
Minor update: pic_programmer demo: use current (updated) components instead of old ones in schematic and board.
2016-06-26 16:43:18 +02:00
ecad3ad235
Netlist generator: avoid changing the order of parts in libparts section each time libraries are reloaded.
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pic_programmer demo: very minor fix and update netlist.
cached_container.cpp: more info when the message "Out of memory" is displayed.
2015-11-05 17:28:31 +01:00
ae506e8223
polygons in footprint body: fix incorrect calculation of polygons with clearance or outline thickness (fix bug #1511366 )
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Clean demos
2015-11-02 10:24:32 +01:00
acc19096c3
Demos: fix 3D models (bug 1500956) kit/pic/sonde/test_xil/video
2015-10-03 01:14:48 +09:00
e25ba1f51e
Demos: make a private library for each demo, to avoid issues when using modified kicad new schematic libraries
2015-05-18 09:15:25 +02:00
ff154dba3c
demos/ schematic tidying
2015-03-28 13:24:13 +01:00
6bae852cb9
Minor fixes: specctra export: skip malformed circles (having a radius = 0) in board outline creation, which can crash 3d-viewer or vrml export.
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dialog_fp_lib_table: remember during a session the last open table (global or local).
drawing_tool: fix compil warning
Update demos.
2014-09-22 09:51:06 +02:00
06f59a94ed
eeschema: Find Replace: fix a bug in replace command: sometimes, the string to replace was found, but not replaced if this string contained lower case letters.
2014-09-01 17:28:29 +02:00
3814cdaff1
Pcbnew: Minor fix in hotkeys. Demos: add an example to use a local fp-lib-table and local libs, and update schematics and boards.
2014-08-31 18:19:07 +02:00
fe919cd456
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 20:42:34 +01:00
234c4a3814
$ iconv -f LATIN1 -t UTF-8 pic_sockets.sch -o /tmp/pic_sockets.sch
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convert to UTF-8, eeschema cannot load LATIN1 strings anymore.
2013-07-28 10:21:43 -05:00
8ccf0320b4
1) Add "rules" to base of tree for copying into BZR_HOME/rules.
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File "rules" has instructional text as comments near top.
2) Convert all text files in repo to LF line ending form.
Any checkout done with "rules" in play will convert the working
tree to native line ending, while keeping repo as LF line ending.
2013-05-25 23:36:44 -05:00
8d22086097
AUTHORS.txt: add some contributor names (I certainly forgot some other contributors, and I apologize).
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Demos: convert .brd files to .kicad_pcb files and fix 2 broken files
2013-01-14 13:16:23 +01:00
95388c6ec4
eeschema: fix memory leakage.
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Pcbnew: fix a minor issue.
Version update.
2011-06-09 15:30:46 +02:00
61edf74377
Demo files cleanup and update
2010-12-04 18:38:41 +01:00
af7c26e8be
bitmap2component minor enhancements
2010-06-25 21:02:39 +02:00
3543ba65de
++eeschema:
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In netlist generation, changed the rule to calculate netnames of nets with labels:
Previously, named nets (i.e. nets with local, hierarchical or global labels) have their name
defined by the first label found in list.
So net names could be changed without really changing the schematic.
Now the names are calculated from the rules (by priority order) :
1 - use the most top level labels in hierarchies.
2 - use global labels first, local labels next (hidden power pins names are global labels).
3 - use alphabetic sort (so, if GND and AGND are connected, the net will be always named AGND,
and adding a VSS connection cannot change the net name)
So power nets and nets that have more than one label cannot have their netname changed
if there is no actual change relative to these nets names in schematic
2010-06-23 19:00:12 +02:00
02b88a7016
Use bin/plugins/ as install path for bitmap2component instead of bin/
2010-06-12 09:24:14 +02:00
a3a4bbc03b
pcbnew test scale values when printing/ploting to avoid 0 scale or others stupid values
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(scale now allowed from 0.01 to 100)
2009-01-18 19:20:15 +00:00
c333da1916
some "todo" cleanup
2009-01-18 15:51:06 +00:00
e4fdce4a47
minor update
2008-06-22 16:02:08 +00:00
0381261834
eeschema:
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* made schematic loading of 'GLabels' dependent on the schematic file version (currently at 2).
If the version == 1, these are loaded as hierarchal labels
* made text labels global in the herarchy, consistent with their historical usage.
2008-02-12 22:34:40 +00:00
bc21c746f8
2007-06-21 15:01:52 +00:00
dedb0228dc
add files not currently available in source (e.g. docs, modules, etc.)
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set svn:eol-style property to native for all ascii files to support cross platform development
2007-06-05 12:10:51 +00:00
jean-pierre charras
kinichiro
Dick Hollenbeck
charras