Also reduces line-wrapping a bit.
I don't think this fixes the linked bug, but I can't reproduce it
and this was found while reviewing the code.
Fixes https://gitlab.com/kicad/code/kicad/issues/8810
ADDED Eeschema-specific netclass settings including wire and bus
thickness, color, and line style.
Netclasses override individual wire & bus colors and line styles.
If that proves an issue we might look at something more sophisticated
with inheritance.
Fixes https://gitlab.com/kicad/code/kicad/issues/4581
Various architecture upgrades to support this.
Creating a BOARD now requires a valid PROJECT, which caused
some (mostly transparent) changes to the Python API internals.
ADDED: Project local settings file
CHANGED: Board design settings are no longer stored in PCB file
CHANGED: Net classes are no longer stored in PCB file
CHANGED: Importing board settings now reads boards, not just projects
Fixes https://gitlab.com/kicad/code/kicad/-/issues/2578
Fixes https://gitlab.com/kicad/code/kicad/-/issues/4070
Jeff Young
Marek Roszko
jean-pierre charras
Jon Evans