Instead of just checking for the zone outline, we adjust to check the
full fill area of the zones for intersection and overlaps
(cherry picked from commit 954b265839)
Aliases in bus resolution were being resolved without a path, making
them effectively global nets. This applies the corrected path to the
bus members and adds a QA to catch this error
The propagation is currently (maybe not needed) limited to the global
name that is the source of the change. We also need to propagate the
global name that is changed in case the global is set in a tree leaf and
not the root
Fixes https://gitlab.com/kicad/code/kicad/issues/14657
(cherry picked from commit 6e4de18e15)
A sheetpath is required to correctly resolve text variables.
Depending on currentSheet is rife with bugs.
There are many places where we do *not* want to be prepending
field names to the field values, such as netlisting,
building PDF hypertext menus, etc.
Also, Find/Replace needs to work on unresolved text, as
that's what we're going to display (and if replace nuked
your variable references you wouldn't be happy).
(cherry picked from commit b41d446f58)
Adds QA checks to copper sliver tests. Adds the following checks:
- Dot product between two arms (quickly avoids checks for >90°)
- Checks the sliver is convex (area test)
- Eliminates minor slivers with angles that are approximately 0 and ones
with the opposite side width beneath a configurable level
- Updates Clipper2 to fix a couple of jagged edges on inflate
- Adds simplify during zone fill inflation to limit jaggies
Fixes https://gitlab.com/kicad/code/kicad/issues/14549
(cherry picked from commit f7f52d77e4)
About 1/3 of callers to Parent() don't care if they get the immediate
parent or not, about 1/3 want only the immediate parent, and about 1/3
want the hole parent's Parent().
I had earlier changed PNS::ITEM::HOLE to override Parent() and return
the hole parent's Parent(), but since the callers are pretty evenly
split I've reverted that and added BoardItem() for callers who want the
eventual BOARD_ITEM (whether a direct parent or a grandparent).
(Also removes a dead routine so I didn't have to figure out which of
the two it wanted....)
(cherry picked from commit 6f0d963683)
- LINEs now own their vias optionally (depending whether a LINE with its VIA belongs to a node)
- get rid of unique_ptr on the internal NODE::Add API (and also made it private)
- make sure stack pointers are not added to the node
- use rvalue reference for NODE::Add/NODE::Replace
Manually rebased by Jeff Young <jeff@rokeby.ie> 5 April 2023
(cherry picked from commit d961cdce3f)
Rebased by Jeff Young <jeff@rokeby.ie> 5 April 2023
(Also includes a bug-fix for highlighting collisions with edge-cut
items.)
(cherry picked from commit bfbda978b8)
Previously, bus elements that were not instantiated as individual nets
could not connect to each other. This caused issues for complex
schematics where busses needed to connect to other busses with elements
that resolved to the same net names. Functionally, this means mixing
bus elements, which we will replace with first-class elements in version
8 but currently can only be accomplished either by using bus aliases and
this patch or by individually instantiating each bus element as a
local label
Fixes https://gitlab.com/kicad/code/kicad/issues/14300
(cherry picked from commit 16b4ec3c7e)
Also fixes a bug where all VDMOS instance parameters weren't marked as
instance parameters.
Also fixes a bug where VDMOS thermal models weren't supported (they
have two extra pins: Tj and Tcase).
(cherry picked from commit 5bda3b99f9)
While convoluted, this model matches as best we have found so far, the
alignment with scintilla. The spacing is character size for N-1 of the
characters in the 4-space tab stops. The final character is sized for
the actual space character in the stroke font (0.761905)
Fixes https://gitlab.com/kicad/code/kicad/issues/13791
(cherry picked from commit bce402a01c)
Fixes#12580
Additionally does not export no_connect netlist annotation on pins
which are both connected to another pin and a NC item, unless all
connected pins are stacked at the symbol level.
Adds testing of pin types to netlist QA unit tests.
(cherry picked from commit 9dca70a773)
Fractured polygons are always fractured along the x-axis, so when
checking to see if a segment is a fracture point, we check if the y
coordinate is equal. This avoids situations where there are multiple
fracture points between two inflection points
Additionally, we add a second check to ensure we don't hit spurious
blobs (all kinks should be symmetric and therefore be substantial in
each direction)
Fixes https://gitlab.com/kicad/code/kicad/issues/14130
(cherry picked from commit 7653a2bf99)
Fixes#10926
Contains the following changes:
- Adds a new ERC_SCH_PIN_CONTEXT class which is used to provide deterministic
comparison between items causing ERC violations (e.g. pins) when associated
with a SCH_SHEET_PATH context.
- Adds association of SCH_SHEET_PATHs for ERC_ITEMs and the sub-schematic items
which caused an ERC violation. This allows correct display of markers on the
sheets of interest only, and allows correct naming resolution and cross-probing
from the ERC dialog.
- Adds a new ERC_TREE_MODEL class, derived from RC_TREE_MODEL, which correctly
resolves component references across heirarchical sheets using the associated
SCH_SHEET_PATHs. This allows sheet-specific component references to be displayed
correctly in the ERC results tree.
- Updates SCH_MARKER to only draw sheet-specific markers on the sheet causing
an ERC violation.
- Increments the schematic file version.
- When loading a schematic with legacy ERC exclusions, discards those of type
ERCE_PIN_TO_PIN_WARNING, ERCE_PIN_TO_PIN_ERROR, ERCE_HIERACHICAL_LABEL, and
ERCE_DIFFERENT_UNIT_NET as there is no safe way to automatically infer the
information which is now stored with these exclusions (sheet paths for error
location and related items). Requiring users to (once) re-add exclusions is
preferable to silently incorrectly matching new ERC issues to legacy exclusions.
When the designer asks to reset annotations, we reset all annotations
including power symbols. This may create additional churn in the files
but only when requested and is useful to fix schematic errors
Fixes https://gitlab.com/kicad/code/kicad/issues/13138
This iterated over all pins to find the pin after a given item. Because
out pattern is consistently to iterate in the outer loop, this means
that we were an O(n^2) loop for the pins just to find their names. This
affected very large parts (e.g. FPGAs) when switching sheets to display
Seth Hillbrand
Jeff Young
Mark Roszko
Tomasz Wlostowski
jean-pierre charras
Wayne Stambaugh
JamesJCode
Fabien Corona
Roberto Fernandez Bautista
Jon Evans