b85ed89ea5
Corrected a few pads layer settings in 'sonde xilinx' demo.
2015-04-16 09:33:33 +02:00
ff154dba3c
demos/ schematic tidying
2015-03-28 13:24:13 +01:00
fe919cd456
Update demos. Fix pspice netlist issues when using ( and ) in net names ( parenthesis are replaced by underscore) .
2014-01-07 20:42:34 +01:00
8ccf0320b4
1) Add "rules" to base of tree for copying into BZR_HOME/rules.
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File "rules" has instructional text as comments near top.
2) Convert all text files in repo to LF line ending form.
Any checkout done with "rules" in play will convert the working
tree to native line ending, while keeping repo as LF line ending.
2013-05-25 23:36:44 -05:00
8d22086097
AUTHORS.txt: add some contributor names (I certainly forgot some other contributors, and I apologize).
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Demos: convert .brd files to .kicad_pcb files and fix 2 broken files
2013-01-14 13:16:23 +01:00
a180518f4b
Some demo files updated.
2011-12-18 10:06:22 +01:00
fde4243954
Fixes
2011-03-07 21:20:37 +01:00
0cb6cd8c02
Eeschema: in intermediate netlist generation: remove redundant pins list by component, and make Dick happy.
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Known bug in intermediate netlist generation: multi parts per package have their common pins listed more than once in nets section. Will be fixed.
2011-02-10 09:27:36 +01:00
4574d4369e
fixed bug 585140 and minor cleaning
2010-05-27 12:23:29 +02:00
792eb943b5
fixed bug 583939
2010-05-23 19:39:47 +02:00
dedb0228dc
add files not currently available in source (e.g. docs, modules, etc.)
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set svn:eol-style property to native for all ascii files to support cross platform development
2007-06-05 12:10:51 +00:00
Maciej Suminski
jean-pierre charras
Dick Hollenbeck
jp
raburton