{
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      "drc_exclusions": [],
      "rules": {
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      "via_dimensions": []
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  "cvpcb": {
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      "bus_label_syntax": "error",
      "bus_to_bus_conflict": "error",
      "bus_to_net_conflict": "error",
      "different_unit_footprint": "error",
      "different_unit_net": "error",
      "duplicate_sheet_names": "error",
      "global_label_dangling": "warning",
      "hier_label_mismatch": "error",
      "label_dangling": "error",
      "lib_symbol_issues": "warning",
      "multiple_net_names": "warning",
      "net_not_bus_member": "warning",
      "no_connect_connected": "warning",
      "no_connect_dangling": "warning",
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      "pin_not_driven": "error",
      "pin_to_pin": "warning",
      "power_pin_not_driven": "error",
      "similar_labels": "warning",
      "unresolved_variable": "error",
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        "microvia_diameter": 0.3,
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        "pcb_color": "rgba(0, 0, 0, 0.000)",
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      "idf": "",
      "netlist": "",
      "specctra_dsn": "",
      "step": "",
      "vrml": ""
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      "default_junction_size": 40.0,
      "default_line_thickness": 6.0,
      "default_text_size": 50.0,
      "default_wire_thickness": 6.0,
      "field_names": [],
      "intersheets_ref_prefix": "",
      "intersheets_ref_short": false,
      "intersheets_ref_show": false,
      "intersheets_ref_suffix": "",
      "junction_size_choice": 3,
      "pin_symbol_size": 25.0,
      "text_offset_ratio": 0.3
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    "legacy_lib_list": [],
    "meta": {
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    },
    "net_format_name": "",
    "page_layout_descr_file": "",
    "plot_directory": "",
    "spice_adjust_passive_values": false,
    "spice_external_command": "spice \"%I\"",
    "subpart_first_id": 65,
    "subpart_id_separator": 0
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  "sheets": [
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  "text_variables": {}
}