(kicad_pcb (version 20210424) (generator pcbnew)

  (general
    (thickness 1.6)
  )

  (paper "A4")
  (title_block
    (title "Actionneur_piezo")
    (company "Kicad devs")
    (comment 1 "Demo")
  )

  (layers
    (0 "F.Cu" power "top_copper")
    (31 "B.Cu" signal "bottom_copper")
    (32 "B.Adhes" user "B.Adhesive")
    (33 "F.Adhes" user "F.Adhesive")
    (34 "B.Paste" user)
    (35 "F.Paste" user)
    (36 "B.SilkS" user "B.Silkscreen")
    (37 "F.SilkS" user "F.Silkscreen")
    (38 "B.Mask" user)
    (39 "F.Mask" user)
    (40 "Dwgs.User" user "User.Drawings")
    (41 "Cmts.User" user "User.Comments")
    (42 "Eco1.User" user "User.Eco1")
    (43 "Eco2.User" user "User.Eco2")
    (44 "Edge.Cuts" user)
    (45 "Margin" user)
    (46 "B.CrtYd" user "B.Courtyard")
    (47 "F.CrtYd" user "F.Courtyard")
    (48 "B.Fab" user)
    (49 "F.Fab" user)
  )

  (setup
    (stackup
      (layer "F.SilkS" (type "Top Silk Screen") (color "White"))
      (layer "F.Paste" (type "Top Solder Paste"))
      (layer "F.Mask" (type "Top Solder Mask") (color "Green") (thickness 0.01))
      (layer "F.Cu" (type "copper") (thickness 0.035))
      (layer "dielectric 1" (type "core") (thickness 1.51) (material "FR4") (epsilon_r 4.5) (loss_tangent 0.02))
      (layer "B.Cu" (type "copper") (thickness 0.035))
      (layer "B.Mask" (type "Bottom Solder Mask") (color "Green") (thickness 0.01))
      (layer "B.Paste" (type "Bottom Solder Paste"))
      (layer "B.SilkS" (type "Bottom Silk Screen") (color "White"))
      (copper_finish "None")
      (dielectric_constraints no)
    )
    (pad_to_mask_clearance 0)
    (aux_axis_origin 83.5 138)
    (pcbplotparams
      (layerselection 0x00000fc_80000001)
      (disableapertmacros false)
      (usegerberextensions false)
      (usegerberattributes true)
      (usegerberadvancedattributes false)
      (creategerberjobfile false)
      (svguseinch false)
      (svgprecision 6)
      (excludeedgelayer false)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin true)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15.000000)
      (dxfpolygonmode true)
      (dxfimperialunits true)
      (dxfusepcbnewfont true)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (sketchpadsonfab false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 0)
      (scaleselection 1)
      (outputdirectory "")
    )
  )

  (net 0 "")
  (net 1 "-VAA")
  (net 2 "/12Vext")
  (net 3 "/ampli_ht_horizontal/PIEZO_IN")
  (net 4 "/ampli_ht_horizontal/PIEZO_OUT")
  (net 5 "/ampli_ht_horizontal/S_OUT+")
  (net 6 "/ampli_ht_horizontal/Vpil_0_3,3V")
  (net 7 "/ampli_ht_vertical/PIEZO_IN")
  (net 8 "/ampli_ht_vertical/PIEZO_OUT")
  (net 9 "/ampli_ht_vertical/S_OUT+")
  (net 10 "/ampli_ht_vertical/Vpil_0_3,3V")
  (net 11 "GND")
  (net 12 "HT")
  (net 13 "Net-(C10-Pad1)")
  (net 14 "Net-(C10-Pad2)")
  (net 15 "Net-(C12-Pad1)")
  (net 16 "Net-(C14-Pad1)")
  (net 17 "Net-(C3-Pad2)")
  (net 18 "Net-(C4-Pad1)")
  (net 19 "Net-(C5-Pad1)")
  (net 20 "Net-(C6-Pad2)")
  (net 21 "Net-(C7-Pad1)")
  (net 22 "Net-(C8-Pad1)")
  (net 23 "Net-(D4-Pad1)")
  (net 24 "Net-(D4-Pad2)")
  (net 25 "Net-(D7-Pad1)")
  (net 26 "Net-(D7-Pad2)")
  (net 27 "Net-(R11-Pad1)")
  (net 28 "Net-(R19-Pad2)")
  (net 29 "Net-(R21-Pad1)")
  (net 30 "Net-(R9-Pad2)")
  (net 31 "Net-(RV1-Pad2)")
  (net 32 "Net-(RV2-Pad2)")
  (net 33 "VCC")
  (net 34 "Net-(D2-Pad1)")
  (net 35 "Net-(D3-Pad1)")
  (net 36 "Net-(D5-Pad1)")
  (net 37 "Net-(D6-Pad1)")
  (net 38 "Net-(D8-Pad2)")
  (net 39 "Net-(D9-Pad2)")
  (net 40 "+12V")
  (net 41 "Net-(Q1-Pad1)")
  (net 42 "Net-(Q2-Pad1)")
  (net 43 "Net-(Q3-Pad1)")
  (net 44 "Net-(Q4-Pad1)")
  (net 45 "Net-(Q4-Pad2)")
  (net 46 "Net-(Q5-Pad1)")
  (net 47 "Net-(Q6-Pad1)")
  (net 48 "Net-(Q7-Pad1)")
  (net 49 "Net-(Q8-Pad1)")
  (net 50 "Net-(Q8-Pad2)")
  (net 51 "unconnected-(U1-Pad6)")
  (net 52 "unconnected-(U1-Pad7)")

  (footprint "Capacitor_THT:CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal" (layer "F.Cu")
    (tedit 5AE50EF2) (tstamp 00000000-0000-0000-0000-00005592cf15)
    (at 126.619 60.706)
    (descr "CP, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=10*4.5mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf")
    (tags "CP Axial series Axial Horizontal pin pitch 15mm  length 10mm diameter 4.5mm Electrolytic Capacitor")
    (property "Sheetfile" "complex_hierarchy.kicad_sch")
    (property "Sheetname" "")
    (path "/00000000-0000-0000-0000-00004ae173cf")
    (attr through_hole)
    (fp_text reference "C2" (at 7.5 -3.37) (layer "F.SilkS")
      (effects (font (size 1 1) (thickness 0.15)))
      (tstamp 418bad6f-611a-41ee-b864-dcde626e8023)
    )
    (fp_text value "47uF/20V" (at 7.5 3.37) (layer "F.Fab")
      (effects (font (size 1 1) (thickness 0.15)))
      (tstamp dafb1786-c415-4ffe-a8c4-7c471877c633)
    )
    (fp_text user "${REFERENCE}" (at 7.5 0) (layer "F.Fab")
      (effects (font (size 1 1) (thickness 0.15)))
      (tstamp 945489ab-e656-4fd2-a1a0-d64bd9dd463f)
    )
    (fp_line (start 4.63 1.62) (end 5.38 2.37) (layer "F.SilkS") (width 0.12) (tstamp 693e8a29-f7e4-49be-bc4b-d95bb2e37757))
    (fp_line (start 1.24 0) (end 2.38 0) (layer "F.SilkS") (width 0.12) (tstamp 77c66cb0-3007-4510-aef9-e1975743a3ce))
    (fp_line (start 13.76 0) (end 12.62 0) (layer "F.SilkS") (width 0.12) (tstamp 780696f6-1af4-40c6-96d8-a9d89e0a1271))
    (fp_line (start 2.38 -2.37) (end 3.88 -2.37) (layer "F.SilkS") (width 0.12) (tstamp 941b8231-4821-44a2-a94f-e3d8bdbab511))
    (fp_line (start 3.88 -2.37) (end 4.63 -1.62) (layer "F.SilkS") (width 0.12) (tstamp 945c41ca-c877-4f81-9e69-e2717f5bb015))
    (fp_line (start 1.38 -2.95) (end 1.38 -1.45) (layer "F.SilkS") (width 0.12) (tstamp 9f1af9f8-9eb7-4a4b-9bf1-3a141244ff71))
    (fp_line (start 5.38 2.37) (end 12.62 2.37) (layer "F.SilkS") (width 0.12) (tstamp a5408007-d403-4513-a87c-d592aa9dc61b))
    (fp_line (start 0.63 -2.2) (end 2.13 -2.2) (layer "F.SilkS") (width 0.12) (tstamp b556c9a7-f7ff-4b4a-a159-81d8772e7178))
    (fp_line (start 2.38 2.37) (end 3.88 2.37) (layer "F.SilkS") (width 0.12) (tstamp cbe364c8-97ff-4c5d-93bb-8f6cbfe496ab))
    (fp_line (start 5.38 -2.37) (end 12.62 -2.37) (layer "F.SilkS") (width 0.12) (tstamp dd7da961-77e6-410e-be65-79173960a61a))
    (fp_line (start 3.88 2.37) (end 4.63 1.62) (layer "F.SilkS") (width 0.12) (tstamp dee401e2-6b54-4a2f-88ec-16623bea4e63))
    (fp_line (start 4.63 -1.62) (end 5.38 -2.37) (layer "F.SilkS") (width 0.12) (tstamp e645d31b-9f87-48ea-be59-f4c00f6df138))
    (fp_line (start 12.62 -2.37) (end 12.62 2.37) (layer "F.SilkS") (width 0.12) (tstamp ebe86282-eed9-4337-bb11-26a6208f6b32))
    (fp_line (start 2.38 -2.37) (end 2.38 2.37) (layer "F.SilkS") (width 0.12) (tstamp f4f7ad0c-6807-4d4d-9592-fd3b40dff6ca))
    (fp_line (start 16.25 -2.5) (end -1.25 -2.5) (layer "F.CrtYd") (width 0.05) (tstamp 3898ed30-a6a5-4864-9263-a3d27c75f763))
    (fp_line (start -1.25 -2.5) (end -1.25 2.5) (layer "F.CrtYd") (width 0.05) (tstamp 4b764917-cd4a-4ca7-9d03-8f1f04a3a4a1))
    (fp_line (start -1.25 2.5) (end 16.25 2.5) (layer "F.CrtYd") (width 0.05) (tstamp a72e0960-68d8-4e50-888f-257b729dae18))
    (fp_line (start 16.25 2.5) (end 16.25 -2.5) (layer "F.CrtYd") (width 0.05) (tstamp d072449b-885b-4e0a-9150-3a89be26f528))
    (fp_line (start 4.63 -1.5) (end 5.38 -2.25) (layer "F.Fab") (width 0.1) (tstamp 085f303d-c28e-455d-92a6-82c2ee21f0de))
    (fp_line (start 4.63 1.5) (end 5.38 2.25) (layer "F.Fab") (width 0.1) (tstamp 0fe211b1-9d75-42a8-a338-e544402b82f9))
    (fp_line (start 3.88 2.25) (end 4.63 1.5) (layer "F.Fab") (width 0.1) (tstamp 2a0b2a66-1502-4a3f-bce2-2ee26f30d5a6))
    (fp_line (start 2.5 -2.25) (end 3.88 -2.25) (layer "F.Fab") (width 0.1) (tstamp 2aa29f95-f6de-4218-a667-3ad18b2e0f04))
    (fp_line (start 2.5 2.25) (end 3.88 2.25) (layer "F.Fab") (width 0.1) (tstamp 502ac720-75e0-4623-90c7-39ff6c338469))
    (fp_line (start 15 0) (end 12.5 0) (layer "F.Fab") (width 0.1) (tstamp 79ea4f3b-6b97-43ba-8f5c-ca88155cb96e))
    (fp_line (start 12.5 -2.25) (end 12.5 2.25) (layer "F.Fab") (width 0.1) (tstamp 82c2f000-d1b2-4815-9af2-611465285b50))
    (fp_line (start 5.38 -2.25) (end 12.5 -2.25) (layer "F.Fab") (width 0.1) (tstamp 88209ea0-5c89-435a-942b-dd16b828df88))
    (fp_line (start 2.5 -2.25) (end 2.5 2.25) (layer "F.Fab") (width 0.1) (tstamp 8c000a01-dae0-473f-a222-a2cb3a32620e))
    (fp_line (start 3.88 -2.25) (end 4.63 -1.5) (layer "F.Fab") (width 0.1) (tstamp 9ab3f3c8-07a1-4292-a59f-2d11d2b1fbd0))
    (fp_line (start 4.65 -0.75) (end 4.65 0.75) (layer "F.Fab") (width 0.1) (tstamp ab773a3e-e3f6-42f6-b7ca-c331a4ec7bdb))
    (fp_line (start 0 0) (end 2.5 0) (layer "F.Fab") (width 0.1) (tstamp cf9acd60-f7dc-427a-91f3-73abc94a14bf))
    (fp_line (start 5.38 2.25) (end 12.5 2.25) (layer "F.Fab") (width 0.1) (tstamp defa4e8c-5675-4b67-ac34-48c177a96048))
    (fp_line (start 3.9 0) (end 5.4 0) (layer "F.Fab") (width 0.1) (tstamp f22cd9c5-9b0a-4b3c-b94c-d7f372d65f68))
    (pad "1" thru_hole rect locked (at 0 0) (size 2 2) (drill 1) (layers *.Cu *.Mask)
      (net 40 "+12V") (pintype "passive") (tstamp 87b15f05-cfc2-47e8-afe0-328539c951d0))
    (pad "2" thru_hole oval locked (at 15 0) (size 2 2) (drill 1) (layers *.Cu *.Mask)
      (net 11 "GND") (pintype "passive") (tstamp d910ec16-88ba-4f14-8fac-e1629e5b1805))
    (model "${KICAD6_3DMODEL_DIR}/Capacitor_THT.3dshapes/CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal.wrl"
      (offset (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

  (footprint "Capacitor_THT:CP_Axial_L11.0mm_D6.0mm_P18.00mm_Horizontal" (layer "F.Cu")
    (tedit 5AE50EF2) (tstamp 00000000-0000-0000-0000-00005592cf60)
    (at 121.793 60.579 180)
    (descr "CP, Axial series, Axial, Horizontal, pin pitch=18mm, , length*diameter=11*6mm^2, Electrolytic Capacitor")
    (tags "CP Axial series Axial Horizontal pin pitch 18mm  length 11mm diameter 6mm Electrolytic Capacitor")
    (property "Sheetfile" "complex_hierarchy.kicad_sch")
    (property "Sheetname" "")
    (path "/00000000-0000-0000-0000-00004b3a1558")
    (attr through_hole)
    (fp_text reference "C9" (at 9 -4.12) (layer "F.SilkS")
      (effects (font (size 1 1) (thickness 0.15)))
      (tstamp 62cf5fa8-a4b4-46ab-858e-45d88fe7089b)
    )
    (fp_text value "47uF/63V" (at 9 4.12) (layer "F.Fab")
      (effects (font (size 1 1) (thickness 0.15)))
      (tstamp 295c0c8c-f24d-45ea-9f06-30afef2c240e)
    )
    (fp_text user "${REFERENCE}" (at 9 0) (layer "F.Fab")
      (effects (font (size 1 1) (thickness 0.15)))
      (tstamp b9092744-4072-423a-a26f-1580a9a32c45)
    )
    (fp_line (start 14.62 -3.12) (end 14.62 3.12) (layer "F.SilkS") (width 0.12) (tstamp 02796805-8dcb-4d2b-a382-b25d559832b3))
    (fp_line (start 6.98 3.12) (end 14.62 3.12) (layer "F.SilkS") (width 0.12) (tstamp 1b2514cf-b8ba-449d-b011-5f3da9e3b8da))
    (fp_line (start 1.44 0) (end 3.38 0) (layer "F.SilkS") (width 0.12) (tstamp 22e780f6-886e-40fc-92ae-4712cf640cd2))
    (fp_line (start 3.38 3.12) (end 5.18 3.12) (layer "F.SilkS") (width 0.12) (tstamp 42ed3a13-7560-4942-8090-efb2b60dc53f))
    (fp_line (start 5.18 3.12) (end 6.08 2.22) (layer "F.SilkS") (width 0.12) (tstamp 7607eeb6-e204-4c90-bb0b-e08bd0dd7014))
    (fp_line (start 1.28 -2.6) (end 3.08 -2.6) (layer "F.SilkS") (width 0.12) (tstamp 85f8eb62-19d6-4097-82aa-6ac841d70cc1))
    (fp_line (start 2.18 -3.5) (end 2.18 -1.7) (layer "F.SilkS") (width 0.12) (tstamp 8bebf5c9-a9be-4e00-b515-ffad8c6fbd01))
    (fp_line (start 3.38 -3.12) (end 5.18 -3.12) (layer "F.SilkS") (width 0.12) (tstamp 963d86db-208e-4927-95dd-6d89997d1163))
    (fp_line (start 16.56 0) (end 14.62 0) (layer "F.SilkS") (width 0.12) (tstamp 9ce1352a-00ed-4aa5-8cb7-cd8fd65c5944))
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    (pad "1" thru_hole rect locked (at 0 0 180) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
      (net 12 "HT") (pintype "passive") (tstamp 3d7106fe-350c-4ade-b801-a3ae92fc8a0e))
    (pad "2" thru_hole oval locked (at 18 0 180) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
      (net 11 "GND") (pintype "passive") (tstamp 783c790e-9491-4066-a41f-d913ce8508d8))
    (model "${KICAD6_3DMODEL_DIR}/Capacitor_THT.3dshapes/CP_Axial_L11.0mm_D6.0mm_P18.00mm_Horizontal.wrl"
      (offset (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

  (footprint "Capacitor_THT:CP_Axial_L10.0mm_D4.5mm_P15.00mm_Horizontal" (layer "F.Cu")
    (tedit 5AE50EF2) (tstamp 00000000-0000-0000-0000-00005592cf70)
    (at 139.7 77.216)
    (descr "CP, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=10*4.5mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf")
    (tags "CP Axial series Axial Horizontal pin pitch 15mm  length 10mm diameter 4.5mm Electrolytic Capacitor")
    (property "Sheetfile" "complex_hierarchy.kicad_sch")
    (property "Sheetname" "")
    (path "/00000000-0000-0000-0000-00004b4b15e7")
    (attr through_hole)
    (fp_text reference "C10" (at 2.54 -3.556) (layer "F.SilkS")
      (effects (font (size 1 1) (thickness 0.15)))
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