34 lines
1.1 KiB
Plaintext
34 lines
1.1 KiB
Plaintext
* another state machine example
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* by Holger Vogt, July 9th, 2020
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* 3-bit counter in a subcircuit with 5 V analog in and out
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*** counter
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.subckt 3bcounter clock updown out_b0 out_b1 out_b2
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* Define a simple 3 bit up/down counter that counts clk edges.
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* Digital outputs are on b2 b1 b0.
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* inputs clock reset outputs (all digital)
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a0 [upd] clk n_zero [b2 b1 b0] state2
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* This needs to be edited: enter the absolute path of file state-3bit-count.in
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.model state2 d_state(state_file = "D:\Spice_general\KiCad-799\up-down-counter\state-3bit-count.in")
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*.model state2 d_state(state_file = "state-3bit-count.in")
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* Digital "one" and "zero"
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a1 n_one pullup1
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.model pullup1 d_pullup(load = 1pF)
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a2 n_zero pulldown1
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.model pulldown1 d_pulldown(load = 1pF)
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* Convert the digital outputs to analog
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a3 [b2] [out_b2] dac1
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a4 [b1] [out_b1] dac1
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a5 [b0] [out_b0] dac1
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.model dac1 dac_bridge(out_low = 0 out_high = 5 out_undef = 2.5)
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* Convert the analog inputs to digital
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a6 [clock] [clk] adc1
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a7 [updown] [upd] adc1
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.model adc1 adc_bridge(in_low = 0.3 in_high = 3.5)
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.ends
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*** end counter
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