334 lines
12 KiB
C++
334 lines
12 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2004-2022 KiCad Developers.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <common.h>
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#include <board_design_settings.h>
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#include <footprint.h>
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#include <pad.h>
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#include <pcb_track.h>
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#include <geometry/shape_segment.h>
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#include <geometry/shape_circle.h>
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#include <drc/drc_engine.h>
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#include <drc/drc_item.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_test_provider_clearance_base.h>
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#include "drc_rtree.h"
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/*
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Holes clearance test. Checks pad and via holes for their mechanical clearances.
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Generated errors:
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- DRCE_DRILLED_HOLES_TOO_CLOSE
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- DRCE_DRILLED_HOLES_COLOCATED
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*/
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class DRC_TEST_PROVIDER_HOLE_TO_HOLE : public DRC_TEST_PROVIDER_CLEARANCE_BASE
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{
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public:
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DRC_TEST_PROVIDER_HOLE_TO_HOLE () :
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DRC_TEST_PROVIDER_CLEARANCE_BASE(),
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m_board( nullptr ),
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m_largestHoleToHoleClearance( 0 )
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{
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}
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virtual ~DRC_TEST_PROVIDER_HOLE_TO_HOLE()
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{
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}
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virtual bool Run() override;
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virtual const wxString GetName() const override
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{
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return wxT( "hole_to_hole_clearance" );
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};
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virtual const wxString GetDescription() const override
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{
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return wxT( "Tests hole to hole spacing" );
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}
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private:
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bool testHoleAgainstHole( BOARD_ITEM* aItem, SHAPE_CIRCLE* aHole, BOARD_ITEM* aOther );
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BOARD* m_board;
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DRC_RTREE m_holeTree;
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int m_largestHoleToHoleClearance;
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};
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static std::shared_ptr<SHAPE_CIRCLE> getHoleShape( BOARD_ITEM* aItem )
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{
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if( aItem->Type() == PCB_VIA_T )
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{
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PCB_VIA* via = static_cast<PCB_VIA*>( aItem );
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return std::make_shared<SHAPE_CIRCLE>( via->GetCenter(), via->GetDrillValue() / 2 );
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}
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else if( aItem->Type() == PCB_PAD_T )
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{
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PAD* pad = static_cast<PAD*>( aItem );
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return std::make_shared<SHAPE_CIRCLE>( pad->GetPosition(), pad->GetDrillSize().x / 2 );
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}
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return std::make_shared<SHAPE_CIRCLE>( VECTOR2I( 0, 0 ), 0 );
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}
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bool DRC_TEST_PROVIDER_HOLE_TO_HOLE::Run()
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{
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if( m_drcEngine->IsErrorLimitExceeded( DRCE_DRILLED_HOLES_TOO_CLOSE )
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&& m_drcEngine->IsErrorLimitExceeded( DRCE_DRILLED_HOLES_COLOCATED ) )
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{
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reportAux( wxT( "Hole to hole violations ignored. Tests not run." ) );
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return true; // continue with other tests
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}
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m_board = m_drcEngine->GetBoard();
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DRC_CONSTRAINT worstClearanceConstraint;
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if( m_drcEngine->QueryWorstConstraint( HOLE_TO_HOLE_CONSTRAINT, worstClearanceConstraint ) )
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{
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m_largestHoleToHoleClearance = worstClearanceConstraint.GetValue().Min();
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reportAux( wxT( "Worst hole to hole : %d nm" ), m_largestHoleToHoleClearance );
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}
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else
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{
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reportAux( wxT( "No hole to hole constraints found. Skipping check." ) );
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return true; // continue with other tests
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}
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if( !reportPhase( _( "Checking hole to hole clearances..." ) ) )
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return false; // DRC cancelled
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const size_t progressDelta = 200;
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size_t count = 0;
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size_t ii = 0;
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m_holeTree.clear();
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forEachGeometryItem( { PCB_PAD_T, PCB_VIA_T }, LSET::AllLayersMask(),
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[&]( BOARD_ITEM* item ) -> bool
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{
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++count;
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return true;
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} );
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count *= 2; // One for adding to the rtree; one for checking
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forEachGeometryItem( { PCB_PAD_T, PCB_VIA_T }, LSET::AllLayersMask(),
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[&]( BOARD_ITEM* item ) -> bool
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{
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if( !reportProgress( ii++, count, progressDelta ) )
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return false;
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if( item->Type() == PCB_PAD_T )
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{
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PAD* pad = static_cast<PAD*>( item );
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// Slots are generally milled _after_ drilling, so we ignore them.
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if( pad->GetDrillSize().x && pad->GetDrillSize().x == pad->GetDrillSize().y )
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m_holeTree.Insert( item, Edge_Cuts, m_largestHoleToHoleClearance );
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}
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else if( item->Type() == PCB_VIA_T )
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{
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// Blind/buried/microvias will be drilled/burned _prior_ to lamination, so
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// subsequently drilled holes need to avoid them.
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m_holeTree.Insert( item, Edge_Cuts, m_largestHoleToHoleClearance );
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}
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return true;
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} );
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std::unordered_map<PTR_PTR_CACHE_KEY, int> checkedPairs;
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for( PCB_TRACK* track : m_board->Tracks() )
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{
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if( track->Type() != PCB_VIA_T )
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continue;
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PCB_VIA* via = static_cast<PCB_VIA*>( track );
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if( !reportProgress( ii++, count, progressDelta ) )
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return false; // DRC cancelled
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// We only care about mechanically drilled (ie: non-laser) holes. These include both
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// blind/buried via holes (drilled prior to lamination) and through-via and drilled pad
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// holes (which are generally drilled post laminataion).
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if( via->GetViaType() != VIATYPE::MICROVIA )
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{
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std::shared_ptr<SHAPE_CIRCLE> holeShape = getHoleShape( via );
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m_holeTree.QueryColliding( via, Edge_Cuts, Edge_Cuts,
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// Filter:
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[&]( BOARD_ITEM* other ) -> bool
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{
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BOARD_ITEM* a = via;
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BOARD_ITEM* b = other;
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// store canonical order so we don't collide in both directions
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// (a:b and b:a)
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if( static_cast<void*>( a ) > static_cast<void*>( b ) )
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std::swap( a, b );
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if( checkedPairs.find( { a, b } ) != checkedPairs.end() )
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{
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return false;
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}
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else
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{
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checkedPairs[ { a, b } ] = 1;
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return true;
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}
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},
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// Visitor:
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[&]( BOARD_ITEM* other ) -> bool
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{
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return testHoleAgainstHole( via, holeShape.get(), other );
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},
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m_largestHoleToHoleClearance );
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}
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}
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checkedPairs.clear();
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for( FOOTPRINT* footprint : m_board->Footprints() )
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{
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for( PAD* pad : footprint->Pads() )
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{
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if( !reportProgress( ii++, count, progressDelta ) )
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return false; // DRC cancelled
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// We only care about drilled (ie: round) pad holes
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if( pad->HasDrilledHole() )
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{
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std::shared_ptr<SHAPE_CIRCLE> holeShape = getHoleShape( pad );
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m_holeTree.QueryColliding( pad, Edge_Cuts, Edge_Cuts,
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// Filter:
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[&]( BOARD_ITEM* other ) -> bool
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{
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BOARD_ITEM* a = pad;
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BOARD_ITEM* b = other;
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// store canonical order so we don't collide in both directions
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// (a:b and b:a)
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if( static_cast<void*>( a ) > static_cast<void*>( b ) )
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std::swap( a, b );
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if( checkedPairs.find( { a, b } ) != checkedPairs.end() )
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{
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return false;
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}
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else
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{
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checkedPairs[ { a, b } ] = 1;
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return true;
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}
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},
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// Visitor:
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[&]( BOARD_ITEM* other ) -> bool
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{
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return testHoleAgainstHole( pad, holeShape.get(), other );
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},
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m_largestHoleToHoleClearance );
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}
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}
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if( m_drcEngine->IsCancelled() )
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return false;
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}
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reportRuleStatistics();
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return !m_drcEngine->IsCancelled();
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}
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bool DRC_TEST_PROVIDER_HOLE_TO_HOLE::testHoleAgainstHole( BOARD_ITEM* aItem, SHAPE_CIRCLE* aHole,
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BOARD_ITEM* aOther )
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{
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bool reportCoLocation = !m_drcEngine->IsErrorLimitExceeded( DRCE_DRILLED_HOLES_COLOCATED );
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bool reportHole2Hole = !m_drcEngine->IsErrorLimitExceeded( DRCE_DRILLED_HOLES_TOO_CLOSE );
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if( !reportCoLocation && !reportHole2Hole )
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return false;
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std::shared_ptr<SHAPE_CIRCLE> otherHole = getHoleShape( aOther );
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int epsilon = m_board->GetDesignSettings().GetDRCEpsilon();
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SEG::ecoord epsilon_sq = SEG::Square( epsilon );
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// Blind-buried vias are drilled prior to stackup; they're only an issue if they share layers
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if( aItem->Type() == PCB_VIA_T && aOther->Type() == PCB_VIA_T )
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{
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LSET viaHoleLayers = static_cast<PCB_VIA*>( aItem )->GetLayerSet() & LSET::AllCuMask();
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if( ( viaHoleLayers & static_cast<PCB_VIA*>( aOther )->GetLayerSet() ).none() )
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return false;
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}
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// Holes at same location generate a separate violation
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if( ( aHole->GetCenter() - otherHole->GetCenter() ).SquaredEuclideanNorm() < epsilon_sq )
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{
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if( reportCoLocation )
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{
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std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_DRILLED_HOLES_COLOCATED );
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drce->SetItems( aItem, aOther );
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reportViolation( drce, aHole->GetCenter(), UNDEFINED_LAYER );
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}
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}
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else if( reportHole2Hole )
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{
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int actual = ( aHole->GetCenter() - otherHole->GetCenter() ).EuclideanNorm();
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actual = std::max( 0, actual - aHole->GetRadius() - otherHole->GetRadius() );
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auto constraint = m_drcEngine->EvalRules( HOLE_TO_HOLE_CONSTRAINT, aItem, aOther,
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UNDEFINED_LAYER /* holes pierce all layers */ );
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int minClearance = std::max( 0, constraint.GetValue().Min() - epsilon );
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if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE
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&& minClearance >= 0
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&& actual < minClearance )
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{
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std::shared_ptr<DRC_ITEM> drce = DRC_ITEM::Create( DRCE_DRILLED_HOLES_TOO_CLOSE );
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wxString msg = formatMsg( _( "(%s min %s; actual %s)" ),
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constraint.GetName(),
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minClearance,
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actual );
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drce->SetErrorMessage( drce->GetErrorText() + wxS( " " ) + msg );
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drce->SetItems( aItem, aOther );
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drce->SetViolatingRule( constraint.GetParentRule() );
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reportViolation( drce, aHole->GetCenter(), UNDEFINED_LAYER );
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}
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}
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return !m_drcEngine->IsCancelled();
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}
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namespace detail
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{
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static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_HOLE_TO_HOLE> dummy;
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}
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