1537 lines
42 KiB
C++
1537 lines
42 KiB
C++
/*
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* KiRouter - a push-and-(sometimes-)shove PCB router
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*
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* Copyright (C) 2013-2016 CERN
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* Copyright (C) 2016-2020 KiCad Developers, see AUTHORS.txt for contributors.
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* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
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*
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* This program is free software: you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 3 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <board.h>
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#include <board_connected_item.h>
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#include <fp_text.h>
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#include <footprint.h>
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#include <track.h>
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#include <zone.h>
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#include <pcb_shape.h>
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#include <pcb_text.h>
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#include <board_commit.h>
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#include <layers_id_colors_and_visibility.h>
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#include <geometry/convex_hull.h>
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#include <confirm.h>
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#include <view/view.h>
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#include <view/view_item.h>
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#include <view/view_group.h>
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#include <pcb_painter.h>
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#include <geometry/shape.h>
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#include <geometry/shape_line_chain.h>
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#include <geometry/shape_arc.h>
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#include <geometry/shape_simple.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_engine.h>
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#include <memory>
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#include <advanced_config.h>
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#include "tools/pcb_tool_base.h"
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#include "pns_kicad_iface.h"
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#include "pns_arc.h"
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#include "pns_routing_settings.h"
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#include "pns_sizes_settings.h"
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#include "pns_item.h"
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#include "pns_solid.h"
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#include "pns_segment.h"
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#include "pns_node.h"
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#include "pns_router.h"
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#include "pns_debug_decorator.h"
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#include "router_preview_item.h"
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typedef VECTOR2I::extended_type ecoord;
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class PNS_PCBNEW_RULE_RESOLVER : public PNS::RULE_RESOLVER
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{
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public:
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PNS_PCBNEW_RULE_RESOLVER( BOARD* aBoard, PNS::ROUTER_IFACE* aRouterIface );
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virtual ~PNS_PCBNEW_RULE_RESOLVER();
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virtual bool CollideHoles( const PNS::ITEM* aA, const PNS::ITEM* aB,
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bool aNeedMTV, VECTOR2I* aMTV ) const override;
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virtual int Clearance( const PNS::ITEM* aA, const PNS::ITEM* aB ) override;
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virtual int DpCoupledNet( int aNet ) override;
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virtual int DpNetPolarity( int aNet ) override;
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virtual bool DpNetPair( const PNS::ITEM* aItem, int& aNetP, int& aNetN ) override;
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virtual bool IsDiffPair( const PNS::ITEM* aA, const PNS::ITEM* aB ) override;
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virtual bool QueryConstraint( PNS::CONSTRAINT_TYPE aType, const PNS::ITEM* aItemA, const PNS::ITEM* aItemB, int aLayer, PNS::CONSTRAINT* aConstraint ) override;
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virtual wxString NetName( int aNet ) override;
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private:
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int holeRadius( const PNS::ITEM* aItem ) const;
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int matchDpSuffix( const wxString& aNetName, wxString& aComplementNet, wxString& aBaseDpName );
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private:
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PNS::ROUTER_IFACE* m_routerIface;
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BOARD* m_board;
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TRACK m_dummyTrack;
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ARC m_dummyArc;
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VIA m_dummyVia;
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std::map<std::pair<const PNS::ITEM*, const PNS::ITEM*>, int> m_clearanceCache;
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};
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PNS_PCBNEW_RULE_RESOLVER::PNS_PCBNEW_RULE_RESOLVER( BOARD* aBoard,
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PNS::ROUTER_IFACE* aRouterIface ) :
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m_routerIface( aRouterIface ),
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m_board( aBoard ),
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m_dummyTrack( aBoard ),
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m_dummyArc( aBoard ),
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m_dummyVia( aBoard )
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{
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}
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PNS_PCBNEW_RULE_RESOLVER::~PNS_PCBNEW_RULE_RESOLVER()
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{
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}
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int PNS_PCBNEW_RULE_RESOLVER::holeRadius( const PNS::ITEM* aItem ) const
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{
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if( aItem->Kind() == PNS::ITEM::SOLID_T )
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{
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const PAD* pad = dynamic_cast<const PAD*>( aItem->Parent() );
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if( pad && pad->GetDrillShape() == PAD_DRILL_SHAPE_CIRCLE )
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return pad->GetDrillSize().x / 2;
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}
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else if( aItem->Kind() == PNS::ITEM::VIA_T )
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{
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const ::VIA* via = dynamic_cast<const ::VIA*>( aItem->Parent() );
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if( via )
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return via->GetDrillValue() / 2;
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}
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return 0;
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}
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bool PNS_PCBNEW_RULE_RESOLVER::CollideHoles( const PNS::ITEM* aA, const PNS::ITEM* aB,
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bool aNeedMTV, VECTOR2I* aMTV ) const
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{
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VECTOR2I pos_a = aA->Shape()->Centre();
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VECTOR2I pos_b = aB->Shape()->Centre();
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// Holes with identical locations are allowable
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if( pos_a == pos_b )
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return false;
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int radius_a = holeRadius( aA );
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int radius_b = holeRadius( aB );
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// Do both objects have holes?
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if( radius_a > 0 && radius_b > 0 )
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{
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int holeToHoleMin = m_board->GetDesignSettings().m_HoleToHoleMin;
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ecoord min_dist = holeToHoleMin + radius_a + radius_b;
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ecoord min_dist_sq = min_dist * min_dist;
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const VECTOR2I delta = pos_b - pos_a;
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ecoord dist_sq = delta.SquaredEuclideanNorm();
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if( dist_sq == 0 || dist_sq < min_dist_sq )
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{
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if( aNeedMTV )
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*aMTV = delta.Resize( min_dist - sqrt( dist_sq ) + 3 ); // fixme: apparent rounding error
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return true;
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}
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}
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return false;
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}
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bool PNS_PCBNEW_RULE_RESOLVER::IsDiffPair( const PNS::ITEM* aA, const PNS::ITEM* aB )
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{
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int net_p, net_n;
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if( !DpNetPair( aA, net_p, net_n ) )
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return false;
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if( aA->Net() == net_p && aB->Net() == net_n )
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return true;
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if( aB->Net() == net_p && aA->Net() == net_n )
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return true;
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return false;
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}
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bool PNS_PCBNEW_RULE_RESOLVER::QueryConstraint( PNS::CONSTRAINT_TYPE aType,
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const PNS::ITEM* aItemA, const PNS::ITEM* aItemB,
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int aLayer, PNS::CONSTRAINT* aConstraint )
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{
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std::shared_ptr<DRC_ENGINE> drcEngine = m_board->GetDesignSettings().m_DRCEngine;
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if( !drcEngine )
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return false;
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DRC_CONSTRAINT_TYPE_T hostType;
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switch ( aType )
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{
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case PNS::CONSTRAINT_TYPE::CT_CLEARANCE: hostType = CLEARANCE_CONSTRAINT; break;
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case PNS::CONSTRAINT_TYPE::CT_WIDTH: hostType = TRACK_WIDTH_CONSTRAINT; break;
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case PNS::CONSTRAINT_TYPE::CT_DIFF_PAIR_GAP: hostType = DIFF_PAIR_GAP_CONSTRAINT; break;
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case PNS::CONSTRAINT_TYPE::CT_LENGTH: hostType = LENGTH_CONSTRAINT; break;
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case PNS::CONSTRAINT_TYPE::CT_VIA_DIAMETER: hostType = VIA_DIAMETER_CONSTRAINT; break;
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case PNS::CONSTRAINT_TYPE::CT_VIA_HOLE: hostType = HOLE_SIZE_CONSTRAINT; break;
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default: return false; // should not happen
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}
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BOARD_ITEM* parentA = aItemA ? aItemA->Parent() : nullptr;
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BOARD_ITEM* parentB = aItemB ? aItemB->Parent() : nullptr;
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DRC_CONSTRAINT hostConstraint;
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// A track being routed may not have a BOARD_ITEM associated yet.
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if( aItemA && !parentA )
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{
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switch( aItemA->Kind() )
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{
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case PNS::ITEM::ARC_T: parentA = &m_dummyArc; break;
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case PNS::ITEM::VIA_T: parentA = &m_dummyVia; break;
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case PNS::ITEM::SEGMENT_T: parentA = &m_dummyTrack; break;
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case PNS::ITEM::LINE_T: parentA = &m_dummyTrack; break;
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default: break;
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}
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if( parentA )
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{
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parentA->SetLayer( (PCB_LAYER_ID) aLayer );
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static_cast<BOARD_CONNECTED_ITEM*>( parentA )->SetNetCode( aItemA->Net() );
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}
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}
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if( aItemB && !parentB )
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{
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switch( aItemB->Kind() )
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{
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case PNS::ITEM::ARC_T: parentB = &m_dummyArc; break;
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case PNS::ITEM::VIA_T: parentB = &m_dummyVia; break;
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case PNS::ITEM::SEGMENT_T: parentB = &m_dummyTrack; break;
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case PNS::ITEM::LINE_T: parentB = &m_dummyTrack; break;
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default: break;
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}
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if( parentB )
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{
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parentB->SetLayer( (PCB_LAYER_ID) aLayer );
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static_cast<BOARD_CONNECTED_ITEM*>( parentB )->SetNetCode( aItemB->Net() );
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}
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}
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if( parentA )
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{
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hostConstraint = drcEngine->EvalRulesForItems( hostType, parentA, parentB,
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(PCB_LAYER_ID) aLayer );
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}
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if( hostConstraint.IsNull() )
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return false;
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switch ( aType )
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{
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case PNS::CONSTRAINT_TYPE::CT_CLEARANCE:
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case PNS::CONSTRAINT_TYPE::CT_WIDTH:
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case PNS::CONSTRAINT_TYPE::CT_DIFF_PAIR_GAP:
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case PNS::CONSTRAINT_TYPE::CT_VIA_DIAMETER:
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case PNS::CONSTRAINT_TYPE::CT_VIA_HOLE:
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aConstraint->m_Value = hostConstraint.GetValue();
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aConstraint->m_RuleName = hostConstraint.GetName();
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aConstraint->m_Type = aType;
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return true;
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default:
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return false;
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}
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}
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int PNS_PCBNEW_RULE_RESOLVER::Clearance( const PNS::ITEM* aA, const PNS::ITEM* aB )
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{
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std::pair<const PNS::ITEM*, const PNS::ITEM*> key( aA, aB );
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auto it = m_clearanceCache.find( key );
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if( it != m_clearanceCache.end() )
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return it->second;
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PNS::CONSTRAINT constraint;
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bool ok = false;
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int rv = 0;
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if( aB && IsDiffPair( aA, aB ) )
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{
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// for diff pairs, we use the gap value for shoving/dragging
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if( QueryConstraint( PNS::CONSTRAINT_TYPE::CT_DIFF_PAIR_GAP, aA, aB, aA->Layer(),
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&constraint ) )
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{
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rv = constraint.m_Value.Opt();
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ok = true;
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}
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}
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if( !ok )
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{
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if( QueryConstraint( PNS::CONSTRAINT_TYPE::CT_CLEARANCE, aA, aB, aA->Layer(),
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&constraint ) )
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{
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rv = constraint.m_Value.Min();
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ok = true;
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}
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}
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// still no valid clearance rule? fall back to global minimum.
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if( !ok )
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rv = m_board->GetDesignSettings().m_MinClearance;
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m_clearanceCache[ key ] = rv;
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return rv;
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}
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bool PNS_KICAD_IFACE_BASE::inheritTrackWidth( PNS::ITEM* aItem, int* aInheritedWidth )
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{
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VECTOR2I p;
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assert( aItem->Owner() != NULL );
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switch( aItem->Kind() )
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{
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case PNS::ITEM::VIA_T:
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p = static_cast<PNS::VIA*>( aItem )->Pos();
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break;
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case PNS::ITEM::SOLID_T:
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p = static_cast<PNS::SOLID*>( aItem )->Pos();
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break;
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case PNS::ITEM::SEGMENT_T:
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*aInheritedWidth = static_cast<PNS::SEGMENT*>( aItem )->Width();
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return true;
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default:
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return false;
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}
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PNS::JOINT* jt = static_cast<PNS::NODE*>( aItem->Owner() )->FindJoint( p, aItem );
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assert( jt != NULL );
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int mval = INT_MAX;
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PNS::ITEM_SET linkedSegs = jt->Links();
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linkedSegs.ExcludeItem( aItem ).FilterKinds( PNS::ITEM::SEGMENT_T );
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for( PNS::ITEM* item : linkedSegs.Items() )
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{
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int w = static_cast<PNS::SEGMENT*>( item )->Width();
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mval = std::min( w, mval );
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}
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if( mval == INT_MAX )
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return false;
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*aInheritedWidth = mval;
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return true;
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}
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bool PNS_KICAD_IFACE_BASE::ImportSizes( PNS::SIZES_SETTINGS& aSizes, PNS::ITEM* aStartItem, int aNet )
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{
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BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
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PNS::CONSTRAINT constraint;
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int trackWidth = bds.m_TrackMinWidth;
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bool found = false;
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if( bds.m_UseConnectedTrackWidth && aStartItem != nullptr )
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{
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found = inheritTrackWidth( aStartItem, &trackWidth );
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}
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if( !found && bds.UseNetClassTrack() && aStartItem )
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{
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if( m_ruleResolver->QueryConstraint( PNS::CONSTRAINT_TYPE::CT_WIDTH, aStartItem, nullptr,
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aStartItem->Layer(), &constraint ) )
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{
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trackWidth = constraint.m_Value.Opt();
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found = true; // Note: allowed to override anything, including bds.m_TrackMinWidth
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}
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}
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if( !found )
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{
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trackWidth = bds.GetCurrentTrackWidth();
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}
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aSizes.SetTrackWidth( trackWidth );
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int viaDiameter = bds.m_ViasMinSize;
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int viaDrill = bds.m_MinThroughDrill;
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if( bds.UseNetClassVia() && aStartItem ) // netclass value
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{
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if( m_ruleResolver->QueryConstraint( PNS::CONSTRAINT_TYPE::CT_VIA_DIAMETER, aStartItem,
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nullptr, aStartItem->Layer(), &constraint ) )
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{
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viaDiameter = constraint.m_Value.Opt();
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}
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if( m_ruleResolver->QueryConstraint( PNS::CONSTRAINT_TYPE::CT_VIA_HOLE, aStartItem,
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nullptr, aStartItem->Layer(), &constraint ) )
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{
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viaDrill = constraint.m_Value.Opt();
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}
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}
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else
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{
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viaDiameter = bds.GetCurrentViaSize();
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viaDrill = bds.GetCurrentViaDrill();
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}
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aSizes.SetViaDiameter( viaDiameter );
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aSizes.SetViaDrill( viaDrill );
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int diffPairWidth = bds.m_TrackMinWidth;
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int diffPairGap = bds.m_MinClearance;
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int diffPairViaGap = bds.m_MinClearance;
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if( bds.UseNetClassDiffPair() && aStartItem )
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{
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if( m_ruleResolver->QueryConstraint( PNS::CONSTRAINT_TYPE::CT_WIDTH, aStartItem,
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nullptr, aStartItem->Layer(), &constraint ) )
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{
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diffPairWidth = constraint.m_Value.Opt();
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}
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if( m_ruleResolver->QueryConstraint( PNS::CONSTRAINT_TYPE::CT_DIFF_PAIR_GAP, aStartItem,
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nullptr, aStartItem->Layer(), &constraint ) )
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{
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diffPairGap = constraint.m_Value.Opt();
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diffPairViaGap = constraint.m_Value.Opt();
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}
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}
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else if( bds.UseCustomDiffPairDimensions() )
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{
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diffPairWidth = bds.GetCustomDiffPairWidth();
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diffPairGap = bds.GetCustomDiffPairGap();
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diffPairViaGap = bds.GetCustomDiffPairViaGap();
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}
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//printf( "DPWidth: %d gap %d\n", diffPairWidth, diffPairGap );
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aSizes.SetDiffPairWidth( diffPairWidth );
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aSizes.SetDiffPairGap( diffPairGap );
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aSizes.SetDiffPairViaGap( diffPairViaGap );
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aSizes.ClearLayerPairs();
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return true;
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}
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int PNS_PCBNEW_RULE_RESOLVER::matchDpSuffix( const wxString& aNetName, wxString& aComplementNet,
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wxString& aBaseDpName )
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{
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int rv = 0;
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if( aNetName.EndsWith( "+" ) )
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{
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aComplementNet = "-";
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rv = 1;
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}
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else if( aNetName.EndsWith( "P" ) )
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{
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aComplementNet = "N";
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rv = 1;
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}
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else if( aNetName.EndsWith( "-" ) )
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{
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aComplementNet = "+";
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rv = -1;
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}
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else if( aNetName.EndsWith( "N" ) )
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{
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aComplementNet = "P";
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rv = -1;
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}
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// Match P followed by 2 digits
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else if( aNetName.Right( 2 ).IsNumber() && aNetName.Right( 3 ).Left( 1 ) == "P" )
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{
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aComplementNet = "N" + aNetName.Right( 2 );
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rv = 1;
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}
|
|
// Match P followed by 1 digit
|
|
else if( aNetName.Right( 1 ).IsNumber() && aNetName.Right( 2 ).Left( 1 ) == "P" )
|
|
{
|
|
aComplementNet = "N" + aNetName.Right( 1 );
|
|
rv = 1;
|
|
}
|
|
// Match N followed by 2 digits
|
|
else if( aNetName.Right( 2 ).IsNumber() && aNetName.Right( 3 ).Left( 1 ) == "N" )
|
|
{
|
|
aComplementNet = "P" + aNetName.Right( 2 );
|
|
rv = -1;
|
|
}
|
|
// Match N followed by 1 digit
|
|
else if( aNetName.Right( 1 ).IsNumber() && aNetName.Right( 2 ).Left( 1 ) == "N" )
|
|
{
|
|
aComplementNet = "P" + aNetName.Right( 1 );
|
|
rv = -1;
|
|
}
|
|
if( rv != 0 )
|
|
{
|
|
aBaseDpName = aNetName.Left( aNetName.Length() - aComplementNet.Length() );
|
|
aComplementNet = aBaseDpName + aComplementNet;
|
|
}
|
|
|
|
return rv;
|
|
}
|
|
|
|
|
|
int PNS_PCBNEW_RULE_RESOLVER::DpCoupledNet( int aNet )
|
|
{
|
|
wxString refName = m_board->FindNet( aNet )->GetNetname();
|
|
wxString dummy, coupledNetName;
|
|
|
|
if( matchDpSuffix( refName, coupledNetName, dummy ) )
|
|
{
|
|
NETINFO_ITEM* net = m_board->FindNet( coupledNetName );
|
|
|
|
if( !net )
|
|
return -1;
|
|
|
|
return net->GetNetCode();
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
|
|
wxString PNS_PCBNEW_RULE_RESOLVER::NetName( int aNet )
|
|
{
|
|
return m_board->FindNet( aNet )->GetNetname();
|
|
}
|
|
|
|
|
|
int PNS_PCBNEW_RULE_RESOLVER::DpNetPolarity( int aNet )
|
|
{
|
|
wxString refName = m_board->FindNet( aNet )->GetNetname();
|
|
wxString dummy1, dummy2;
|
|
|
|
return matchDpSuffix( refName, dummy1, dummy2 );
|
|
}
|
|
|
|
|
|
bool PNS_PCBNEW_RULE_RESOLVER::DpNetPair( const PNS::ITEM* aItem, int& aNetP, int& aNetN )
|
|
{
|
|
if( !aItem || !aItem->Parent() || !aItem->Parent()->IsConnected() )
|
|
return false;
|
|
|
|
BOARD_CONNECTED_ITEM* cItem = static_cast<BOARD_CONNECTED_ITEM*>( aItem->Parent() );
|
|
NETINFO_ITEM* netInfo = cItem->GetNet();
|
|
|
|
if( !netInfo )
|
|
return false;
|
|
|
|
wxString netNameP = netInfo->GetNetname();
|
|
wxString netNameN, netNameCoupled, netNameBase;
|
|
|
|
int r = matchDpSuffix( netNameP, netNameCoupled, netNameBase );
|
|
|
|
if( r == 0 )
|
|
{
|
|
return false;
|
|
}
|
|
else if( r == 1 )
|
|
{
|
|
netNameN = netNameCoupled;
|
|
}
|
|
else
|
|
{
|
|
netNameN = netNameP;
|
|
netNameP = netNameCoupled;
|
|
}
|
|
|
|
// wxLogTrace( "PNS","p %s n %s base %s\n", (const char *)netNameP.c_str(), (const char *)netNameN.c_str(), (const char *)netNameBase.c_str() );
|
|
|
|
NETINFO_ITEM* netInfoP = m_board->FindNet( netNameP );
|
|
NETINFO_ITEM* netInfoN = m_board->FindNet( netNameN );
|
|
|
|
//wxLogTrace( "PNS","ip %p in %p\n", netInfoP, netInfoN);
|
|
|
|
if( !netInfoP || !netInfoN )
|
|
return false;
|
|
|
|
aNetP = netInfoP->GetNetCode();
|
|
aNetN = netInfoN->GetNetCode();
|
|
|
|
return true;
|
|
}
|
|
|
|
|
|
class PNS_PCBNEW_DEBUG_DECORATOR: public PNS::DEBUG_DECORATOR
|
|
{
|
|
public:
|
|
PNS_PCBNEW_DEBUG_DECORATOR( KIGFX::VIEW* aView = NULL ) :
|
|
PNS::DEBUG_DECORATOR(),
|
|
m_view( NULL ),
|
|
m_items( NULL )
|
|
{
|
|
SetView( aView );
|
|
}
|
|
|
|
~PNS_PCBNEW_DEBUG_DECORATOR()
|
|
{
|
|
Clear();
|
|
delete m_items;
|
|
}
|
|
|
|
void SetView( KIGFX::VIEW* aView )
|
|
{
|
|
Clear();
|
|
delete m_items;
|
|
m_items = NULL;
|
|
m_view = aView;
|
|
|
|
if( m_view == NULL )
|
|
return;
|
|
|
|
m_items = new KIGFX::VIEW_GROUP( m_view );
|
|
m_items->SetLayer( LAYER_SELECT_OVERLAY ) ;
|
|
m_view->Add( m_items );
|
|
}
|
|
|
|
void AddPoint( VECTOR2I aP, int aColor, const std::string aName = "" ) override
|
|
{
|
|
SHAPE_LINE_CHAIN l;
|
|
|
|
l.Append( aP - VECTOR2I( -50000, -50000 ) );
|
|
l.Append( aP + VECTOR2I( -50000, -50000 ) );
|
|
|
|
AddLine( l, aColor, 10000 );
|
|
|
|
l.Clear();
|
|
l.Append( aP - VECTOR2I( 50000, -50000 ) );
|
|
l.Append( aP + VECTOR2I( 50000, -50000 ) );
|
|
|
|
AddLine( l, aColor, 10000 );
|
|
}
|
|
|
|
void AddBox( BOX2I aB, int aColor, const std::string aName = "" ) override
|
|
{
|
|
SHAPE_LINE_CHAIN l;
|
|
|
|
VECTOR2I o = aB.GetOrigin();
|
|
VECTOR2I s = aB.GetSize();
|
|
|
|
l.Append( o );
|
|
l.Append( o.x + s.x, o.y );
|
|
l.Append( o.x + s.x, o.y + s.y );
|
|
l.Append( o.x, o.y + s.y );
|
|
l.Append( o );
|
|
|
|
AddLine( l, aColor, 10000 );
|
|
}
|
|
|
|
void AddSegment( SEG aS, int aColor, const std::string aName = "" ) override
|
|
{
|
|
SHAPE_LINE_CHAIN l;
|
|
|
|
l.Append( aS.A );
|
|
l.Append( aS.B );
|
|
|
|
AddLine( l, aColor, 10000 );
|
|
}
|
|
|
|
void AddDirections( VECTOR2D aP, int aMask, int aColor,
|
|
const std::string aName = "" ) override
|
|
{
|
|
BOX2I b( aP - VECTOR2I( 10000, 10000 ), VECTOR2I( 20000, 20000 ) );
|
|
|
|
AddBox( b, aColor );
|
|
for( int i = 0; i < 8; i++ )
|
|
{
|
|
if( ( 1 << i ) & aMask )
|
|
{
|
|
VECTOR2I v = DIRECTION_45( ( DIRECTION_45::Directions ) i ).ToVector() * 100000;
|
|
AddSegment( SEG( aP, aP + v ), aColor );
|
|
}
|
|
}
|
|
}
|
|
|
|
void AddLine( const SHAPE_LINE_CHAIN& aLine, int aType, int aWidth,
|
|
const std::string aName = "" ) override
|
|
{
|
|
if( !m_view )
|
|
return;
|
|
|
|
ROUTER_PREVIEW_ITEM* pitem = new ROUTER_PREVIEW_ITEM( NULL, m_view );
|
|
|
|
pitem->Line( aLine, aWidth, aType );
|
|
m_items->Add( pitem ); // Should not be needed, as m_items has been passed as a parent group in alloc;
|
|
m_view->Update( m_items );
|
|
}
|
|
|
|
void Clear() override
|
|
{
|
|
if( m_view && m_items )
|
|
{
|
|
m_items->FreeItems();
|
|
m_view->Update( m_items );
|
|
}
|
|
}
|
|
|
|
private:
|
|
KIGFX::VIEW* m_view;
|
|
KIGFX::VIEW_GROUP* m_items;
|
|
};
|
|
|
|
|
|
PNS::DEBUG_DECORATOR* PNS_KICAD_IFACE_BASE::GetDebugDecorator()
|
|
{
|
|
return m_debugDecorator;
|
|
}
|
|
|
|
|
|
PNS_KICAD_IFACE_BASE::PNS_KICAD_IFACE_BASE()
|
|
{
|
|
m_ruleResolver = nullptr;
|
|
m_board = nullptr;
|
|
m_world = nullptr;
|
|
m_debugDecorator = nullptr;
|
|
}
|
|
|
|
|
|
PNS_KICAD_IFACE::PNS_KICAD_IFACE()
|
|
{
|
|
m_tool = nullptr;
|
|
m_view = nullptr;
|
|
m_previewItems = nullptr;
|
|
m_dispOptions = nullptr;
|
|
}
|
|
|
|
|
|
PNS_KICAD_IFACE_BASE::~PNS_KICAD_IFACE_BASE()
|
|
{
|
|
}
|
|
|
|
|
|
PNS_KICAD_IFACE::~PNS_KICAD_IFACE()
|
|
{
|
|
delete m_ruleResolver;
|
|
delete m_debugDecorator;
|
|
|
|
if( m_previewItems )
|
|
{
|
|
m_previewItems->FreeItems();
|
|
delete m_previewItems;
|
|
}
|
|
}
|
|
|
|
|
|
std::unique_ptr<PNS::SOLID> PNS_KICAD_IFACE_BASE::syncPad( PAD* aPad )
|
|
{
|
|
LAYER_RANGE layers( 0, MAX_CU_LAYERS - 1 );
|
|
|
|
// ignore non-copper pads except for those with holes
|
|
if( ( aPad->GetLayerSet() & LSET::AllCuMask() ).none() && aPad->GetDrillSize().x == 0 )
|
|
return NULL;
|
|
|
|
switch( aPad->GetAttribute() )
|
|
{
|
|
case PAD_ATTRIB_PTH:
|
|
case PAD_ATTRIB_NPTH:
|
|
break;
|
|
|
|
case PAD_ATTRIB_CONN:
|
|
case PAD_ATTRIB_SMD:
|
|
{
|
|
LSET lmsk = aPad->GetLayerSet();
|
|
bool is_copper = false;
|
|
|
|
for( int i = 0; i < MAX_CU_LAYERS; i++ )
|
|
{
|
|
if( lmsk[i] )
|
|
{
|
|
is_copper = true;
|
|
|
|
if( aPad->GetAttribute() != PAD_ATTRIB_NPTH )
|
|
layers = LAYER_RANGE( i );
|
|
|
|
break;
|
|
}
|
|
}
|
|
|
|
if( !is_copper )
|
|
return NULL;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
wxLogTrace( "PNS", "unsupported pad type 0x%x", aPad->GetAttribute() );
|
|
return NULL;
|
|
}
|
|
|
|
std::unique_ptr<PNS::SOLID> solid = std::make_unique<PNS::SOLID>();
|
|
|
|
if( aPad->GetDrillSize().x > 0 )
|
|
{
|
|
SHAPE_SEGMENT* slot = (SHAPE_SEGMENT*) aPad->GetEffectiveHoleShape()->Clone();
|
|
|
|
if( aPad->GetAttribute() != PAD_ATTRIB_NPTH )
|
|
{
|
|
BOARD_DESIGN_SETTINGS& bds = m_board->GetDesignSettings();
|
|
slot->SetWidth( slot->GetWidth() + bds.GetHolePlatingThickness() * 2 );
|
|
}
|
|
|
|
solid->SetAlternateShape( slot );
|
|
}
|
|
|
|
if( aPad->GetAttribute() == PAD_ATTRIB_NPTH )
|
|
solid->SetRoutable( false );
|
|
|
|
solid->SetLayers( layers );
|
|
solid->SetNet( aPad->GetNetCode() );
|
|
solid->SetParent( aPad );
|
|
solid->SetPadToDie( aPad->GetPadToDieLength() );
|
|
|
|
wxPoint wx_c = aPad->ShapePos();
|
|
wxPoint offset = aPad->GetOffset();
|
|
|
|
VECTOR2I c( wx_c.x, wx_c.y );
|
|
|
|
RotatePoint( &offset, aPad->GetOrientation() );
|
|
|
|
solid->SetPos( VECTOR2I( c.x - offset.x, c.y - offset.y ) );
|
|
solid->SetOffset( VECTOR2I( offset.x, offset.y ) );
|
|
|
|
|
|
auto shapes = std::dynamic_pointer_cast<SHAPE_COMPOUND>( aPad->GetEffectiveShape() );
|
|
|
|
if( shapes && shapes->Size() == 1 )
|
|
{
|
|
solid->SetShape( shapes->Clone() );
|
|
}
|
|
else
|
|
{
|
|
// Fixme (but not urgent). For complex pad shapes, we pass a single simple polygon to the
|
|
// router, otherwise it won't know how to correctly build walkaround 'hulls' for the pad
|
|
// primitives - it can recognize only simple shapes, but not COMPOUNDs made of multiple shapes.
|
|
// The proper way to fix this would be to implement SHAPE_COMPOUND::ConvertToSimplePolygon(),
|
|
// but the complexity of pad polygonization code (see PAD::GetEffectivePolygon), including approximation
|
|
// error handling makes me slightly scared to do it right now.
|
|
|
|
const std::shared_ptr<SHAPE_POLY_SET>& outline = aPad->GetEffectivePolygon();
|
|
SHAPE_SIMPLE* shape = new SHAPE_SIMPLE();
|
|
|
|
for( auto iter = outline->CIterate( 0 ); iter; iter++ )
|
|
shape->Append( *iter );
|
|
|
|
solid->SetShape( shape );
|
|
}
|
|
|
|
return solid;
|
|
}
|
|
|
|
|
|
std::unique_ptr<PNS::SEGMENT> PNS_KICAD_IFACE_BASE::syncTrack( TRACK* aTrack )
|
|
{
|
|
auto segment = std::make_unique<PNS::SEGMENT>( SEG( aTrack->GetStart(), aTrack->GetEnd() ),
|
|
aTrack->GetNetCode() );
|
|
|
|
segment->SetWidth( aTrack->GetWidth() );
|
|
segment->SetLayers( LAYER_RANGE( aTrack->GetLayer() ) );
|
|
segment->SetParent( aTrack );
|
|
|
|
if( aTrack->IsLocked() )
|
|
segment->Mark( PNS::MK_LOCKED );
|
|
|
|
return segment;
|
|
}
|
|
|
|
|
|
std::unique_ptr<PNS::ARC> PNS_KICAD_IFACE_BASE::syncArc( ARC* aArc )
|
|
{
|
|
auto arc = std::make_unique<PNS::ARC>( SHAPE_ARC( aArc->GetStart(), aArc->GetMid(), aArc->GetEnd(),
|
|
aArc->GetWidth() ),
|
|
aArc->GetNetCode() );
|
|
|
|
arc->SetLayers( LAYER_RANGE( aArc->GetLayer() ) );
|
|
arc->SetParent( aArc );
|
|
|
|
if( aArc->IsLocked() )
|
|
arc->Mark( PNS::MK_LOCKED );
|
|
|
|
return arc;
|
|
}
|
|
|
|
|
|
std::unique_ptr<PNS::VIA> PNS_KICAD_IFACE_BASE::syncVia( VIA* aVia )
|
|
{
|
|
PCB_LAYER_ID top, bottom;
|
|
aVia->LayerPair( &top, &bottom );
|
|
|
|
auto via = std::make_unique<PNS::VIA>( aVia->GetPosition(),
|
|
LAYER_RANGE( aVia->TopLayer(), aVia->BottomLayer() ),
|
|
aVia->GetWidth(),
|
|
aVia->GetDrillValue(),
|
|
aVia->GetNetCode(),
|
|
aVia->GetViaType() );
|
|
|
|
via->SetParent( aVia );
|
|
|
|
if( aVia->IsLocked() )
|
|
via->Mark( PNS::MK_LOCKED );
|
|
|
|
return via;
|
|
}
|
|
|
|
|
|
bool PNS_KICAD_IFACE_BASE::syncZone( PNS::NODE* aWorld, ZONE* aZone, SHAPE_POLY_SET* aBoardOutline )
|
|
{
|
|
SHAPE_POLY_SET poly;
|
|
|
|
// TODO handle no-via restriction
|
|
if( !aZone->GetIsRuleArea() || !aZone->GetDoNotAllowTracks() )
|
|
return false;
|
|
|
|
LSET layers = aZone->GetLayerSet();
|
|
EDA_UNITS units = EDA_UNITS::MILLIMETRES; // TODO: get real units
|
|
|
|
for( int layer = F_Cu; layer <= B_Cu; layer++ )
|
|
{
|
|
if( ! layers[ layer ] )
|
|
continue;
|
|
|
|
aZone->BuildSmoothedPoly( poly, ToLAYER_ID( layer ), aBoardOutline );
|
|
poly.CacheTriangulation();
|
|
|
|
if( !poly.IsTriangulationUpToDate() )
|
|
{
|
|
KIDIALOG dlg( nullptr, wxString::Format( _( "%s is malformed." ),
|
|
aZone->GetSelectMenuText( units ) ),
|
|
KIDIALOG::KD_WARNING );
|
|
dlg.ShowDetailedText( wxString::Format( _( "This zone cannot be handled by the track "
|
|
"layout tool.\n"
|
|
"Please verify it is not a "
|
|
"self-intersecting polygon." ) ) );
|
|
dlg.DoNotShowCheckbox( __FILE__, __LINE__ );
|
|
dlg.ShowModal();
|
|
|
|
return false;
|
|
}
|
|
|
|
for( int outline = 0; outline < poly.OutlineCount(); outline++ )
|
|
{
|
|
const SHAPE_POLY_SET::TRIANGULATED_POLYGON* tri = poly.TriangulatedPolygon( outline );
|
|
|
|
for( size_t i = 0; i < tri->GetTriangleCount(); i++)
|
|
{
|
|
VECTOR2I a, b, c;
|
|
tri->GetTriangle( i, a, b, c );
|
|
SHAPE_SIMPLE* triShape = new SHAPE_SIMPLE;
|
|
|
|
triShape->Append( a );
|
|
triShape->Append( b );
|
|
triShape->Append( c );
|
|
|
|
std::unique_ptr<PNS::SOLID> solid = std::make_unique<PNS::SOLID>();
|
|
|
|
solid->SetLayer( layer );
|
|
solid->SetNet( -1 );
|
|
solid->SetParent( aZone );
|
|
solid->SetShape( triShape );
|
|
solid->SetRoutable( false );
|
|
|
|
aWorld->Add( std::move( solid ) );
|
|
}
|
|
}
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
|
|
bool PNS_KICAD_IFACE_BASE::syncTextItem( PNS::NODE* aWorld, EDA_TEXT* aText, PCB_LAYER_ID aLayer )
|
|
{
|
|
if( !IsCopperLayer( aLayer ) )
|
|
return false;
|
|
|
|
int textWidth = aText->GetEffectiveTextPenWidth();
|
|
std::vector<wxPoint> textShape = aText->TransformToSegmentList();
|
|
|
|
if( textShape.size() < 2 )
|
|
return false;
|
|
|
|
for( size_t jj = 0; jj < textShape.size(); jj += 2 )
|
|
{
|
|
VECTOR2I start( textShape[jj] );
|
|
VECTOR2I end( textShape[jj+1] );
|
|
std::unique_ptr<PNS::SOLID> solid = std::make_unique<PNS::SOLID>();
|
|
|
|
solid->SetLayer( aLayer );
|
|
solid->SetNet( -1 );
|
|
solid->SetParent( dynamic_cast<BOARD_ITEM*>( aText ) );
|
|
solid->SetShape( new SHAPE_SEGMENT( start, end, textWidth ) );
|
|
solid->SetRoutable( false );
|
|
|
|
aWorld->Add( std::move( solid ) );
|
|
}
|
|
|
|
return true;
|
|
|
|
/* A coarser (but faster) method:
|
|
*
|
|
SHAPE_POLY_SET outline;
|
|
SHAPE_SIMPLE* shape = new SHAPE_SIMPLE();
|
|
|
|
aText->TransformBoundingBoxWithClearanceToPolygon( &outline, 0 );
|
|
|
|
for( auto iter = outline.CIterate( 0 ); iter; iter++ )
|
|
shape->Append( *iter );
|
|
|
|
solid->SetShape( shape );
|
|
|
|
solid->SetLayer( aLayer );
|
|
solid->SetNet( -1 );
|
|
solid->SetParent( nullptr );
|
|
solid->SetRoutable( false );
|
|
aWorld->Add( std::move( solid ) );
|
|
return true;
|
|
*/
|
|
}
|
|
|
|
|
|
bool PNS_KICAD_IFACE_BASE::syncGraphicalItem( PNS::NODE* aWorld, PCB_SHAPE* aItem )
|
|
{
|
|
if( aItem->GetLayer() == Edge_Cuts
|
|
|| aItem->GetLayer() == Margin
|
|
|| IsCopperLayer( aItem->GetLayer() ) )
|
|
{
|
|
// TODO: where do we handle filled polygons on copper layers?
|
|
if( aItem->GetShape() == S_POLYGON && aItem->IsFilled() )
|
|
return false;
|
|
|
|
for( SHAPE* shape : aItem->MakeEffectiveShapes() )
|
|
{
|
|
std::unique_ptr<PNS::SOLID> solid = std::make_unique<PNS::SOLID>();
|
|
|
|
if( aItem->GetLayer() == Edge_Cuts || aItem->GetLayer() == Margin )
|
|
solid->SetLayers( LAYER_RANGE( F_Cu, B_Cu ) );
|
|
else
|
|
solid->SetLayer( aItem->GetLayer() );
|
|
|
|
if( aItem->GetLayer() == Edge_Cuts )
|
|
{
|
|
switch( shape->Type() )
|
|
{
|
|
case SH_SEGMENT: static_cast<SHAPE_SEGMENT*>( shape )->SetWidth( 0 ); break;
|
|
case SH_ARC: static_cast<SHAPE_ARC*>( shape )->SetWidth( 0 ); break;
|
|
case SH_LINE_CHAIN: static_cast<SHAPE_LINE_CHAIN*>( shape )->SetWidth( 0 ); break;
|
|
default: /* remaining shapes don't have width */ break;
|
|
}
|
|
}
|
|
|
|
solid->SetNet( -1 );
|
|
solid->SetParent( aItem );
|
|
solid->SetShape( shape );
|
|
solid->SetRoutable( false );
|
|
|
|
aWorld->Add( std::move( solid ) );
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
|
|
void PNS_KICAD_IFACE_BASE::SetBoard( BOARD* aBoard )
|
|
{
|
|
m_board = aBoard;
|
|
wxLogTrace( "PNS", "m_board = %p", m_board );
|
|
}
|
|
|
|
|
|
bool PNS_KICAD_IFACE::IsAnyLayerVisible( const LAYER_RANGE& aLayer ) const
|
|
{
|
|
if( !m_view )
|
|
return false;
|
|
|
|
for( int i = aLayer.Start(); i <= aLayer.End(); i++ )
|
|
if( m_view->IsLayerVisible( i ) )
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
|
|
bool PNS_KICAD_IFACE::IsOnLayer( const PNS::ITEM* aItem, int aLayer ) const
|
|
{
|
|
/// Default is all layers
|
|
if( aLayer < 0 )
|
|
return true;
|
|
|
|
if( aItem->Parent() )
|
|
{
|
|
switch( aItem->Parent()->Type() )
|
|
{
|
|
case PCB_VIA_T:
|
|
{
|
|
const VIA* via = static_cast<const VIA*>( aItem->Parent() );
|
|
|
|
return via->FlashLayer( static_cast<PCB_LAYER_ID>( aLayer ) );
|
|
}
|
|
|
|
case PCB_PAD_T:
|
|
{
|
|
const PAD* pad = static_cast<const PAD*>( aItem->Parent() );
|
|
|
|
return pad->FlashLayer( static_cast<PCB_LAYER_ID>( aLayer ) );
|
|
}
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
return aItem->Layers().Overlaps( aLayer );
|
|
}
|
|
|
|
|
|
bool PNS_KICAD_IFACE::IsItemVisible( const PNS::ITEM* aItem ) const
|
|
{
|
|
// by default, all items are visible (new ones created by the router have parent == NULL
|
|
// as they have not been committed yet to the BOARD)
|
|
if( !m_view || !aItem->Parent() )
|
|
return true;
|
|
|
|
BOARD_ITEM* item = aItem->Parent();
|
|
bool isOnVisibleLayer = true;
|
|
RENDER_SETTINGS* settings = m_view->GetPainter()->GetSettings();
|
|
|
|
if( settings->GetHighContrast() )
|
|
isOnVisibleLayer = item->IsOnLayer( settings->GetPrimaryHighContrastLayer() );
|
|
|
|
if( m_view->IsVisible( item ) && isOnVisibleLayer
|
|
&& item->ViewGetLOD( item->GetLayer(), m_view ) < m_view->GetScale() )
|
|
{
|
|
return true;
|
|
}
|
|
|
|
// Items hidden in the router are not hidden on the board
|
|
if( m_hiddenItems.find( item ) != m_hiddenItems.end() )
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
|
|
void PNS_KICAD_IFACE_BASE::SyncWorld( PNS::NODE *aWorld )
|
|
{
|
|
int worstPadClearance = 0;
|
|
|
|
m_world = aWorld;
|
|
|
|
if( !m_board )
|
|
{
|
|
wxLogTrace( "PNS", "No board attached, aborting sync." );
|
|
return;
|
|
}
|
|
|
|
for( BOARD_ITEM* gitem : m_board->Drawings() )
|
|
{
|
|
if ( gitem->Type() == PCB_SHAPE_T )
|
|
{
|
|
syncGraphicalItem( aWorld, static_cast<PCB_SHAPE*>( gitem ) );
|
|
}
|
|
else if( gitem->Type() == PCB_TEXT_T )
|
|
{
|
|
syncTextItem( aWorld, static_cast<PCB_TEXT*>( gitem ), gitem->GetLayer() );
|
|
}
|
|
}
|
|
|
|
SHAPE_POLY_SET buffer;
|
|
SHAPE_POLY_SET* boardOutline = nullptr;
|
|
|
|
if( m_board->GetBoardPolygonOutlines( buffer ) )
|
|
boardOutline = &buffer;
|
|
|
|
for( ZONE* zone : m_board->Zones() )
|
|
{
|
|
syncZone( aWorld, zone, boardOutline );
|
|
}
|
|
|
|
for( FOOTPRINT* footprint : m_board->Footprints() )
|
|
{
|
|
for( PAD* pad : footprint->Pads() )
|
|
{
|
|
if( std::unique_ptr<PNS::SOLID> solid = syncPad( pad ) )
|
|
aWorld->Add( std::move( solid ) );
|
|
|
|
worstPadClearance = std::max( worstPadClearance, pad->GetLocalClearance() );
|
|
}
|
|
|
|
syncTextItem( aWorld, &footprint->Reference(), footprint->Reference().GetLayer() );
|
|
syncTextItem( aWorld, &footprint->Value(), footprint->Value().GetLayer() );
|
|
|
|
for( FP_ZONE* zone : footprint->Zones() )
|
|
syncZone( aWorld, zone, boardOutline );
|
|
|
|
if( footprint->IsNetTie() )
|
|
continue;
|
|
|
|
for( BOARD_ITEM* mgitem : footprint->GraphicalItems() )
|
|
{
|
|
if( mgitem->Type() == PCB_FP_SHAPE_T )
|
|
{
|
|
syncGraphicalItem( aWorld, static_cast<PCB_SHAPE*>( mgitem ) );
|
|
}
|
|
else if( mgitem->Type() == PCB_FP_TEXT_T )
|
|
{
|
|
syncTextItem( aWorld, static_cast<FP_TEXT*>( mgitem ), mgitem->GetLayer() );
|
|
}
|
|
}
|
|
}
|
|
|
|
for( TRACK* t : m_board->Tracks() )
|
|
{
|
|
KICAD_T type = t->Type();
|
|
|
|
if( type == PCB_TRACE_T )
|
|
{
|
|
if( auto segment = syncTrack( t ) )
|
|
aWorld->Add( std::move( segment ) );
|
|
}
|
|
else if( type == PCB_ARC_T )
|
|
{
|
|
if( auto arc = syncArc( static_cast<ARC*>( t ) ) )
|
|
aWorld->Add( std::move( arc ) );
|
|
}
|
|
else if( type == PCB_VIA_T )
|
|
{
|
|
if( auto via = syncVia( static_cast<VIA*>( t ) ) )
|
|
aWorld->Add( std::move( via ) );
|
|
}
|
|
}
|
|
|
|
int worstRuleClearance = m_board->GetDesignSettings().GetBiggestClearanceValue();
|
|
|
|
// NB: if this were ever to become a long-lived object we would need to dirty its
|
|
// clearance cache here....
|
|
delete m_ruleResolver;
|
|
m_ruleResolver = new PNS_PCBNEW_RULE_RESOLVER( m_board, this );
|
|
|
|
aWorld->SetRuleResolver( m_ruleResolver );
|
|
aWorld->SetMaxClearance( 4 * std::max(worstPadClearance, worstRuleClearance ) );
|
|
}
|
|
|
|
|
|
void PNS_KICAD_IFACE::EraseView()
|
|
{
|
|
for( auto item : m_hiddenItems )
|
|
m_view->SetVisible( item, true );
|
|
|
|
m_hiddenItems.clear();
|
|
|
|
if( m_previewItems )
|
|
{
|
|
m_previewItems->FreeItems();
|
|
m_view->Update( m_previewItems );
|
|
}
|
|
|
|
if( m_debugDecorator )
|
|
m_debugDecorator->Clear();
|
|
}
|
|
|
|
void PNS_KICAD_IFACE_BASE::SetDebugDecorator( PNS::DEBUG_DECORATOR *aDec )
|
|
{
|
|
m_debugDecorator = aDec;
|
|
}
|
|
|
|
void PNS_KICAD_IFACE::DisplayItem( const PNS::ITEM* aItem, int aColor, int aClearance, bool aEdit )
|
|
{
|
|
wxLogTrace( "PNS", "DisplayItem %p", aItem );
|
|
|
|
ROUTER_PREVIEW_ITEM* pitem = new ROUTER_PREVIEW_ITEM( aItem, m_view );
|
|
|
|
if( aColor >= 0 )
|
|
pitem->SetColor( KIGFX::COLOR4D( aColor ) );
|
|
|
|
if( aClearance >= 0 )
|
|
{
|
|
pitem->SetClearance( aClearance );
|
|
|
|
switch( m_dispOptions->m_ShowTrackClearanceMode )
|
|
{
|
|
case PCB_DISPLAY_OPTIONS::DO_NOT_SHOW_CLEARANCE:
|
|
pitem->ShowTrackClearance( false );
|
|
pitem->ShowViaClearance( false );
|
|
break;
|
|
case PCB_DISPLAY_OPTIONS::SHOW_CLEARANCE_ALWAYS:
|
|
case PCB_DISPLAY_OPTIONS::SHOW_CLEARANCE_NEW_AND_EDITED_TRACKS_AND_VIA_AREAS:
|
|
pitem->ShowTrackClearance( true );
|
|
pitem->ShowViaClearance( true );
|
|
break;
|
|
|
|
case PCB_DISPLAY_OPTIONS::SHOW_CLEARANCE_NEW_TRACKS_AND_VIA_AREAS:
|
|
pitem->ShowTrackClearance( !aEdit );
|
|
pitem->ShowViaClearance( !aEdit );
|
|
break;
|
|
|
|
case PCB_DISPLAY_OPTIONS::SHOW_CLEARANCE_NEW_TRACKS:
|
|
pitem->ShowTrackClearance( !aEdit );
|
|
pitem->ShowViaClearance( false );
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
m_previewItems->Add( pitem );
|
|
m_view->Update( m_previewItems );
|
|
}
|
|
|
|
|
|
void PNS_KICAD_IFACE::DisplayRatline( const SHAPE_LINE_CHAIN& aRatline, int aColor )
|
|
{
|
|
ROUTER_PREVIEW_ITEM* pitem = new ROUTER_PREVIEW_ITEM( nullptr, m_view );
|
|
pitem->Line( aRatline, 10000, aColor );
|
|
m_previewItems->Add( pitem );
|
|
m_view->Update( m_previewItems );
|
|
}
|
|
|
|
|
|
void PNS_KICAD_IFACE::HideItem( PNS::ITEM* aItem )
|
|
{
|
|
BOARD_ITEM* parent = aItem->Parent();
|
|
|
|
if( parent )
|
|
{
|
|
if( m_view->IsVisible( parent ) )
|
|
m_hiddenItems.insert( parent );
|
|
|
|
m_view->SetVisible( parent, false );
|
|
m_view->Update( parent, KIGFX::APPEARANCE );
|
|
}
|
|
}
|
|
|
|
|
|
void PNS_KICAD_IFACE_BASE::RemoveItem( PNS::ITEM* aItem )
|
|
{
|
|
|
|
}
|
|
|
|
|
|
void PNS_KICAD_IFACE::RemoveItem( PNS::ITEM* aItem )
|
|
{
|
|
BOARD_ITEM* parent = aItem->Parent();
|
|
|
|
if ( aItem->OfKind(PNS::ITEM::SOLID_T) )
|
|
{
|
|
PAD* pad = static_cast<PAD*>( parent );
|
|
VECTOR2I pos = static_cast<PNS::SOLID*>( aItem )->Pos();
|
|
|
|
m_fpOffsets[ pad ].p_old = pos;
|
|
return;
|
|
}
|
|
|
|
if( parent )
|
|
{
|
|
m_commit->Remove( parent );
|
|
}
|
|
}
|
|
|
|
|
|
void PNS_KICAD_IFACE_BASE::AddItem( PNS::ITEM* aItem )
|
|
{
|
|
|
|
}
|
|
|
|
|
|
void PNS_KICAD_IFACE::AddItem( PNS::ITEM* aItem )
|
|
{
|
|
BOARD_CONNECTED_ITEM* newBI = NULL;
|
|
|
|
switch( aItem->Kind() )
|
|
{
|
|
case PNS::ITEM::ARC_T:
|
|
{
|
|
auto arc = static_cast<PNS::ARC*>( aItem );
|
|
ARC* new_arc = new ARC( m_board, static_cast<const SHAPE_ARC*>( arc->Shape() ) );
|
|
new_arc->SetWidth( arc->Width() );
|
|
new_arc->SetLayer( ToLAYER_ID( arc->Layers().Start() ) );
|
|
new_arc->SetNetCode( std::max<int>( 0, arc->Net() ) );
|
|
newBI = new_arc;
|
|
break;
|
|
}
|
|
|
|
case PNS::ITEM::SEGMENT_T:
|
|
{
|
|
PNS::SEGMENT* seg = static_cast<PNS::SEGMENT*>( aItem );
|
|
TRACK* track = new TRACK( m_board );
|
|
const SEG& s = seg->Seg();
|
|
track->SetStart( wxPoint( s.A.x, s.A.y ) );
|
|
track->SetEnd( wxPoint( s.B.x, s.B.y ) );
|
|
track->SetWidth( seg->Width() );
|
|
track->SetLayer( ToLAYER_ID( seg->Layers().Start() ) );
|
|
track->SetNetCode( seg->Net() > 0 ? seg->Net() : 0 );
|
|
newBI = track;
|
|
break;
|
|
}
|
|
|
|
case PNS::ITEM::VIA_T:
|
|
{
|
|
VIA* via_board = new VIA( m_board );
|
|
PNS::VIA* via = static_cast<PNS::VIA*>( aItem );
|
|
via_board->SetPosition( wxPoint( via->Pos().x, via->Pos().y ) );
|
|
via_board->SetWidth( via->Diameter() );
|
|
via_board->SetDrill( via->Drill() );
|
|
via_board->SetNetCode( via->Net() > 0 ? via->Net() : 0 );
|
|
via_board->SetViaType( via->ViaType() ); // MUST be before SetLayerPair()
|
|
via_board->SetLayerPair( ToLAYER_ID( via->Layers().Start() ),
|
|
ToLAYER_ID( via->Layers().End() ) );
|
|
newBI = via_board;
|
|
break;
|
|
}
|
|
|
|
case PNS::ITEM::SOLID_T:
|
|
{
|
|
PAD* pad = static_cast<PAD*>( aItem->Parent() );
|
|
VECTOR2I pos = static_cast<PNS::SOLID*>( aItem )->Pos();
|
|
|
|
m_fpOffsets[ pad ].p_new = pos;
|
|
return;
|
|
}
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if( newBI )
|
|
{
|
|
//newBI->SetLocalRatsnestVisible( m_dispOptions->m_ShowGlobalRatsnest );
|
|
aItem->SetParent( newBI );
|
|
newBI->ClearFlags();
|
|
|
|
m_commit->Add( newBI );
|
|
}
|
|
}
|
|
|
|
|
|
void PNS_KICAD_IFACE::Commit()
|
|
{
|
|
std::set<FOOTPRINT*> processedMods;
|
|
|
|
EraseView();
|
|
|
|
for( auto fpOffset : m_fpOffsets )
|
|
{
|
|
auto offset = fpOffset.second.p_new - fpOffset.second.p_old;
|
|
auto mod = fpOffset.first->GetParent();
|
|
|
|
VECTOR2I p_orig = mod->GetPosition();
|
|
VECTOR2I p_new = p_orig + offset;
|
|
|
|
if( processedMods.find( mod ) != processedMods.end() )
|
|
continue;
|
|
|
|
processedMods.insert( mod );
|
|
m_commit->Modify( mod );
|
|
mod->SetPosition( wxPoint( p_new.x, p_new.y ));
|
|
}
|
|
|
|
m_fpOffsets.clear();
|
|
|
|
m_commit->Push( _( "Interactive Router" ) );
|
|
m_commit = std::make_unique<BOARD_COMMIT>( m_tool );
|
|
}
|
|
|
|
|
|
void PNS_KICAD_IFACE::SetView( KIGFX::VIEW* aView )
|
|
{
|
|
wxLogTrace( "PNS", "SetView %p", aView );
|
|
|
|
if( m_previewItems )
|
|
{
|
|
m_previewItems->FreeItems();
|
|
delete m_previewItems;
|
|
}
|
|
|
|
m_view = aView;
|
|
m_previewItems = new KIGFX::VIEW_GROUP( m_view );
|
|
m_previewItems->SetLayer( LAYER_SELECT_OVERLAY ) ;
|
|
|
|
if(m_view)
|
|
m_view->Add( m_previewItems );
|
|
|
|
delete m_debugDecorator;
|
|
|
|
auto dec = new PNS_PCBNEW_DEBUG_DECORATOR();
|
|
m_debugDecorator = dec;
|
|
|
|
if( ADVANCED_CFG::GetCfg().m_ShowRouterDebugGraphics )
|
|
dec->SetView( m_view );
|
|
}
|
|
|
|
|
|
void PNS_KICAD_IFACE::UpdateNet( int aNetCode )
|
|
{
|
|
wxLogTrace( "PNS", "Update-net %d", aNetCode );
|
|
|
|
}
|
|
|
|
PNS::RULE_RESOLVER* PNS_KICAD_IFACE_BASE::GetRuleResolver()
|
|
{
|
|
return m_ruleResolver;
|
|
}
|
|
|
|
|
|
void PNS_KICAD_IFACE::SetHostTool( PCB_TOOL_BASE* aTool )
|
|
{
|
|
m_tool = aTool;
|
|
m_commit = std::make_unique<BOARD_COMMIT>( m_tool );
|
|
}
|
|
|
|
void PNS_KICAD_IFACE::SetDisplayOptions( const PCB_DISPLAY_OPTIONS* aDispOptions )
|
|
{
|
|
m_dispOptions = aDispOptions;
|
|
}
|