1789 lines
59 KiB
C++
1789 lines
59 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright (C) 2007-2015 SoftPLC Corporation, Dick Hollenbeck <dick@softplc.com>
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* Copyright (C) 2015-2017 KiCad Developers, see AUTHORS.txt for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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/* This source is a complement to specctra.cpp and implements the export to
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specctra dsn file format. The specification for the grammar of the specctra
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dsn file used to develop this code is given here:
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http://tech.groups.yahoo.com/group/kicad-users/files/ then file "specctra.pdf"
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Also see the comments at the top of the specctra.cpp file itself.
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*/
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#include <pcb_edit_frame.h>
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#include <confirm.h> // DisplayError()
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#include <gestfich.h> // EDA_FileSelector()
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#include <trigo.h> // RotatePoint()
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#include <macros.h>
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#include <set> // std::set
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#include <map> // std::map
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#include <boost/utility.hpp> // boost::addressof()
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#include <class_board.h>
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#include <class_module.h>
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#include <class_edge_mod.h>
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#include <class_track.h>
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#include <class_zone.h>
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#include <class_drawsegment.h>
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#include <base_units.h>
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#include <wildcards_and_files_ext.h>
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#include <collectors.h>
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#include <geometry/shape_poly_set.h>
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#include <geometry/convex_hull.h>
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#include <convert_basic_shapes_to_polygon.h>
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#include "specctra.h"
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using namespace DSN;
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// comment the line #define EXPORT_CUSTOM_PADS_CONVEX_HULL to export CUSTOM pads exact shapes.
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// Keep in mind shapes can be non convex polygons with holes (linked to outline)
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// that can create issues.
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// Especially Freerouter does not handle them very well:
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// - too complex shapes are not accepted, especially shapes with holes (dsn files are not loaded).
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// - and Freerouter actually uses something like a convex hull of the shape (that works not very well).
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// I am guessing non convex polygons with holes linked could create issues with any Router.
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#define EXPORT_CUSTOM_PADS_CONVEX_HULL
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// Add .1 mil to the requested clearances as a safety margin.
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// There has been disagreement about interpretation of clearance in the past
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// between KiCad and Freerouter, so keep this safetyMargin until the
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// disagreement is resolved and stable. Freerouter seems to be moving
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// (protected) traces upon loading the DSN file, and even though it seems to sometimes
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// add its own 0.1 to the clearances, I believe this is happening after
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// the load process (and moving traces) so I am of the opinion this is
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// still needed.
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static const double safetyMargin = 0.1;
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// see pcb_edit_frame.h
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void PCB_EDIT_FRAME::ExportToSpecctra( wxCommandEvent& event )
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{
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wxString fullFileName;
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wxString dsn_ext = SpecctraDsnFileExtension;
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wxString mask = SpecctraDsnFileWildcard();
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wxFileName fn( GetBoard()->GetFileName() );
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fn.SetExt( dsn_ext );
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fullFileName = EDA_FILE_SELECTOR( _( "Specctra DSN File" ),
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fn.GetPath(),
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fn.GetFullName(),
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dsn_ext,
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mask,
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this,
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wxFD_SAVE | wxFD_OVERWRITE_PROMPT,
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false );
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if( fullFileName == wxEmptyString )
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return;
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ExportSpecctraFile( fullFileName );
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}
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bool PCB_EDIT_FRAME::ExportSpecctraFile( const wxString& aFullFilename )
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{
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SPECCTRA_DB db;
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bool ok = true;
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wxString errorText;
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BASE_SCREEN* screen = GetScreen();
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bool wasModified = screen->IsModify();
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db.SetPCB( SPECCTRA_DB::MakePCB() );
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LOCALE_IO toggle; // Switch the locale to standard C
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// DSN Images (=KiCad MODULES and pads) must be presented from the
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// top view. So we temporarily flip any modules which are on the back
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// side of the board to the front, and record this in the MODULE's flag field.
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db.FlipMODULEs( GetBoard() );
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try
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{
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GetBoard()->SynchronizeNetsAndNetClasses();
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db.FromBOARD( GetBoard() );
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db.ExportPCB( aFullFilename, true );
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// if an exception is thrown by FromBOARD or ExportPCB(), then
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// ~SPECCTRA_DB() will close the file.
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}
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catch( const IO_ERROR& ioe )
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{
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ok = false;
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// copy the error string to safe place, ioe is in this scope only.
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errorText = ioe.What();
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}
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// done assuredly, even if an exception was thrown and caught.
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db.RevertMODULEs( GetBoard() );
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// The two calls below to MODULE::Flip(), both set the
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// modified flag, yet their actions cancel each other out, so it should
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// be ok to clear the modify flag.
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if( !wasModified )
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screen->ClrModify();
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if( ok )
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{
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SetStatusText( wxString( _( "BOARD exported OK." ) ) );
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}
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else
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{
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DisplayErrorMessage( this,
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_( "Unable to export, please fix and try again" ),
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errorText );
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}
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return ok;
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}
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namespace DSN {
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const KICAD_T SPECCTRA_DB::scanPADs[] = { PCB_PAD_T, EOT };
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// "specctra reported units" are what we tell the external router that our
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// exported lengths are in.
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/**
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* Function scale
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* converts a distance from PCBNEW internal units to the reported specctra dsn units
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* in floating point format.
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*/
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static inline double scale( int kicadDist )
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{
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// nanometers to um
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return kicadDist / ( IU_PER_MM / 1000.0 );
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}
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// / Convert integer internal units to float um
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static inline double IU2um( int kicadDist )
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{
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return kicadDist * (1000.0 / IU_PER_MM);
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}
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static inline double mapX( int x )
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{
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return scale( x );
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}
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static inline double mapY( int y )
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{
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return -scale( y ); // make y negative, since it is increasing going down.
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}
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/**
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* Function mapPt
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* converts a KiCad point into a DSN file point. Kicad's BOARD coordinates
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* are in nanometers (called Internal Units or IU)and we are exporting in units
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* of mils, so we have to scale them.
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*/
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static POINT mapPt( const wxPoint& pt )
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{
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POINT ret;
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ret.x = mapX( pt.x );
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ret.y = mapY( pt.y );
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ret.FixNegativeZero();
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return ret;
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}
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/**
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* Function isRoundKeepout
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* decides if the pad is a copper-less through hole which needs to be made into
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* a round keepout.
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*/
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static bool isRoundKeepout( D_PAD* aPad )
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{
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if( aPad->GetShape()==PAD_SHAPE_CIRCLE )
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{
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if( aPad->GetDrillSize().x >= aPad->GetSize().x )
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return true;
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if( !( aPad->GetLayerSet() & LSET::AllCuMask() ).any() )
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return true;
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}
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return false;
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}
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/**
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* Function makePath
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* creates a PATH element with a single straight line, a pair of vertices.
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*/
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static PATH* makePath( const POINT& aStart, const POINT& aEnd, const std::string& aLayerName )
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{
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PATH* path = new PATH( 0, T_path );
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path->AppendPoint( aStart );
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path->AppendPoint( aEnd );
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path->SetLayerId( aLayerName.c_str() );
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return path;
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}
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PADSTACK* SPECCTRA_DB::makePADSTACK( BOARD* aBoard, D_PAD* aPad )
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{
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char name[256]; // padstack name builder
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std::string uniqifier;
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// caller must do these checks before calling here.
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wxASSERT( !isRoundKeepout( aPad ) );
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PADSTACK* padstack = new PADSTACK();
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int reportedLayers = 0; // how many in reported padstack
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const char* layerName[MAX_CU_LAYERS];
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uniqifier = '[';
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static const LSET all_cu = LSET::AllCuMask();
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bool onAllCopperLayers = ( (aPad->GetLayerSet() & all_cu) == all_cu );
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if( onAllCopperLayers )
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uniqifier += 'A'; // A for all layers
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const int copperCount = aBoard->GetCopperLayerCount();
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for( int layer=0; layer<copperCount; ++layer )
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{
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PCB_LAYER_ID kilayer = pcbLayer2kicad[layer];
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if( onAllCopperLayers || aPad->IsOnLayer( kilayer ) )
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{
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layerName[reportedLayers++] = layerIds[layer].c_str();
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if( !onAllCopperLayers )
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{
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if( layer == 0 )
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uniqifier += 'T';
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else if( layer == copperCount - 1 )
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uniqifier += 'B';
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else
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uniqifier += char('0' + layer); // layer index char
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}
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}
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}
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uniqifier += ']';
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POINT dsnOffset;
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if( aPad->GetOffset().x || aPad->GetOffset().y )
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{
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char offsetTxt[64];
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wxPoint offset( aPad->GetOffset().x, aPad->GetOffset().y );
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dsnOffset = mapPt( offset );
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// using '(' or ')' would cause padstack name to be quote wrapped,
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// so use other brackets, and {} locks freerouter.
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sprintf( offsetTxt, "[%.6g,%.6g]", dsnOffset.x, dsnOffset.y );
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uniqifier += offsetTxt;
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}
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switch( aPad->GetShape() )
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{
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default:
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case PAD_SHAPE_CIRCLE:
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{
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double diameter = scale( aPad->GetSize().x );
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for( int ndx=0; ndx<reportedLayers; ++ndx )
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{
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SHAPE* shape = new SHAPE( padstack );
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padstack->Append( shape );
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CIRCLE* circle = new CIRCLE( shape );
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shape->SetShape( circle );
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circle->SetLayerId( layerName[ndx] );
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circle->SetDiameter( diameter );
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circle->SetVertex( dsnOffset );
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}
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snprintf( name, sizeof(name), "Round%sPad_%.6g_um",
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uniqifier.c_str(), IU2um( aPad->GetSize().x ) );
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name[ sizeof(name) - 1 ] = 0;
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padstack->SetPadstackId( name );
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}
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break;
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case PAD_SHAPE_RECT:
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{
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double dx = scale( aPad->GetSize().x ) / 2.0;
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double dy = scale( aPad->GetSize().y ) / 2.0;
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POINT lowerLeft( -dx, -dy );
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POINT upperRight( dx, dy );
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lowerLeft += dsnOffset;
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upperRight += dsnOffset;
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for( int ndx=0; ndx<reportedLayers; ++ndx )
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{
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SHAPE* shape = new SHAPE( padstack );
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padstack->Append( shape );
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RECTANGLE* rect = new RECTANGLE( shape );
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shape->SetShape( rect );
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rect->SetLayerId( layerName[ndx] );
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rect->SetCorners( lowerLeft, upperRight );
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}
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snprintf( name, sizeof(name), "Rect%sPad_%.6gx%.6g_um",
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uniqifier.c_str(),
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IU2um( aPad->GetSize().x ),
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IU2um( aPad->GetSize().y ) );
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name[ sizeof(name) - 1 ] = 0;
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padstack->SetPadstackId( name );
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}
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break;
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case PAD_SHAPE_OVAL:
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{
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double dx = scale( aPad->GetSize().x ) / 2.0;
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double dy = scale( aPad->GetSize().y ) / 2.0;
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double dr = dx - dy;
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double radius;
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POINT pstart;
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POINT pstop;
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if( dr >= 0 ) // oval is horizontal
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{
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radius = dy;
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pstart = POINT( -dr, 0.0 );
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pstop = POINT( dr, 0.0 );
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}
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else // oval is vertical
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{
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radius = dx;
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dr = -dr;
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pstart = POINT( 0.0, -dr );
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pstop = POINT( 0.0, dr );
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}
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pstart += dsnOffset;
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pstop += dsnOffset;
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for( int ndx=0; ndx<reportedLayers; ++ndx )
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{
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SHAPE* shape;
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PATH* path;
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// see http://www.freerouting.net/usren/viewtopic.php?f=3&t=317#p408
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shape = new SHAPE( padstack );
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padstack->Append( shape );
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path = makePath( pstart, pstop, layerName[ndx] );
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shape->SetShape( path );
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path->aperture_width = 2.0 * radius;
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}
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snprintf( name, sizeof(name), "Oval%sPad_%.6gx%.6g_um",
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uniqifier.c_str(),
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IU2um( aPad->GetSize().x ),
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IU2um( aPad->GetSize().y ) );
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name[ sizeof(name) - 1 ] = 0;
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padstack->SetPadstackId( name );
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}
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break;
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case PAD_SHAPE_TRAPEZOID:
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{
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double dx = scale( aPad->GetSize().x ) / 2.0;
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double dy = scale( aPad->GetSize().y ) / 2.0;
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double ddx = scale( aPad->GetDelta().x ) / 2.0;
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double ddy = scale( aPad->GetDelta().y ) / 2.0;
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// see class_pad_draw_functions.cpp which draws the trapezoid pad
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POINT lowerLeft( -dx - ddy, -dy - ddx );
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POINT upperLeft( -dx + ddy, +dy + ddx );
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POINT upperRight( +dx - ddy, +dy - ddx );
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POINT lowerRight( +dx + ddy, -dy + ddx );
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lowerLeft += dsnOffset;
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upperLeft += dsnOffset;
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upperRight += dsnOffset;
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lowerRight += dsnOffset;
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for( int ndx=0; ndx<reportedLayers; ++ndx )
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{
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SHAPE* shape = new SHAPE( padstack );
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padstack->Append( shape );
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// a T_polygon exists as a PATH
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PATH* polygon = new PATH( shape, T_polygon );
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shape->SetShape( polygon );
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polygon->SetLayerId( layerName[ndx] );
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polygon->AppendPoint( lowerLeft );
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polygon->AppendPoint( upperLeft );
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polygon->AppendPoint( upperRight );
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polygon->AppendPoint( lowerRight );
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}
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// this string _must_ be unique for a given physical shape
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snprintf( name, sizeof(name), "Trapz%sPad_%.6gx%.6g_%c%.6gx%c%.6g_um",
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uniqifier.c_str(), IU2um( aPad->GetSize().x ), IU2um( aPad->GetSize().y ),
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aPad->GetDelta().x < 0 ? 'n' : 'p',
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std::abs( IU2um( aPad->GetDelta().x )),
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aPad->GetDelta().y < 0 ? 'n' : 'p',
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std::abs( IU2um( aPad->GetDelta().y ) )
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);
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name[ sizeof(name)-1 ] = 0;
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padstack->SetPadstackId( name );
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}
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break;
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case PAD_SHAPE_ROUNDRECT:
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{
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// Export the shape as as polygon, round rect does not exist as primitive
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const int circleToSegmentsCount = 36;
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int rradius = aPad->GetRoundRectCornerRadius();
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SHAPE_POLY_SET cornerBuffer;
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// Use a slightly bigger shape because the round corners are approximated by
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// segments, giving to the polygon a slightly smaller shape than the actual shape
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/* calculates the coeff to compensate radius reduction of holes clearance
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* due to the segment approx.
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* For a circle the min radius is radius * cos( 2PI / s_CircleToSegmentsCount / 2)
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* correctionFactor is 1 /cos( PI/s_CircleToSegmentsCount )
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*/
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double correctionFactor = 1.0 / cos( M_PI / (double) circleToSegmentsCount );
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int extra_clearance = KiROUND( rradius * (1.0 - correctionFactor ) ) + 1;
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wxSize psize = aPad->GetSize();
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psize.x += extra_clearance*2;
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psize.y += extra_clearance*2;
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rradius += extra_clearance;
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TransformRoundRectToPolygon( cornerBuffer, wxPoint(0,0), psize,
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0, rradius, circleToSegmentsCount );
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SHAPE_LINE_CHAIN& polygonal_shape = cornerBuffer.Outline( 0 );
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for( int ndx=0; ndx < reportedLayers; ++ndx )
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{
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SHAPE* shape = new SHAPE( padstack );
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padstack->Append( shape );
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// a T_polygon exists as a PATH
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PATH* polygon = new PATH( shape, T_polygon );
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shape->SetShape( polygon );
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polygon->SetLayerId( layerName[ndx] );
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// append a closed polygon
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POINT first_corner;
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for( int idx = 0; idx < polygonal_shape.PointCount(); idx++ )
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{
|
|
POINT corner( scale( polygonal_shape.Point( idx ).x ),
|
|
scale( -polygonal_shape.Point( idx ).y ) );
|
|
corner += dsnOffset;
|
|
polygon->AppendPoint( corner );
|
|
|
|
if( idx == 0 )
|
|
first_corner = corner;
|
|
}
|
|
polygon->AppendPoint( first_corner ); // Close polygon
|
|
}
|
|
|
|
// this string _must_ be unique for a given physical shape
|
|
snprintf( name, sizeof(name), "RoundRect%sPad_%.6gx%.6g_%.6g_um",
|
|
uniqifier.c_str(),
|
|
IU2um( aPad->GetSize().x ),
|
|
IU2um( aPad->GetSize().y ), IU2um( rradius ) );
|
|
|
|
name[ sizeof(name) - 1 ] = 0;
|
|
|
|
padstack->SetPadstackId( name );
|
|
}
|
|
break;
|
|
|
|
case PAD_SHAPE_CUSTOM:
|
|
{
|
|
std::vector<wxPoint> polygonal_shape;
|
|
const SHAPE_POLY_SET& pad_shape = aPad->GetCustomShapeAsPolygon();
|
|
|
|
#ifdef EXPORT_CUSTOM_PADS_CONVEX_HULL
|
|
BuildConvexHull( polygonal_shape, pad_shape );
|
|
#else
|
|
const SHAPE_LINE_CHAIN& p_outline = pad_shape.COutline( 0 );
|
|
for( int ii = 0; ii < p_outline.PointCount(); ++ii )
|
|
polygonal_shape.push_back( wxPoint( p_outline.CPoint( ii ) ) );
|
|
#endif
|
|
|
|
// The polygon must be closed
|
|
if( polygonal_shape.front() != polygonal_shape.back() )
|
|
polygonal_shape.push_back( polygonal_shape.front() );
|
|
|
|
for( int ndx=0; ndx < reportedLayers; ++ndx )
|
|
{
|
|
SHAPE* shape = new SHAPE( padstack );
|
|
|
|
padstack->Append( shape );
|
|
|
|
// a T_polygon exists as a PATH
|
|
PATH* polygon = new PATH( shape, T_polygon );
|
|
|
|
shape->SetShape( polygon );
|
|
|
|
polygon->SetLayerId( layerName[ndx] );
|
|
|
|
for( unsigned idx = 0; idx < polygonal_shape.size(); idx++ )
|
|
{
|
|
POINT corner( scale( polygonal_shape[idx].x ), scale( -polygonal_shape[idx].y ) );
|
|
corner += dsnOffset;
|
|
polygon->AppendPoint( corner );
|
|
}
|
|
}
|
|
|
|
// this string _must_ be unique for a given physical shape, so try to make it unique
|
|
EDA_RECT rect = aPad->GetBoundingBox();
|
|
snprintf( name, sizeof(name), "Cust%sPad_%.6gx%.6g_%.6gx_%.6g_%d_um",
|
|
uniqifier.c_str(), IU2um( aPad->GetSize().x ), IU2um( aPad->GetSize().y ),
|
|
IU2um( rect.GetWidth() ), IU2um( rect.GetHeight() ),
|
|
(int)polygonal_shape.size() );
|
|
name[ sizeof(name)-1 ] = 0;
|
|
|
|
padstack->SetPadstackId( name );
|
|
}
|
|
break;
|
|
}
|
|
|
|
return padstack;
|
|
}
|
|
|
|
|
|
/// data type used to ensure unique-ness of pin names, holding (wxString and int)
|
|
typedef std::map<wxString, int> PINMAP;
|
|
|
|
|
|
IMAGE* SPECCTRA_DB::makeIMAGE( BOARD* aBoard, MODULE* aModule )
|
|
{
|
|
PINMAP pinmap;
|
|
wxString padName;
|
|
|
|
PCB_TYPE_COLLECTOR moduleItems;
|
|
|
|
// get all the MODULE's pads.
|
|
moduleItems.Collect( aModule, scanPADs );
|
|
|
|
IMAGE* image = new IMAGE(0);
|
|
|
|
image->image_id = aModule->GetFPID().Format().c_str();
|
|
|
|
// from the pads, and make an IMAGE using collated padstacks.
|
|
for( int p=0; p < moduleItems.GetCount(); ++p )
|
|
{
|
|
D_PAD* pad = (D_PAD*) moduleItems[p];
|
|
|
|
// see if this pad is a through hole with no copper on its perimeter
|
|
if( isRoundKeepout( pad ) )
|
|
{
|
|
double diameter = scale( pad->GetDrillSize().x );
|
|
POINT vertex = mapPt( pad->GetPos0() );
|
|
|
|
int layerCount = aBoard->GetCopperLayerCount();
|
|
|
|
for( int layer=0; layer<layerCount; ++layer )
|
|
{
|
|
KEEPOUT* keepout = new KEEPOUT( image, T_keepout );
|
|
|
|
image->keepouts.push_back( keepout );
|
|
|
|
CIRCLE* circle = new CIRCLE( keepout );
|
|
|
|
keepout->SetShape( circle );
|
|
|
|
circle->SetDiameter( diameter );
|
|
circle->SetVertex( vertex );
|
|
circle->SetLayerId( layerIds[layer].c_str() );
|
|
}
|
|
}
|
|
// else if() could there be a square keepout here?
|
|
|
|
else
|
|
{
|
|
// Pads not on copper layers (i.e. only on tech layers) are ignored
|
|
// because they create invalid pads in .dsn file for freeroute
|
|
LSET mask_copper_layers = pad->GetLayerSet() & LSET::AllCuMask();
|
|
|
|
if( !mask_copper_layers.any() )
|
|
continue;
|
|
|
|
PADSTACK* padstack = makePADSTACK( aBoard, pad );
|
|
PADSTACKSET::iterator iter = padstackset.find( *padstack );
|
|
|
|
if( iter != padstackset.end() )
|
|
{
|
|
// padstack is a duplicate, delete it and use the original
|
|
delete padstack;
|
|
padstack = (PADSTACK*) *iter.base(); // folklore, be careful here
|
|
}
|
|
else
|
|
{
|
|
padstackset.insert( padstack );
|
|
}
|
|
|
|
PIN* pin = new PIN( image );
|
|
|
|
padName = pad->GetName();
|
|
pin->pin_id = TO_UTF8( padName );
|
|
|
|
if( padName!=wxEmptyString && pinmap.find( padName )==pinmap.end() )
|
|
{
|
|
pinmap[ padName ] = 0;
|
|
}
|
|
else // pad name is a duplicate within this module
|
|
{
|
|
char buf[32];
|
|
|
|
int duplicates = ++pinmap[ padName ];
|
|
|
|
sprintf( buf, "@%d", duplicates );
|
|
|
|
pin->pin_id += buf; // append "@1" or "@2", etc. to pin name
|
|
}
|
|
|
|
pin->kiNetCode = pad->GetNetCode();
|
|
|
|
image->pins.push_back( pin );
|
|
|
|
pin->padstack_id = padstack->padstack_id;
|
|
|
|
double angle = pad->GetOrientationDegrees() - aModule->GetOrientationDegrees();
|
|
NORMALIZE_ANGLE_DEGREES_POS( angle );
|
|
pin->SetRotation( angle );
|
|
|
|
wxPoint pos( pad->GetPos0() );
|
|
|
|
pin->SetVertex( mapPt( pos ) );
|
|
}
|
|
}
|
|
|
|
#if 1 // enable image (outline) scopes.
|
|
static const KICAD_T scanEDGEs[] = { PCB_MODULE_EDGE_T, EOT };
|
|
|
|
// get all the MODULE's EDGE_MODULEs and convert those to DSN outlines.
|
|
moduleItems.Collect( aModule, scanEDGEs );
|
|
|
|
for( int i = 0; i<moduleItems.GetCount(); ++i )
|
|
{
|
|
EDGE_MODULE* graphic = (EDGE_MODULE*) moduleItems[i];
|
|
SHAPE* outline;
|
|
PATH* path;
|
|
|
|
switch( graphic->GetShape() )
|
|
{
|
|
case S_SEGMENT:
|
|
outline = new SHAPE( image, T_outline );
|
|
|
|
image->Append( outline );
|
|
path = new PATH( outline );
|
|
|
|
outline->SetShape( path );
|
|
path->SetAperture( scale( graphic->GetWidth() ) );
|
|
path->SetLayerId( "signal" );
|
|
path->AppendPoint( mapPt( graphic->GetStart0() ) );
|
|
path->AppendPoint( mapPt( graphic->GetEnd0() ) );
|
|
break;
|
|
|
|
case S_CIRCLE:
|
|
{
|
|
// this is best done by 4 QARC's but freerouter does not yet support QARCs.
|
|
// for now, support by using line segments.
|
|
|
|
outline = new SHAPE( image, T_outline );
|
|
|
|
image->Append( outline );
|
|
path = new PATH( outline );
|
|
|
|
outline->SetShape( path );
|
|
path->SetAperture( scale( graphic->GetWidth() ) );
|
|
path->SetLayerId( "signal" );
|
|
|
|
// Do the math using KiCad units, that way we stay out of the
|
|
// scientific notation range of floating point numbers in the
|
|
// DSN file. We do not parse scientific notation in our own
|
|
// lexer/beautifier, and the spec is not clear that this is
|
|
// required. Fixed point floats are all that should be needed.
|
|
|
|
double radius = GetLineLength( graphic->GetStart(), graphic->GetEnd() );
|
|
|
|
const int SEG_PER_CIRCLE = 36; // seg count to approximate circle by line segments
|
|
|
|
for( int ii = 0; ii < SEG_PER_CIRCLE; ++ii )
|
|
{
|
|
double radians = 2*M_PI / SEG_PER_CIRCLE * ii;
|
|
wxPoint point( KiROUND( radius * cos( radians ) ),
|
|
KiROUND( radius * sin( radians ) ) );
|
|
|
|
point += graphic->m_Start0; // an offset
|
|
|
|
path->AppendPoint( mapPt( point ) );
|
|
}
|
|
// The shape must be closed
|
|
wxPoint point( radius , 0 );
|
|
point += graphic->m_Start0;
|
|
path->AppendPoint( mapPt( point ) );
|
|
}
|
|
break;
|
|
|
|
case S_RECT:
|
|
case S_ARC:
|
|
default:
|
|
DBG( printf( "makeIMAGE(): unsupported shape %s\n",
|
|
TO_UTF8( BOARD_ITEM::ShowShape( graphic->GetShape() ) ) ); )
|
|
continue;
|
|
}
|
|
}
|
|
|
|
#endif
|
|
|
|
return image;
|
|
}
|
|
|
|
|
|
PADSTACK* SPECCTRA_DB::makeVia( int aCopperDiameter, int aDrillDiameter,
|
|
int aTopLayer, int aBotLayer )
|
|
{
|
|
char name[48];
|
|
PADSTACK* padstack = new PADSTACK();
|
|
double dsnDiameter = scale( aCopperDiameter );
|
|
|
|
for( int layer=aTopLayer; layer<=aBotLayer; ++layer )
|
|
{
|
|
SHAPE* shape = new SHAPE( padstack );
|
|
|
|
padstack->Append( shape );
|
|
|
|
CIRCLE* circle = new CIRCLE( shape );
|
|
|
|
shape->SetShape( circle );
|
|
|
|
circle->SetDiameter( dsnDiameter );
|
|
circle->SetLayerId( layerIds[layer].c_str() );
|
|
}
|
|
|
|
snprintf( name, sizeof(name), "Via[%d-%d]_%.6g:%.6g_um",
|
|
aTopLayer, aBotLayer, dsnDiameter,
|
|
// encode the drill value into the name for later import
|
|
IU2um( aDrillDiameter )
|
|
);
|
|
|
|
name[ sizeof(name) - 1 ] = 0;
|
|
padstack->SetPadstackId( name );
|
|
|
|
return padstack;
|
|
}
|
|
|
|
|
|
PADSTACK* SPECCTRA_DB::makeVia( const ::VIA* aVia )
|
|
{
|
|
PCB_LAYER_ID topLayerNum;
|
|
PCB_LAYER_ID botLayerNum;
|
|
|
|
aVia->LayerPair( &topLayerNum, &botLayerNum );
|
|
|
|
int topLayer = kicadLayer2pcb[topLayerNum];
|
|
int botLayer = kicadLayer2pcb[botLayerNum];
|
|
|
|
if( topLayer > botLayer )
|
|
std::swap( topLayer, botLayer );
|
|
|
|
return makeVia( aVia->GetWidth(), aVia->GetDrillValue(), topLayer, botLayer );
|
|
}
|
|
|
|
|
|
void SPECCTRA_DB::fillBOUNDARY( BOARD* aBoard, BOUNDARY* boundary )
|
|
{
|
|
wxString errMessage;
|
|
SHAPE_POLY_SET outlines;
|
|
|
|
aBoard->GetBoardPolygonOutlines( outlines, &errMessage );
|
|
|
|
for( int cnt = 0; cnt < outlines.OutlineCount(); cnt++ ) // Should be one outline
|
|
{
|
|
PATH* path = new PATH( boundary );
|
|
boundary->paths.push_back( path );
|
|
path->layer_id = "pcb";
|
|
|
|
SHAPE_LINE_CHAIN& outline = outlines.Outline( cnt );
|
|
|
|
for( int ii = 0; ii < outline.PointCount(); ii++ )
|
|
{
|
|
wxPoint pos( outline.Point( ii ).x, outline.Point( ii ).y );
|
|
path->AppendPoint( mapPt( pos ) );
|
|
}
|
|
|
|
// Close polygon:
|
|
wxPoint pos0( outline.Point( 0 ).x, outline.Point( 0 ).y );
|
|
path->AppendPoint( mapPt( pos0 ) );
|
|
|
|
// Generate holes as keepout:
|
|
for( int ii = 0; ii < outlines.HoleCount( cnt ); ii++ )
|
|
{
|
|
// emit a signal layers keepout for every interior polygon left...
|
|
KEEPOUT* keepout = new KEEPOUT( NULL, T_keepout );
|
|
PATH* poly_ko = new PATH( NULL, T_polygon );
|
|
|
|
keepout->SetShape( poly_ko );
|
|
poly_ko->SetLayerId( "signal" );
|
|
pcb->structure->keepouts.push_back( keepout );
|
|
|
|
SHAPE_LINE_CHAIN& hole = outlines.Hole( cnt, ii );
|
|
|
|
for( int jj = 0; jj < hole.PointCount(); jj++ )
|
|
{
|
|
wxPoint pos( hole.Point( jj ).x, hole.Point( jj ).y );
|
|
poly_ko->AppendPoint( mapPt( pos ) );
|
|
}
|
|
|
|
// Close polygon:
|
|
wxPoint pos( hole.Point( 0 ).x, hole.Point( 0 ).y );
|
|
poly_ko->AppendPoint( mapPt( pos ) );
|
|
}
|
|
}
|
|
|
|
if( !errMessage.IsEmpty() )
|
|
wxLogMessage( errMessage );
|
|
}
|
|
|
|
|
|
typedef std::set<std::string> STRINGSET;
|
|
typedef std::pair<STRINGSET::iterator, bool> STRINGSET_PAIR;
|
|
|
|
|
|
void SPECCTRA_DB::FromBOARD( BOARD* aBoard )
|
|
{
|
|
PCB_TYPE_COLLECTOR items;
|
|
|
|
static const KICAD_T scanMODULEs[] = { PCB_MODULE_T, EOT };
|
|
|
|
// Not all boards are exportable. Check that all reference Ids are unique.
|
|
// Unless they are unique, we cannot import the session file which comes
|
|
// back to us later from the router.
|
|
{
|
|
items.Collect( aBoard, scanMODULEs );
|
|
|
|
STRINGSET refs; // holds module reference designators
|
|
|
|
for( int i=0; i<items.GetCount(); ++i )
|
|
{
|
|
MODULE* module = (MODULE*) items[i];
|
|
|
|
if( module->GetReference() == wxEmptyString )
|
|
{
|
|
THROW_IO_ERROR( wxString::Format( _( "Symbol with value of \"%s\" has empty reference id." ),
|
|
GetChars( module->GetValue() ) ) );
|
|
}
|
|
|
|
// if we cannot insert OK, that means the reference has been seen before.
|
|
STRINGSET_PAIR refpair = refs.insert( TO_UTF8( module->GetReference() ) );
|
|
if( !refpair.second ) // insert failed
|
|
{
|
|
THROW_IO_ERROR( wxString::Format( _( "Multiple symbols have identical reference IDs of \"%s\"." ),
|
|
GetChars( module->GetReference() ) ) );
|
|
}
|
|
}
|
|
}
|
|
|
|
if( !pcb )
|
|
pcb = SPECCTRA_DB::MakePCB();
|
|
|
|
//-----<layer_descriptor>-----------------------------------------------
|
|
{
|
|
// specctra wants top physical layer first, then going down to the
|
|
// bottom most physical layer in physical sequence.
|
|
// @question : why does KiCad not display layers in that order?
|
|
|
|
buildLayerMaps( aBoard );
|
|
|
|
int layerCount = aBoard->GetCopperLayerCount();
|
|
|
|
for( int pcbNdx=0; pcbNdx<layerCount; ++pcbNdx )
|
|
{
|
|
LAYER* layer = new LAYER( pcb->structure );
|
|
|
|
pcb->structure->layers.push_back( layer );
|
|
|
|
layer->name = layerIds[pcbNdx];
|
|
|
|
DSN_T layerType;
|
|
|
|
switch( aBoard->GetLayerType( pcbLayer2kicad[pcbNdx] ) )
|
|
{
|
|
default:
|
|
case LT_SIGNAL: layerType = T_signal; break;
|
|
case LT_POWER: layerType = T_power; break;
|
|
|
|
#if 1 // Freerouter does not support type "mixed", only signal and power.
|
|
// Remap "mixed" to "signal".
|
|
case LT_MIXED: layerType = T_signal; break;
|
|
#else
|
|
case LT_MIXED: layerType = T_mixed; break;
|
|
#endif
|
|
case LT_JUMPER: layerType = T_jumper; break;
|
|
}
|
|
|
|
layer->layer_type = layerType;
|
|
|
|
layer->properties.push_back( PROPERTY() );
|
|
PROPERTY* property = &layer->properties.back();
|
|
property->name = "index";
|
|
char temp[32];
|
|
sprintf( temp, "%d", pcbNdx );
|
|
property->value = temp;
|
|
}
|
|
}
|
|
|
|
// a space in a quoted token is NOT a terminator, true establishes this.
|
|
pcb->parser->space_in_quoted_tokens = true;
|
|
|
|
//-----<unit_descriptor> & <resolution_descriptor>--------------------
|
|
{
|
|
// tell freerouter to use "tenths of micrometers",
|
|
// which is 100 nm resolution. Possibly more resolution is possible
|
|
// in freerouter, but it would need testing.
|
|
|
|
pcb->unit->units = T_um;
|
|
pcb->resolution->units = T_um;
|
|
pcb->resolution->value = 10; // tenths of a um
|
|
// pcb->resolution->value = 1000; // "thousandths of a um" (i.e. "nm")
|
|
}
|
|
|
|
//-----<boundary_descriptor>------------------------------------------
|
|
{
|
|
// Because fillBOUNDARY() can throw an exception, we link in an
|
|
// empty boundary so the BOUNDARY does not get lost in the event of
|
|
// of an exception.
|
|
BOUNDARY* boundary = new BOUNDARY( 0 );
|
|
|
|
pcb->structure->SetBOUNDARY( boundary );
|
|
fillBOUNDARY( aBoard, boundary );
|
|
}
|
|
|
|
|
|
//-----<rules>--------------------------------------------------------
|
|
{
|
|
char rule[80];
|
|
NETCLASSPTR defaultClass = aBoard->GetDesignSettings().GetDefault();
|
|
|
|
int defaultTrackWidth = defaultClass->GetTrackWidth();
|
|
int defaultClearance = defaultClass->GetClearance();
|
|
|
|
double clearance = scale( defaultClearance );
|
|
|
|
STRINGS& rules = pcb->structure->rules->rules;
|
|
|
|
sprintf( rule, "(width %.6g)", scale( defaultTrackWidth ) );
|
|
rules.push_back( rule );
|
|
|
|
sprintf( rule, "(clearance %.6g)", clearance + safetyMargin );
|
|
rules.push_back( rule );
|
|
|
|
// On a high density board (a board with 4 mil tracks, 4 mil spacing)
|
|
// a typical solder mask clearance will be 2-3 mils.
|
|
// This exposes 2 to 3 mils of bare board around each pad, and would
|
|
// leave only 1 to 2 mils of solder mask between the solder mask's boundary
|
|
// to the edge of any trace within "clearance" of the pad. So we need at least
|
|
// 2 mils *extra* clearance for traces which would come near a pad on
|
|
// a different net. So if the baseline trace to trace clearance was say 4 mils, then
|
|
// the SMD to trace clearance should be at least 6 mils.
|
|
double default_smd = clearance + safetyMargin;
|
|
|
|
if( default_smd <= 6.0 )
|
|
default_smd = 6.0;
|
|
|
|
sprintf( rule, "(clearance %.6g (type default_smd))", default_smd );
|
|
|
|
rules.push_back( rule );
|
|
|
|
/* see: http://www.freerouting.net/usren/viewtopic.php?f=5&t=339#p474
|
|
sprintf( rule, "(clearance %.6g (type pad_to_turn_gap))", clearance + safetyMargin );
|
|
rules.push_back( rule );
|
|
|
|
sprintf( rule, "(clearance %.6g (type smd_to_turn_gap))", clearance + safetyMargin );
|
|
rules.push_back( rule );
|
|
|
|
sprintf( rule, "(clearance %.6g (type via_via))", clearance + safetyMargin );
|
|
rules.push_back( rule );
|
|
|
|
sprintf( rule, "(clearance %.6g (type via_smd))", clearance + safetyMargin );
|
|
rules.push_back( rule );
|
|
|
|
sprintf( rule, "(clearance %.6g (type via_pin))", clearance + safetyMargin );
|
|
rules.push_back( rule );
|
|
|
|
sprintf( rule, "(clearance %.6g (type pin_pin))", clearance + safetyMargin );
|
|
rules.push_back( rule );
|
|
|
|
sprintf( rule, "(clearance %.6g (type smd_pin))", clearance + safetyMargin );
|
|
rules.push_back( rule );
|
|
*/
|
|
|
|
// Pad to pad spacing on a single SMT part can be closer than our
|
|
// clearance, we don't want freerouter complaining about that, so
|
|
// output a significantly smaller pad to pad clearance to freerouter.
|
|
clearance = scale( defaultClearance ) / 4;
|
|
|
|
sprintf( rule, "(clearance %.6g (type smd_smd))", clearance );
|
|
rules.push_back( rule );
|
|
}
|
|
|
|
|
|
//-----<zone containers (not keepout areas) become planes>--------------------------------
|
|
// Note: only zones are output here, keepout areas be be created later
|
|
{
|
|
int netlessZones = 0;
|
|
|
|
static const KICAD_T scanZONEs[] = { PCB_ZONE_AREA_T, EOT };
|
|
items.Collect( aBoard, scanZONEs );
|
|
|
|
for( int i = 0; i<items.GetCount(); ++i )
|
|
{
|
|
ZONE_CONTAINER* item = (ZONE_CONTAINER*) items[i];
|
|
|
|
if( item->GetIsKeepout() )
|
|
continue;
|
|
|
|
// Currently, we export only copper layers
|
|
if( ! IsCopperLayer( item->GetLayer() ) )
|
|
continue;
|
|
|
|
COPPER_PLANE* plane = new COPPER_PLANE( pcb->structure );
|
|
|
|
pcb->structure->planes.push_back( plane );
|
|
|
|
PATH* mainPolygon = new PATH( plane, T_polygon );
|
|
|
|
plane->SetShape( mainPolygon );
|
|
|
|
plane->name = TO_UTF8( item->GetNetname() );
|
|
|
|
if( plane->name.size() == 0 )
|
|
{
|
|
char name[32];
|
|
|
|
// This is one of those no connection zones, netcode=0, and it has no name.
|
|
// Create a unique, bogus netname.
|
|
NET* no_net = new NET( pcb->network );
|
|
|
|
sprintf( name, "@:no_net_%d", netlessZones++ );
|
|
no_net->net_id = name;
|
|
|
|
// add the bogus net name to network->nets.
|
|
pcb->network->nets.push_back( no_net );
|
|
|
|
// use the bogus net name in the netless zone.
|
|
plane->name = no_net->net_id;
|
|
}
|
|
|
|
mainPolygon->layer_id = layerIds[ kicadLayer2pcb[ item->GetLayer() ] ];
|
|
|
|
// Handle the main outlines
|
|
SHAPE_POLY_SET::ITERATOR iterator;
|
|
wxPoint startpoint;
|
|
bool is_first_point = true;
|
|
|
|
for( iterator = item->IterateWithHoles(); iterator; iterator++ )
|
|
{
|
|
wxPoint point( iterator->x, iterator->y );
|
|
|
|
if( is_first_point )
|
|
{
|
|
startpoint = point;
|
|
is_first_point = false;
|
|
}
|
|
|
|
mainPolygon->AppendPoint( mapPt( point ) );
|
|
|
|
// this was the end of the main polygon
|
|
if( iterator.IsEndContour() )
|
|
{
|
|
// Close polygon
|
|
mainPolygon->AppendPoint( mapPt( startpoint ) );
|
|
break;
|
|
}
|
|
}
|
|
|
|
WINDOW* window = 0;
|
|
PATH* cutout = 0;
|
|
|
|
bool isStartContour = true;
|
|
|
|
// handle the cutouts
|
|
for( iterator++; iterator; iterator++ )
|
|
{
|
|
if( isStartContour )
|
|
{
|
|
is_first_point = true;
|
|
window = new WINDOW( plane );
|
|
|
|
plane->AddWindow( window );
|
|
|
|
cutout = new PATH( window, T_polygon );
|
|
|
|
window->SetShape( cutout );
|
|
|
|
cutout->layer_id = layerIds[ kicadLayer2pcb[ item->GetLayer() ] ];
|
|
}
|
|
|
|
// If the point in this iteration is the last of the contour, the next iteration
|
|
// will start with a new contour.
|
|
isStartContour = iterator.IsEndContour();
|
|
|
|
wxASSERT( window );
|
|
wxASSERT( cutout );
|
|
|
|
wxPoint point(iterator->x, iterator->y );
|
|
|
|
if( is_first_point )
|
|
{
|
|
startpoint = point;
|
|
is_first_point = false;
|
|
}
|
|
|
|
cutout->AppendPoint( mapPt(point) );
|
|
|
|
// Close the polygon
|
|
if( iterator.IsEndContour() )
|
|
cutout->AppendPoint( mapPt( startpoint ) );
|
|
}
|
|
}
|
|
}
|
|
|
|
//-----<zone containers flagged keepout areas become keepout>--------------------------------
|
|
{
|
|
static const KICAD_T scanZONEs[] = { PCB_ZONE_AREA_T, EOT };
|
|
items.Collect( aBoard, scanZONEs );
|
|
|
|
for( int i=0; i<items.GetCount(); ++i )
|
|
{
|
|
ZONE_CONTAINER* item = (ZONE_CONTAINER*) items[i];
|
|
|
|
if( ! item->GetIsKeepout() )
|
|
continue;
|
|
|
|
// keepout areas have a type. types are
|
|
// T_place_keepout, T_via_keepout, T_wire_keepout,
|
|
// T_bend_keepout, T_elongate_keepout, T_keepout.
|
|
// Pcbnew knows only T_keepout, T_via_keepout and T_wire_keepout
|
|
DSN_T keepout_type;
|
|
|
|
if( item->GetDoNotAllowVias() && item->GetDoNotAllowTracks() )
|
|
keepout_type = T_keepout;
|
|
else if( item->GetDoNotAllowVias() )
|
|
keepout_type = T_via_keepout;
|
|
else if( item->GetDoNotAllowTracks() )
|
|
keepout_type = T_wire_keepout;
|
|
else
|
|
keepout_type = T_keepout;
|
|
|
|
// Now, build keepout polygon on each copper layer where the item
|
|
// keepout is living (keepout zones can live on many copper layers)
|
|
const int copperCount = aBoard->GetCopperLayerCount();
|
|
|
|
for( int layer = 0; layer < copperCount; layer++ )
|
|
{
|
|
if( layer == copperCount-1)
|
|
layer = B_Cu;
|
|
|
|
if( !item->IsOnLayer( PCB_LAYER_ID( layer ) ) )
|
|
continue;
|
|
|
|
KEEPOUT* keepout = new KEEPOUT( pcb->structure, keepout_type );
|
|
pcb->structure->keepouts.push_back( keepout );
|
|
|
|
PATH* mainPolygon = new PATH( keepout, T_polygon );
|
|
keepout->SetShape( mainPolygon );
|
|
|
|
mainPolygon->layer_id = layerIds[ kicadLayer2pcb[ layer ] ];
|
|
|
|
// Handle the main outlines
|
|
SHAPE_POLY_SET::ITERATOR iterator;
|
|
bool is_first_point = true;
|
|
wxPoint startpoint;
|
|
|
|
for( iterator = item->IterateWithHoles(); iterator; iterator++ )
|
|
{
|
|
wxPoint point( iterator->x, iterator->y );
|
|
|
|
if( is_first_point )
|
|
{
|
|
startpoint = point;
|
|
is_first_point = false;
|
|
}
|
|
|
|
mainPolygon->AppendPoint( mapPt(point) );
|
|
|
|
// this was the end of the main polygon
|
|
if( iterator.IsEndContour() )
|
|
{
|
|
mainPolygon->AppendPoint( mapPt( startpoint ) );
|
|
break;
|
|
}
|
|
}
|
|
|
|
WINDOW* window = nullptr;
|
|
PATH* cutout = nullptr;
|
|
|
|
bool isStartContour = true;
|
|
|
|
// handle the cutouts
|
|
for( iterator++; iterator; iterator++ )
|
|
{
|
|
if( isStartContour )
|
|
{
|
|
is_first_point = true;
|
|
window = new WINDOW( keepout );
|
|
keepout->AddWindow( window );
|
|
|
|
cutout = new PATH( window, T_polygon );
|
|
|
|
window->SetShape( cutout );
|
|
|
|
cutout->layer_id = layerIds[ kicadLayer2pcb[ item->GetLayer() ] ];
|
|
}
|
|
|
|
isStartContour = iterator.IsEndContour();
|
|
|
|
wxASSERT( window );
|
|
wxASSERT( cutout );
|
|
|
|
wxPoint point(iterator->x, iterator->y );
|
|
|
|
if( is_first_point )
|
|
{
|
|
startpoint = point;
|
|
is_first_point = false;
|
|
}
|
|
|
|
cutout->AppendPoint( mapPt(point) );
|
|
|
|
// Close the polygon
|
|
if( iterator.IsEndContour() )
|
|
cutout->AppendPoint( mapPt( startpoint ) );
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
//-----<build the images, components, and netlist>-----------------------
|
|
{
|
|
PIN_REF empty( pcb->network );
|
|
|
|
std::string componentId;
|
|
|
|
// find the highest numbered netCode within the board.
|
|
int highestNetCode = aBoard->GetNetCount() - 1;
|
|
|
|
deleteNETs();
|
|
|
|
// expand the net vector to highestNetCode+1, setting empty to NULL
|
|
nets.resize( highestNetCode + 1, NULL );
|
|
|
|
// skip netcode = 0
|
|
for( unsigned i = 1; i<nets.size(); ++i )
|
|
nets[i] = new NET( pcb->network );
|
|
|
|
for( unsigned ii = 0; ii < aBoard->GetNetCount(); ii++ )
|
|
{
|
|
NETINFO_ITEM* net = aBoard->FindNet( ii );
|
|
int netcode = net->GetNet();
|
|
|
|
if( netcode > 0 )
|
|
nets[ netcode ]->net_id = TO_UTF8( net->GetNetname() );
|
|
}
|
|
|
|
items.Collect( aBoard, scanMODULEs );
|
|
|
|
padstackset.clear();
|
|
|
|
for( int m = 0; m<items.GetCount(); ++m )
|
|
{
|
|
MODULE* module = (MODULE*) items[m];
|
|
|
|
IMAGE* image = makeIMAGE( aBoard, module );
|
|
|
|
componentId = TO_UTF8( module->GetReference() );
|
|
|
|
// create a net list entry for all the actual pins in the image
|
|
// for the current module. location of this code is critical
|
|
// because we fabricated some pin names to ensure unique-ness
|
|
// of pin names within a module, do not move this code because
|
|
// the life of this 'IMAGE* image' is not necessarily long. The
|
|
// exported netlist will have some fabricated pin names in it.
|
|
// If you don't like fabricated pin names, then make sure all pads
|
|
// within your MODULEs are uniquely named!
|
|
for( unsigned p = 0; p<image->pins.size(); ++p )
|
|
{
|
|
PIN* pin = &image->pins[p];
|
|
|
|
int netcode = pin->kiNetCode;
|
|
|
|
if( netcode > 0 )
|
|
{
|
|
NET* net = nets[netcode];
|
|
|
|
net->pins.push_back( empty );
|
|
|
|
PIN_REF& pin_ref = net->pins.back();
|
|
|
|
pin_ref.component_id = componentId;
|
|
pin_ref.pin_id = pin->pin_id;
|
|
}
|
|
}
|
|
|
|
|
|
IMAGE* registered = pcb->library->LookupIMAGE( image );
|
|
|
|
if( registered != image )
|
|
{
|
|
// If our new 'image' is not a unique IMAGE, delete it.
|
|
// and use the registered one, known as 'image' after this.
|
|
delete image;
|
|
image = registered;
|
|
}
|
|
|
|
COMPONENT* comp = pcb->placement->LookupCOMPONENT( image->GetImageId() );
|
|
|
|
PLACE* place = new PLACE( comp );
|
|
|
|
comp->places.push_back( place );
|
|
|
|
place->SetRotation( module->GetOrientationDegrees() );
|
|
place->SetVertex( mapPt( module->GetPosition() ) );
|
|
place->component_id = componentId;
|
|
place->part_number = TO_UTF8( module->GetValue() );
|
|
|
|
// module is flipped from bottom side, set side to T_back
|
|
if( module->GetFlag() )
|
|
{
|
|
double angle = 180.0 - module->GetOrientationDegrees();
|
|
NORMALIZE_ANGLE_DEGREES_POS( angle );
|
|
place->SetRotation( angle );
|
|
|
|
place->side = T_back;
|
|
}
|
|
}
|
|
|
|
// copy the SPECCTRA_DB::padstackset to the LIBRARY. Since we are
|
|
// removing, do not increment the iterator
|
|
for( PADSTACKSET::iterator i = padstackset.begin(); i!=padstackset.end();
|
|
i = padstackset.begin() )
|
|
{
|
|
PADSTACKSET::auto_type ps = padstackset.release( i );
|
|
PADSTACK* padstack = ps.release();
|
|
|
|
pcb->library->AddPadstack( padstack );
|
|
}
|
|
|
|
// copy our SPECCTRA_DB::nets to the pcb->network
|
|
for( unsigned n = 1; n<nets.size(); ++n )
|
|
{
|
|
NET* net = nets[n];
|
|
|
|
if( net->pins.size() )
|
|
{
|
|
// give ownership to pcb->network
|
|
pcb->network->nets.push_back( net );
|
|
nets[n] = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
//-----< output vias used in netclasses >-----------------------------------
|
|
{
|
|
NETCLASSES& nclasses = aBoard->GetDesignSettings().m_NetClasses;
|
|
|
|
// Assume the netclass vias are all the same kind of thru, blind, or buried vias.
|
|
// This is in lieu of either having each netclass via have its own layer pair in
|
|
// the netclass dialog, or such control in the specctra export dialog.
|
|
|
|
|
|
// if( aBoard->GetDesignSettings().m_CurrentViaType == VIA_THROUGH )
|
|
{
|
|
m_top_via_layer = 0; // first specctra cu layer is number zero.
|
|
m_bot_via_layer = aBoard->GetCopperLayerCount()-1;
|
|
}
|
|
/*
|
|
else
|
|
{
|
|
// again, should be in the BOARD:
|
|
topLayer = kicadLayer2pcb[ GetScreen()->m_Route_Layer_TOP ];
|
|
botLayer = kicadLayer2pcb[ GetScreen()->m_Route_Layer_BOTTOM ];
|
|
}
|
|
*/
|
|
|
|
// Add the via from the Default netclass first. The via container
|
|
// in pcb->library preserves the sequence of addition.
|
|
|
|
NETCLASSPTR netclass = nclasses.GetDefault();
|
|
|
|
PADSTACK* via = makeVia( netclass->GetViaDiameter(), netclass->GetViaDrill(),
|
|
m_top_via_layer, m_bot_via_layer );
|
|
|
|
// we AppendVia() this first one, there is no way it can be a duplicate,
|
|
// the pcb->library via container is empty at this point. After this,
|
|
// we'll have to use LookupVia().
|
|
wxASSERT( pcb->library->vias.size() == 0 );
|
|
pcb->library->AppendVia( via );
|
|
|
|
#if 0
|
|
// I've seen no way to make stock vias useable by freerouter. Also the
|
|
// zero based diameter was leading to duplicates in the LookupVia() function.
|
|
// User should use netclass based vias when going to freerouter.
|
|
|
|
// Output the stock vias, but preserve uniqueness in the via container by
|
|
// using LookupVia().
|
|
for( unsigned i = 0; i < aBoard->m_ViasDimensionsList.size(); ++i )
|
|
{
|
|
int viaSize = aBoard->m_ViasDimensionsList[i].m_Diameter;
|
|
int viaDrill = aBoard->m_ViasDimensionsList[i].m_Drill;
|
|
|
|
via = makeVia( viaSize, viaDrill,
|
|
m_top_via_layer, m_bot_via_layer );
|
|
|
|
// maybe add 'via' to the library, but only if unique.
|
|
PADSTACK* registered = pcb->library->LookupVia( via );
|
|
|
|
if( registered != via )
|
|
delete via;
|
|
}
|
|
#endif
|
|
|
|
// set the "spare via" index at the start of the
|
|
// pcb->library->spareViaIndex = pcb->library->vias.size();
|
|
|
|
// output the non-Default netclass vias
|
|
for( NETCLASSES::iterator nc = nclasses.begin(); nc != nclasses.end(); ++nc )
|
|
{
|
|
netclass = nc->second;
|
|
|
|
via = makeVia( netclass->GetViaDiameter(), netclass->GetViaDrill(),
|
|
m_top_via_layer, m_bot_via_layer );
|
|
|
|
// maybe add 'via' to the library, but only if unique.
|
|
PADSTACK* registered = pcb->library->LookupVia( via );
|
|
|
|
if( registered != via )
|
|
delete via;
|
|
}
|
|
}
|
|
|
|
|
|
#if 1 // do existing wires and vias
|
|
|
|
//-----<create the wires from tracks>-----------------------------------
|
|
{
|
|
// export all of them for now, later we'll decide what controls we need
|
|
// on this.
|
|
static const KICAD_T scanTRACKs[] = { PCB_TRACE_T, EOT };
|
|
|
|
items.Collect( aBoard, scanTRACKs );
|
|
|
|
std::string netname;
|
|
WIRING* wiring = pcb->wiring;
|
|
PATH* path = 0;
|
|
|
|
int old_netcode = -1;
|
|
int old_width = -1;
|
|
LAYER_NUM old_layer = UNDEFINED_LAYER;
|
|
|
|
for( int i=0; i<items.GetCount(); ++i )
|
|
{
|
|
TRACK* track = (TRACK*) items[i];
|
|
|
|
int netcode = track->GetNetCode();
|
|
|
|
if( netcode == 0 )
|
|
continue;
|
|
|
|
if( old_netcode != netcode ||
|
|
old_width != track->GetWidth() ||
|
|
old_layer != track->GetLayer() ||
|
|
(path && path->points.back() != mapPt(track->GetStart()) )
|
|
)
|
|
{
|
|
old_width = track->GetWidth();
|
|
old_layer = track->GetLayer();
|
|
|
|
if( old_netcode != netcode )
|
|
{
|
|
old_netcode = netcode;
|
|
NETINFO_ITEM* net = aBoard->FindNet( netcode );
|
|
wxASSERT( net );
|
|
netname = TO_UTF8( net->GetNetname() );
|
|
}
|
|
|
|
WIRE* wire = new WIRE( wiring );
|
|
|
|
wiring->wires.push_back( wire );
|
|
wire->net_id = netname;
|
|
|
|
wire->wire_type = T_protect; // @todo, this should be configurable
|
|
|
|
LAYER_NUM kiLayer = track->GetLayer();
|
|
int pcbLayer = kicadLayer2pcb[kiLayer];
|
|
|
|
path = new PATH( wire );
|
|
|
|
wire->SetShape( path );
|
|
|
|
path->layer_id = layerIds[pcbLayer];
|
|
path->aperture_width = scale( old_width );
|
|
|
|
path->AppendPoint( mapPt( track->GetStart() ) );
|
|
}
|
|
|
|
if( path ) // Should not occur
|
|
path->AppendPoint( mapPt( track->GetEnd() ) );
|
|
}
|
|
}
|
|
|
|
|
|
//-----<export the existing real BOARD instantiated vias>-----------------
|
|
{
|
|
// Export all vias, once per unique size and drill diameter combo.
|
|
static const KICAD_T scanVIAs[] = { PCB_VIA_T, EOT };
|
|
|
|
items.Collect( aBoard, scanVIAs );
|
|
|
|
for( int i = 0; i<items.GetCount(); ++i )
|
|
{
|
|
::VIA* via = (::VIA*) items[i];
|
|
wxASSERT( via->Type() == PCB_VIA_T );
|
|
|
|
int netcode = via->GetNetCode();
|
|
|
|
if( netcode == 0 )
|
|
continue;
|
|
|
|
PADSTACK* padstack = makeVia( via );
|
|
PADSTACK* registered = pcb->library->LookupVia( padstack );
|
|
|
|
// if the one looked up is not our padstack, then delete our padstack
|
|
// since it was a duplicate of one already registered.
|
|
if( padstack != registered )
|
|
{
|
|
delete padstack;
|
|
}
|
|
|
|
WIRE_VIA* dsnVia = new WIRE_VIA( pcb->wiring );
|
|
|
|
pcb->wiring->wire_vias.push_back( dsnVia );
|
|
|
|
dsnVia->padstack_id = registered->padstack_id;
|
|
dsnVia->vertexes.push_back( mapPt( via->GetPosition() ) );
|
|
|
|
NETINFO_ITEM* net = aBoard->FindNet( netcode );
|
|
wxASSERT( net );
|
|
|
|
dsnVia->net_id = TO_UTF8( net->GetNetname() );
|
|
|
|
dsnVia->via_type = T_protect; // @todo, this should be configurable
|
|
}
|
|
}
|
|
|
|
#endif // do existing wires and vias
|
|
|
|
//-----<via_descriptor>-------------------------------------------------
|
|
{
|
|
// The pcb->library will output <padstack_descriptors> which is a combined
|
|
// list of part padstacks and via padstacks. specctra dsn uses the
|
|
// <via_descriptors> to say which of those padstacks are vias.
|
|
|
|
// Output the vias in the padstack list here, by name only. This must
|
|
// be done after exporting existing vias as WIRE_VIAs.
|
|
VIA* vias = pcb->structure->via;
|
|
|
|
for( unsigned viaNdx = 0; viaNdx < pcb->library->vias.size(); ++viaNdx )
|
|
{
|
|
vias->AppendVia( pcb->library->vias[viaNdx].padstack_id.c_str() );
|
|
}
|
|
}
|
|
|
|
|
|
//-----<output NETCLASSs>----------------------------------------------------
|
|
NETCLASSES& nclasses = aBoard->GetDesignSettings().m_NetClasses;
|
|
|
|
exportNETCLASS( nclasses.GetDefault(), aBoard );
|
|
|
|
for( NETCLASSES::iterator nc = nclasses.begin(); nc != nclasses.end(); ++nc )
|
|
{
|
|
NETCLASSPTR netclass = nc->second;
|
|
exportNETCLASS( netclass, aBoard );
|
|
}
|
|
}
|
|
|
|
|
|
void SPECCTRA_DB::exportNETCLASS( const NETCLASSPTR& aNetClass, BOARD* aBoard )
|
|
{
|
|
/* From page 11 of specctra spec:
|
|
*
|
|
* Routing and Placement Rule Hierarchies
|
|
*
|
|
* Routing and placement rules can be defined at multiple levels of design
|
|
* specification. When a routing or placement rule is defined for an object at
|
|
* multiple levels, a predefined routing or placement precedence order
|
|
* automatically determines which rule to apply to the object. The routing rule
|
|
* precedence order is
|
|
*
|
|
* pcb < layer < class < class layer < group_set < group_set layer < net <
|
|
* net layer < group < group layer < fromto < fromto layer < class_class <
|
|
* class_class layer < padstack < region < class region < net region <
|
|
* class_class region
|
|
*
|
|
* A pcb rule (global rule for the PCB design) has the lowest precedence in the
|
|
* hierarchy. A class-to-class region rule has the highest precedence. Rules
|
|
* set at one level of the hierarchy override conflicting rules set at lower
|
|
* levels. The placement rule precedence order is
|
|
*
|
|
* pcb < image_set < image < component < super cluster < room <
|
|
* room_image_set < family_family < image_image
|
|
*
|
|
* A pcb rule (global rule for the PCB design) has the lowest precedence in the
|
|
* hierarchy. An image-to-image rule has the highest precedence. Rules set at
|
|
* one level of the hierarchy override conflicting rules set at lower levels.
|
|
*/
|
|
|
|
char text[256];
|
|
|
|
CLASS* clazz = new CLASS( pcb->network );
|
|
|
|
pcb->network->classes.push_back( clazz );
|
|
|
|
// freerouter creates a class named 'default' anyway, and if we
|
|
// try and use that, we end up with two 'default' via rules so use
|
|
// something else as the name of our default class.
|
|
clazz->class_id = TO_UTF8( aNetClass->GetName() );
|
|
|
|
for( NETCLASS::iterator net = aNetClass->begin(); net != aNetClass->end(); ++net )
|
|
clazz->net_ids.push_back( TO_UTF8( *net ) );
|
|
|
|
clazz->rules = new RULE( clazz, T_rule );
|
|
|
|
// output the track width.
|
|
int trackWidth = aNetClass->GetTrackWidth();
|
|
sprintf( text, "(width %.6g)", scale( trackWidth ) );
|
|
clazz->rules->rules.push_back( text );
|
|
|
|
// output the clearance.
|
|
int clearance = aNetClass->GetClearance();
|
|
sprintf( text, "(clearance %.6g)", scale( clearance ) + safetyMargin );
|
|
clazz->rules->rules.push_back( text );
|
|
|
|
if( aNetClass->GetName() == NETCLASS::Default )
|
|
{
|
|
clazz->class_id = "kicad_default";
|
|
}
|
|
|
|
// the easiest way to get the via name is to create a via (which generates
|
|
// the name internal to the PADSTACK), and then grab the name and then
|
|
// delete the via. There are not that many netclasses so
|
|
// this should never become a performance issue.
|
|
|
|
PADSTACK* via = makeVia( aNetClass->GetViaDiameter(), aNetClass->GetViaDrill(),
|
|
m_top_via_layer, m_bot_via_layer );
|
|
|
|
snprintf( text, sizeof(text), "(use_via %s)", via->GetPadstackId().c_str() );
|
|
clazz->circuit.push_back( text );
|
|
|
|
delete via;
|
|
}
|
|
|
|
|
|
void SPECCTRA_DB::FlipMODULEs( BOARD* aBoard )
|
|
{
|
|
for( MODULE* module = aBoard->m_Modules; module; module = module->Next() )
|
|
{
|
|
module->SetFlag( 0 );
|
|
if( module->GetLayer() == B_Cu )
|
|
{
|
|
module->Flip( module->GetPosition() );
|
|
module->SetFlag( 1 );
|
|
}
|
|
}
|
|
|
|
modulesAreFlipped = true;
|
|
}
|
|
|
|
|
|
void SPECCTRA_DB::RevertMODULEs( BOARD* aBoard )
|
|
{
|
|
if( !modulesAreFlipped )
|
|
return;
|
|
|
|
// DSN Images (=KiCad MODULES and pads) must be presented from the
|
|
// top view. Restore those that were flipped.
|
|
for( MODULE* module = aBoard->m_Modules; module; module = module->Next() )
|
|
{
|
|
if( module->GetFlag() )
|
|
{
|
|
module->Flip( module->GetPosition() );
|
|
module->SetFlag( 0 );
|
|
}
|
|
}
|
|
|
|
modulesAreFlipped = false;
|
|
}
|
|
|
|
} // namespace DSN
|