53 lines
1.5 KiB
Plaintext
53 lines
1.5 KiB
Plaintext
(version 1)
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#Clearance for U101
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(rule "U101 clearance"
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(constraint clearance (min 0.127mm))
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(condition "A.insideCourtyard('U101')"))
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#Clearance for U102
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(rule "U102 clearance"
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(constraint clearance (min 0.127mm))
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(condition "A.insideCourtyard('U102')"))
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#Clearance for U201
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(rule "U201 clearance"
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(constraint clearance (min 0.127mm))
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(condition "A.insideCourtyard('U201')"))
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#Clearance for U601
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(rule "U601 clearance"
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(constraint clearance (min 0.127mm))
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(condition "A.insideCourtyard('U601')"))
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#Clearance for J202
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(rule "J202 clearance"
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(constraint clearance (min 0.127mm))
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(condition "A.insideBackCourtyard('J202')"))
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#Clearance for J501
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(rule "J501 clearance"
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(constraint clearance (min 0.127mm))
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(condition "A.insideCourtyard('J501')"))
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#Clearance for TVS diode arrays
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(rule "TVS_Array clearance"
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(constraint clearance (min 0.127mm))
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(condition "A.insideCourtyard('D6*') "))
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#Ignore silkscreen overlap violations in rule area(s) 'interlocking_terminals'
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(rule allow_silk_clearance_violation
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(constraint silk_clearance (min -1mm))
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(condition "A.insideArea('interlocking_terminals')"))
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#Ignore courtyard overlap violations in rule area(s) 'interlocking_terminals'
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#Doesn't seem to work, just exclude the violations for now..
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(rule allow_court_clearance_violation
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(constraint courtyard_clearance (min -2mm))
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(condition "A.insideArea('interlocking_terminals')"))
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#Maintain clearance for outer layer copper pours (else overriden by above)
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(rule "outer_pour clearance"
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(constraint clearance (min 0.4mm))
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(condition "A.Name == 'outer_pour'"))
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