1604 lines
44 KiB
C++
1604 lines
44 KiB
C++
/*******************************************/
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/* class_board.cpp - BOARD class functions */
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/*******************************************/
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#include <limits.h>
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#include "fctsys.h"
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#include "common.h"
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#include "pcbnew.h"
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#include "class_board_design_settings.h"
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#include "colors_selection.h"
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/* This is an odd place for this, but cvpcb won't link if it is
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* in class_board_item.cpp like I first tried it.
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*/
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wxPoint BOARD_ITEM::ZeroOffset( 0, 0 );
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// Current design settings (used also to read configs):
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BOARD_DESIGN_SETTINGS boardDesignSettings;
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/*****************/
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/* Class BOARD: */
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/*****************/
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BOARD::BOARD( EDA_ITEM* parent, PCB_BASE_FRAME* frame ) :
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BOARD_ITEM( (BOARD_ITEM*)parent, TYPE_PCB ),
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m_NetClasses( this )
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{
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m_PcbFrame = frame;
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m_Status_Pcb = 0; // Status word: bit 1 = calculate.
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SetBoardDesignSettings(&boardDesignSettings);
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SetColorsSettings(&g_ColorsSettings);
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m_NbNodes = 0; // Number of connected pads.
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m_NbNoconnect = 0; // Number of unconnected nets.
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m_CurrentZoneContour = NULL; // This ZONE_CONTAINER handle the
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// zone contour currently in
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// progress
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m_NetInfo = new NETINFO_LIST( this ); // handle nets info list (name,
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// design constraints ..
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m_NetInfo->BuildListOfNets(); // prepare pads and nets lists
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// containers.
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for( int layer = 0; layer < NB_COPPER_LAYERS; ++layer )
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{
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m_Layer[layer].m_Name = GetDefaultLayerName( layer );
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m_Layer[layer].m_Type = LT_SIGNAL;
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}
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// Initial parameters for the default NETCLASS come from the global
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// preferences
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// within g_DesignSettings via the NETCLASS() constructor.
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// Should user eventually load a board from a disk file, then these
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// defaults
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// will get overwritten during load.
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m_NetClasses.GetDefault()->SetDescription(
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_( "This is the default net class." ) );
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m_ViaSizeSelector = 0;
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m_TrackWidthSelector = 0;
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// Initialize default values.
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SetCurrentNetClass( m_NetClasses.GetDefault()->GetName() );
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}
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BOARD::~BOARD()
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{
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if( m_PcbFrame->GetScreen() )
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m_PcbFrame->GetScreen()->ClearUndoRedoList();
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while( m_ZoneDescriptorList.size() )
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{
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ZONE_CONTAINER* area_to_remove = m_ZoneDescriptorList[0];
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Delete( area_to_remove );
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}
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m_FullRatsnest.clear();
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m_LocalRatsnest.clear();
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DeleteMARKERs();
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DeleteZONEOutlines();
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delete m_CurrentZoneContour;
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m_CurrentZoneContour = NULL;
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delete m_NetInfo;
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}
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/*
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* Function PushHightLight
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* save current hight light info for later use
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*/
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void BOARD::PushHightLight()
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{
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m_hightLightPrevious = m_hightLight;
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}
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/*
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* Function PopHightLight
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* retrieve a previously saved hight light info
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*/
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void BOARD::PopHightLight()
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{
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m_hightLight = m_hightLightPrevious;
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m_hightLightPrevious.Clear();
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}
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/**
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* Function SetCurrentNetClass
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* Must be called after a netclass selection (or after a netclass parameter
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* change
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* Initialize vias and tracks values displayed in combo boxes of the auxiliary
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* toolbar and some other parameters (netclass name ....)
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* @param aNetClassName = the new netclass name
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* @return true if lists of tracks and vias sizes are modified
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*/
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bool BOARD::SetCurrentNetClass( const wxString& aNetClassName )
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{
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NETCLASS* netClass = m_NetClasses.Find( aNetClassName );
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bool lists_sizes_modified = false;
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// if not found (should not happen) use the default
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if( netClass == NULL )
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netClass = m_NetClasses.GetDefault();
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m_CurrentNetClassName = netClass->GetName();
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// Initialize others values:
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if( m_ViasDimensionsList.size() == 0 )
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{
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VIA_DIMENSION viadim;
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lists_sizes_modified = true;
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m_ViasDimensionsList.push_back( viadim );
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}
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if( m_TrackWidthList.size() == 0 )
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{
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lists_sizes_modified = true;
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m_TrackWidthList.push_back( 0 );
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}
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/* note the m_ViasDimensionsList[0] and m_TrackWidthList[0] values
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* are always the Netclass values
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*/
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if( m_ViasDimensionsList[0].m_Diameter != netClass->GetViaDiameter() )
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lists_sizes_modified = true;
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m_ViasDimensionsList[0].m_Diameter = netClass->GetViaDiameter();
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if( m_TrackWidthList[0] != netClass->GetTrackWidth() )
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lists_sizes_modified = true;
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m_TrackWidthList[0] = netClass->GetTrackWidth();
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if( m_ViaSizeSelector >= m_ViasDimensionsList.size() )
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m_ViaSizeSelector = m_ViasDimensionsList.size();
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if( m_TrackWidthSelector >= m_TrackWidthList.size() )
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m_TrackWidthSelector = m_TrackWidthList.size();
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return lists_sizes_modified;
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}
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/**
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* Function GetBiggestClearanceValue
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* @return the biggest clearance value found in NetClasses list
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*/
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int BOARD::GetBiggestClearanceValue()
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{
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int clearance = m_NetClasses.GetDefault()->GetClearance();
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//Read list of Net Classes
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for( NETCLASSES::const_iterator nc = m_NetClasses.begin();
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nc != m_NetClasses.end();
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nc++ )
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{
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NETCLASS* netclass = nc->second;
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clearance = MAX( clearance, netclass->GetClearance() );
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}
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return clearance;
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}
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/**
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* Function GetCurrentMicroViaSize
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* @return the current micro via size,
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* that is the current netclass value
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*/
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int BOARD::GetCurrentMicroViaSize()
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{
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NETCLASS* netclass = m_NetClasses.Find( m_CurrentNetClassName );
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return netclass->GetuViaDiameter();
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}
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/**
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* Function GetCurrentMicroViaDrill
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* @return the current micro via drill,
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* that is the current netclass value
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*/
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int BOARD::GetCurrentMicroViaDrill()
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{
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NETCLASS* netclass = m_NetClasses.Find( m_CurrentNetClassName );
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return netclass->GetuViaDrill();
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}
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wxString BOARD::GetLayerName( int aLayerIndex ) const
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{
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if( !IsValidLayerIndex( aLayerIndex ) )
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return wxEmptyString;
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// copper layer names are stored in the BOARD.
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if( IsValidCopperLayerIndex( aLayerIndex ) && IsLayerEnabled( aLayerIndex ) )
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{
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// default names were set in BOARD::BOARD() but they may be
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// over-ridden by BOARD::SetLayerName()
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return m_Layer[aLayerIndex].m_Name;
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}
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return GetDefaultLayerName( aLayerIndex );
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}
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wxString BOARD::GetDefaultLayerName( int aLayerNumber )
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{
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const wxChar* txt;
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// These are only default layer names. For PCBNEW, the copper names
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// may be over-ridden in the BOARD (*.brd) file.
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// Use a switch to explicitly show the mapping more clearly
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switch( aLayerNumber )
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{
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case LAYER_N_FRONT: txt = _( "Front" ); break;
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case LAYER_N_2: txt = _( "Inner2" ); break;
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case LAYER_N_3: txt = _( "Inner3" ); break;
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case LAYER_N_4: txt = _( "Inner4" ); break;
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case LAYER_N_5: txt = _( "Inner5" ); break;
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case LAYER_N_6: txt = _( "Inner6" ); break;
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case LAYER_N_7: txt = _( "Inner7" ); break;
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case LAYER_N_8: txt = _( "Inner8" ); break;
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case LAYER_N_9: txt = _( "Inner9" ); break;
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case LAYER_N_10: txt = _( "Inner10" ); break;
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case LAYER_N_11: txt = _( "Inner11" ); break;
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case LAYER_N_12: txt = _( "Inner12" ); break;
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case LAYER_N_13: txt = _( "Inner13" ); break;
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case LAYER_N_14: txt = _( "Inner14" ); break;
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case LAYER_N_15: txt = _( "Inner15" ); break;
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case LAYER_N_BACK: txt = _( "Back" ); break;
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case ADHESIVE_N_BACK: txt = _( "Adhes_Back" ); break;
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case ADHESIVE_N_FRONT: txt = _( "Adhes_Front" ); break;
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case SOLDERPASTE_N_BACK: txt = _( "SoldP_Back" ); break;
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case SOLDERPASTE_N_FRONT: txt = _( "SoldP_Front" ); break;
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case SILKSCREEN_N_BACK: txt = _( "SilkS_Back" ); break;
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case SILKSCREEN_N_FRONT: txt = _( "SilkS_Front" ); break;
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case SOLDERMASK_N_BACK: txt = _( "Mask_Back" ); break;
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case SOLDERMASK_N_FRONT: txt = _( "Mask_Front" ); break;
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case DRAW_N: txt = _( "Drawings" ); break;
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case COMMENT_N: txt = _( "Comments" ); break;
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case ECO1_N: txt = _( "Eco1" ); break;
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case ECO2_N: txt = _( "Eco2" ); break;
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case EDGE_N: txt = _( "PCB_Edges" ); break;
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default: txt = _( "BAD INDEX" ); break;
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}
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return wxString( txt );
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}
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bool BOARD::SetLayerName( int aLayerIndex, const wxString& aLayerName )
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{
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if( !IsValidCopperLayerIndex( aLayerIndex ) )
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return false;
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if( aLayerName == wxEmptyString || aLayerName.Len() > 20 )
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return false;
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// no quote chars in the name allowed
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if( aLayerName.Find( wxChar( '"' ) ) != wxNOT_FOUND )
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return false;
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wxString NameTemp = aLayerName;
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// replace any spaces with underscores before we do any comparing
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NameTemp.Replace( wxT( " " ), wxT( "_" ) );
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if( IsLayerEnabled( aLayerIndex ) )
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{
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for( int i = 0; i < NB_COPPER_LAYERS; i++ )
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{
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if( i != aLayerIndex && IsLayerEnabled( i )
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&& NameTemp == m_Layer[i].m_Name )
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return false;
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}
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m_Layer[aLayerIndex].m_Name = NameTemp;
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return true;
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}
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return false;
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}
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LAYER_T BOARD::GetLayerType( int aLayerIndex ) const
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{
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if( !IsValidCopperLayerIndex( aLayerIndex ) )
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return LT_SIGNAL;
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//@@IMB: The original test was broken due to the discontinuity
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// in the layer sequence.
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if( IsLayerEnabled( aLayerIndex ) )
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return m_Layer[aLayerIndex].m_Type;
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return LT_SIGNAL;
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}
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bool BOARD::SetLayerType( int aLayerIndex, LAYER_T aLayerType )
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{
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if( !IsValidCopperLayerIndex( aLayerIndex ) )
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return false;
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//@@IMB: The original test was broken due to the discontinuity
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// in the layer sequence.
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if( IsLayerEnabled( aLayerIndex ) )
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{
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m_Layer[aLayerIndex].m_Type = aLayerType;
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return true;
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}
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return false;
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}
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const char* LAYER::ShowType( LAYER_T aType )
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{
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const char* cp;
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switch( aType )
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{
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default:
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case LT_SIGNAL:
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cp = "signal";
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break;
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case LT_POWER:
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cp = "power";
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break;
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case LT_MIXED:
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cp = "mixed";
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break;
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case LT_JUMPER:
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cp = "jumper";
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break;
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}
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return cp;
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}
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LAYER_T LAYER::ParseType( const char* aType )
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{
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if( strcmp( aType, "signal" ) == 0 )
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return LT_SIGNAL;
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else if( strcmp( aType, "power" ) == 0 )
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return LT_POWER;
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else if( strcmp( aType, "mixed" ) == 0 )
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return LT_MIXED;
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else if( strcmp( aType, "jumper" ) == 0 )
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return LT_JUMPER;
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else
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return LAYER_T( -1 );
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}
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int BOARD::GetCopperLayerCount() const
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{
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return GetBoardDesignSettings()->GetCopperLayerCount();
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}
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void BOARD::SetCopperLayerCount( int aCount )
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{
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GetBoardDesignSettings()->SetCopperLayerCount( aCount );
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}
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int BOARD::GetEnabledLayers() const
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{
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return GetBoardDesignSettings()->GetEnabledLayers();
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}
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int BOARD::GetVisibleLayers() const
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{
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return GetBoardDesignSettings()->GetVisibleLayers();
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}
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void BOARD::SetEnabledLayers( int aLayerMask )
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{
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GetBoardDesignSettings()->SetEnabledLayers( aLayerMask );
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}
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void BOARD::SetVisibleLayers( int aLayerMask )
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{
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GetBoardDesignSettings()->SetVisibleLayers( aLayerMask );
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}
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// these are not tidy, since there are PCB_VISIBLEs that are not stored in the bitmap.
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void BOARD::SetVisibleElements( int aMask )
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{
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/* Call SetElementVisibility for each item,
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* to ensure specific calculations that can be needed by some items
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* just change the visibility flags could be not sufficient
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*/
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for( int ii = 0; ii < PCB_VISIBLE(END_PCB_VISIBLE_LIST); ii++ )
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{
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int item_mask = 1 << ii;
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SetElementVisibility( ii, aMask & item_mask );
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}
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}
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// these are not tidy, since there are PCB_VISIBLEs that are not stored in the bitmap.
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void BOARD::SetVisibleAlls( )
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{
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SetVisibleLayers( FULL_LAYERS );
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/* Call SetElementVisibility for each item,
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* to ensure specific calculations that can be needed by some items
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*/
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for( int ii = 0; ii < PCB_VISIBLE(END_PCB_VISIBLE_LIST); ii++ )
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SetElementVisibility( ii, true );
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}
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int BOARD::GetVisibleElements() const
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{
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return GetBoardDesignSettings()->GetVisibleElements();
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}
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bool BOARD::IsElementVisible( int aPCB_VISIBLE ) const
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{
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return GetBoardDesignSettings()->IsElementVisible( aPCB_VISIBLE );
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}
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void BOARD::SetElementVisibility( int aPCB_VISIBLE, bool isEnabled )
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{
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switch( aPCB_VISIBLE )
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{
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case RATSNEST_VISIBLE:
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GetBoardDesignSettings()->SetElementVisibility( aPCB_VISIBLE, isEnabled );
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// we must clear or set the CH_VISIBLE flags to hide/show ratsnet
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// because we have a tool to show hide ratsnest relative to a pad or a module
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// so the hide/show option is a per item selection
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if( IsElementVisible(RATSNEST_VISIBLE) )
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{
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for( unsigned ii = 0; ii < GetRatsnestsCount(); ii++ )
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m_FullRatsnest[ii].m_Status |= CH_VISIBLE;
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}
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else
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{
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for( unsigned ii = 0; ii < GetRatsnestsCount(); ii++ )
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m_FullRatsnest[ii].m_Status &= ~CH_VISIBLE;
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}
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break;
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default:
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GetBoardDesignSettings()->SetElementVisibility( aPCB_VISIBLE, isEnabled );
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}
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}
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int BOARD::GetVisibleElementColor( int aPCB_VISIBLE )
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{
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int color = -1;
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switch( aPCB_VISIBLE )
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{
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case VIA_THROUGH_VISIBLE:
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case VIA_MICROVIA_VISIBLE:
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case VIA_BBLIND_VISIBLE:
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case MOD_TEXT_FR_VISIBLE:
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case MOD_TEXT_BK_VISIBLE:
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case MOD_TEXT_INVISIBLE:
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case ANCHOR_VISIBLE:
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case PAD_FR_VISIBLE:
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case PAD_BK_VISIBLE:
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case RATSNEST_VISIBLE:
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case GRID_VISIBLE:
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color = GetColorsSettings()->GetItemColor( aPCB_VISIBLE );
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break;
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default:
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wxLogDebug( wxT( "BOARD::GetVisibleElementColor(): bad arg %d" ), aPCB_VISIBLE );
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}
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return color;
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}
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void BOARD::SetVisibleElementColor( int aPCB_VISIBLE, int aColor )
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{
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switch( aPCB_VISIBLE )
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{
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case VIA_THROUGH_VISIBLE:
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case VIA_MICROVIA_VISIBLE:
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case VIA_BBLIND_VISIBLE:
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case MOD_TEXT_FR_VISIBLE:
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case MOD_TEXT_BK_VISIBLE:
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case MOD_TEXT_INVISIBLE:
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case ANCHOR_VISIBLE:
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case PAD_FR_VISIBLE:
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case PAD_BK_VISIBLE:
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case GRID_VISIBLE:
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case RATSNEST_VISIBLE:
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GetColorsSettings()->SetItemColor( aPCB_VISIBLE, aColor );
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break;
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default:
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wxLogDebug( wxT( "BOARD::SetVisibleElementColor(): bad arg %d" ), aPCB_VISIBLE );
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}
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}
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void BOARD::SetLayerColor( int aLayer, int aColor )
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{
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GetColorsSettings()->SetLayerColor( aLayer, aColor );
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}
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int BOARD::GetLayerColor( int aLayer )
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{
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return GetColorsSettings()->GetLayerColor( aLayer );
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}
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/**
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* Function IsModuleLayerVisible
|
|
* expects either of the two layers on which a module can reside, and returns
|
|
* whether that layer is visible.
|
|
* @param layer One of the two allowed layers for modules: LAYER_N_FRONT or LAYER_N_BACK
|
|
* @return bool - true if the layer is visible, else false.
|
|
*/
|
|
bool BOARD::IsModuleLayerVisible( int layer )
|
|
{
|
|
if( layer==LAYER_N_FRONT )
|
|
return IsElementVisible( PCB_VISIBLE(MOD_FR_VISIBLE) );
|
|
|
|
else if( layer==LAYER_N_BACK )
|
|
return IsElementVisible( PCB_VISIBLE(MOD_BK_VISIBLE) );
|
|
|
|
else
|
|
return true;
|
|
}
|
|
|
|
|
|
|
|
wxPoint& BOARD::GetPosition()
|
|
{
|
|
static wxPoint dummy( 0, 0 );
|
|
|
|
return dummy; // a reference
|
|
}
|
|
|
|
|
|
void BOARD::Add( BOARD_ITEM* aBoardItem, int aControl )
|
|
{
|
|
if( aBoardItem == NULL )
|
|
{
|
|
wxFAIL_MSG( wxT( "BOARD::Add() param error: aBoardItem NULL" ) );
|
|
return;
|
|
}
|
|
|
|
switch( aBoardItem->Type() )
|
|
{
|
|
// this one uses a vector
|
|
case TYPE_MARKER_PCB:
|
|
aBoardItem->SetParent( this );
|
|
m_markers.push_back( (MARKER_PCB*) aBoardItem );
|
|
break;
|
|
|
|
// this one uses a vector
|
|
case TYPE_ZONE_CONTAINER:
|
|
aBoardItem->SetParent( this );
|
|
m_ZoneDescriptorList.push_back( (ZONE_CONTAINER*) aBoardItem );
|
|
break;
|
|
|
|
case TYPE_TRACK:
|
|
case TYPE_VIA:
|
|
TRACK* insertAid;
|
|
insertAid = ( (TRACK*) aBoardItem )->GetBestInsertPoint( this );
|
|
m_Track.Insert( (TRACK*) aBoardItem, insertAid );
|
|
break;
|
|
|
|
case TYPE_ZONE:
|
|
if( aControl & ADD_APPEND )
|
|
m_Zone.PushBack( (SEGZONE*) aBoardItem );
|
|
else
|
|
m_Zone.PushFront( (SEGZONE*) aBoardItem );
|
|
aBoardItem->SetParent( this );
|
|
break;
|
|
|
|
case TYPE_MODULE:
|
|
if( aControl & ADD_APPEND )
|
|
m_Modules.PushBack( (MODULE*) aBoardItem );
|
|
else
|
|
m_Modules.PushFront( (MODULE*) aBoardItem );
|
|
aBoardItem->SetParent( this );
|
|
|
|
// Because the list of pads has changed, reset the status
|
|
// This indicate the list of pad and nets must be recalculated before
|
|
// use
|
|
m_Status_Pcb = 0;
|
|
break;
|
|
|
|
case TYPE_DIMENSION:
|
|
case TYPE_DRAWSEGMENT:
|
|
case TYPE_TEXTE:
|
|
case TYPE_EDGE_MODULE:
|
|
case TYPE_MIRE:
|
|
if( aControl & ADD_APPEND )
|
|
m_Drawings.PushBack( aBoardItem );
|
|
else
|
|
m_Drawings.PushFront( aBoardItem );
|
|
aBoardItem->SetParent( this );
|
|
break;
|
|
|
|
// other types may use linked list
|
|
default:
|
|
{
|
|
wxString msg;
|
|
msg.Printf(
|
|
wxT( "BOARD::Add() needs work: BOARD_ITEM type (%d) not handled" ),
|
|
aBoardItem->Type() );
|
|
wxFAIL_MSG( msg );
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
BOARD_ITEM* BOARD::Remove( BOARD_ITEM* aBoardItem )
|
|
{
|
|
// find these calls and fix them! Don't send me no stinkin' NULL.
|
|
wxASSERT( aBoardItem );
|
|
|
|
switch( aBoardItem->Type() )
|
|
{
|
|
case TYPE_MARKER_PCB:
|
|
|
|
// find the item in the vector, then remove it
|
|
for( unsigned i = 0; i<m_markers.size(); ++i )
|
|
{
|
|
if( m_markers[i] == (MARKER_PCB*) aBoardItem )
|
|
{
|
|
m_markers.erase( m_markers.begin() + i );
|
|
break;
|
|
}
|
|
}
|
|
|
|
break;
|
|
|
|
case TYPE_ZONE_CONTAINER: // this one uses a vector
|
|
// find the item in the vector, then delete then erase it.
|
|
for( unsigned i = 0; i<m_ZoneDescriptorList.size(); ++i )
|
|
{
|
|
if( m_ZoneDescriptorList[i] == (ZONE_CONTAINER*) aBoardItem )
|
|
{
|
|
m_ZoneDescriptorList.erase( m_ZoneDescriptorList.begin() + i );
|
|
break;
|
|
}
|
|
}
|
|
|
|
break;
|
|
|
|
case TYPE_MODULE:
|
|
m_Modules.Remove( (MODULE*) aBoardItem );
|
|
break;
|
|
|
|
case TYPE_TRACK:
|
|
case TYPE_VIA:
|
|
m_Track.Remove( (TRACK*) aBoardItem );
|
|
break;
|
|
|
|
case TYPE_ZONE:
|
|
m_Zone.Remove( (SEGZONE*) aBoardItem );
|
|
break;
|
|
|
|
case TYPE_DIMENSION:
|
|
case TYPE_DRAWSEGMENT:
|
|
case TYPE_TEXTE:
|
|
case TYPE_EDGE_MODULE:
|
|
case TYPE_MIRE:
|
|
m_Drawings.Remove( aBoardItem );
|
|
break;
|
|
|
|
// other types may use linked list
|
|
default:
|
|
wxFAIL_MSG( wxT( "BOARD::Remove() needs more ::Type() support" ) );
|
|
}
|
|
|
|
return aBoardItem;
|
|
}
|
|
|
|
|
|
void BOARD::DeleteMARKERs()
|
|
{
|
|
// the vector does not know how to delete the MARKER_PCB, it holds pointers
|
|
for( unsigned i = 0; i<m_markers.size(); ++i )
|
|
delete m_markers[i];
|
|
|
|
m_markers.clear();
|
|
}
|
|
|
|
|
|
void BOARD::DeleteZONEOutlines()
|
|
{
|
|
// the vector does not know how to delete the ZONE Outlines, it holds
|
|
// pointers
|
|
for( unsigned i = 0; i<m_ZoneDescriptorList.size(); ++i )
|
|
delete m_ZoneDescriptorList[i];
|
|
|
|
m_ZoneDescriptorList.clear();
|
|
}
|
|
|
|
|
|
/* Calculate the track segment count */
|
|
int BOARD::GetNumSegmTrack()
|
|
{
|
|
return m_Track.GetCount();
|
|
}
|
|
|
|
|
|
/* Calculate the zone segment count */
|
|
int BOARD::GetNumSegmZone()
|
|
{
|
|
return m_Zone.GetCount();
|
|
}
|
|
|
|
|
|
// return the unconnection count
|
|
unsigned BOARD::GetNoconnectCount()
|
|
{
|
|
return m_NbNoconnect;
|
|
}
|
|
|
|
|
|
// return the active pad count ( pads with a netcode > 0 )
|
|
unsigned BOARD::GetNodesCount()
|
|
{
|
|
return m_NbNodes;
|
|
}
|
|
|
|
|
|
bool BOARD::ComputeBoundingBox( bool aBoardEdgesOnly )
|
|
{
|
|
bool hasItems = false;
|
|
EDA_RECT area;
|
|
|
|
// Check segments, dimensions, texts, and fiducials
|
|
for( BOARD_ITEM* item = m_Drawings; item != NULL; item = item->Next() )
|
|
{
|
|
if( aBoardEdgesOnly && item->Type() != TYPE_DRAWSEGMENT && item->GetLayer() != EDGE_N )
|
|
continue;
|
|
|
|
if( !hasItems )
|
|
area = item->GetBoundingBox();
|
|
else
|
|
area.Merge( item->GetBoundingBox() );
|
|
hasItems = true;
|
|
}
|
|
|
|
if( !aBoardEdgesOnly )
|
|
{
|
|
// Check modules
|
|
for( MODULE* module = m_Modules; module; module = module->Next() )
|
|
{
|
|
if( !hasItems )
|
|
area = module->GetBoundingBox();
|
|
else
|
|
area.Merge( module->GetBoundingBox() );
|
|
hasItems = true;
|
|
}
|
|
|
|
// Check tracks
|
|
for( TRACK* track = m_Track; track; track = track->Next() )
|
|
{
|
|
if( !hasItems )
|
|
area = track->GetBoundingBox();
|
|
else
|
|
area.Merge( track->GetBoundingBox() );
|
|
hasItems = true;
|
|
}
|
|
|
|
// Check segment zones
|
|
for( TRACK* track = m_Zone; track; track = track->Next() )
|
|
{
|
|
if( !hasItems )
|
|
area = track->GetBoundingBox();
|
|
else
|
|
area.Merge( track->GetBoundingBox() );
|
|
hasItems = true;
|
|
}
|
|
|
|
// Check polygonal zones
|
|
for( unsigned int i = 0; i < m_ZoneDescriptorList.size(); i++ )
|
|
{
|
|
ZONE_CONTAINER* aZone = m_ZoneDescriptorList[i];
|
|
|
|
if( !hasItems )
|
|
area = aZone->GetBoundingBox();
|
|
else
|
|
area.Merge( aZone->GetBoundingBox() );
|
|
area.Merge( aZone->GetBoundingBox() );
|
|
hasItems = true;
|
|
}
|
|
}
|
|
|
|
if( !hasItems && m_PcbFrame )
|
|
{
|
|
if( m_PcbFrame->m_Draw_Sheet_Ref )
|
|
{
|
|
area.SetOrigin( 0, 0 );
|
|
area.SetEnd( m_PcbFrame->GetScreen()->ReturnPageSize().x,
|
|
m_PcbFrame->GetScreen()->ReturnPageSize().y );
|
|
}
|
|
else
|
|
{
|
|
area.SetOrigin( -m_PcbFrame->GetScreen()->ReturnPageSize().x / 2,
|
|
-m_PcbFrame->GetScreen()->ReturnPageSize().y / 2 );
|
|
area.SetEnd( m_PcbFrame->GetScreen()->ReturnPageSize().x / 2,
|
|
m_PcbFrame->GetScreen()->ReturnPageSize().y / 2 );
|
|
}
|
|
}
|
|
|
|
m_BoundaryBox = area;
|
|
|
|
return hasItems;
|
|
}
|
|
|
|
|
|
// virtual, see pcbstruct.h
|
|
|
|
/* Display board statistics: pads, nets, connections.. count
|
|
*/
|
|
void BOARD::DisplayInfo( EDA_DRAW_FRAME* frame )
|
|
{
|
|
wxString txt;
|
|
|
|
frame->ClearMsgPanel();
|
|
|
|
int viasCount = 0;
|
|
int trackSegmentsCount = 0;
|
|
for( BOARD_ITEM* item = m_Track; item; item = item->Next() )
|
|
{
|
|
if( item->Type() == TYPE_VIA )
|
|
viasCount++;
|
|
else
|
|
trackSegmentsCount++;
|
|
}
|
|
|
|
txt.Printf( wxT( "%d" ), GetPadsCount() );
|
|
frame->AppendMsgPanel( _( "Pads" ), txt, DARKGREEN );
|
|
|
|
txt.Printf( wxT( "%d" ), viasCount );
|
|
frame->AppendMsgPanel( _( "Vias" ), txt, DARKGREEN );
|
|
|
|
txt.Printf( wxT( "%d" ), trackSegmentsCount );
|
|
frame->AppendMsgPanel( _( "trackSegm" ), txt, DARKGREEN );
|
|
|
|
txt.Printf( wxT( "%d" ), GetNodesCount() );
|
|
frame->AppendMsgPanel( _( "Nodes" ), txt, DARKCYAN );
|
|
|
|
txt.Printf( wxT( "%d" ), m_NetInfo->GetCount() );
|
|
frame->AppendMsgPanel( _( "Nets" ), txt, RED );
|
|
|
|
/* These parameters are known only if the full ratsnest is available,
|
|
* so, display them only if this is the case
|
|
*/
|
|
if( (m_Status_Pcb & NET_CODES_OK) )
|
|
{
|
|
txt.Printf( wxT( "%d" ), GetRatsnestsCount() );
|
|
frame->AppendMsgPanel( _( "Links" ), txt, DARKGREEN );
|
|
|
|
txt.Printf( wxT( "%d" ), GetRatsnestsCount() - GetNoconnectCount() );
|
|
frame->AppendMsgPanel( _( "Connect" ), txt, DARKGREEN );
|
|
|
|
txt.Printf( wxT( "%d" ), GetNoconnectCount() );
|
|
frame->AppendMsgPanel( _( "Unconnected" ), txt, BLUE );
|
|
}
|
|
}
|
|
|
|
|
|
// virtual, see pcbstruct.h
|
|
SEARCH_RESULT BOARD::Visit( INSPECTOR* inspector, const void* testData,
|
|
const KICAD_T scanTypes[] )
|
|
{
|
|
KICAD_T stype;
|
|
SEARCH_RESULT result = SEARCH_CONTINUE;
|
|
const KICAD_T* p = scanTypes;
|
|
bool done = false;
|
|
|
|
#if 0 && defined(DEBUG)
|
|
std::cout << GetClass().mb_str() << ' ';
|
|
#endif
|
|
|
|
while( !done )
|
|
{
|
|
stype = *p;
|
|
switch( stype )
|
|
{
|
|
case TYPE_PCB:
|
|
result = inspector->Inspect( this, testData ); // inspect me
|
|
// skip over any types handled in the above call.
|
|
++p;
|
|
break;
|
|
|
|
/* Instances of the requested KICAD_T live in a list, either one
|
|
* that I manage, or that my modules manage. If it's a type managed
|
|
* by class MODULE, then simply pass it on to each module's
|
|
* MODULE::Visit() function by way of the
|
|
* IterateForward( m_Modules, ... ) call.
|
|
*/
|
|
|
|
case TYPE_MODULE:
|
|
case TYPE_PAD:
|
|
case TYPE_TEXTE_MODULE:
|
|
case TYPE_EDGE_MODULE:
|
|
|
|
// this calls MODULE::Visit() on each module.
|
|
result = IterateForward( m_Modules, inspector, testData, p );
|
|
|
|
// skip over any types handled in the above call.
|
|
for( ; ; )
|
|
{
|
|
switch( stype = *++p )
|
|
{
|
|
case TYPE_MODULE:
|
|
case TYPE_PAD:
|
|
case TYPE_TEXTE_MODULE:
|
|
case TYPE_EDGE_MODULE:
|
|
continue;
|
|
|
|
default:
|
|
;
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
break;
|
|
|
|
case TYPE_DRAWSEGMENT:
|
|
case TYPE_TEXTE:
|
|
case TYPE_DIMENSION:
|
|
case TYPE_MIRE:
|
|
result = IterateForward( m_Drawings, inspector, testData, p );
|
|
|
|
// skip over any types handled in the above call.
|
|
for( ; ; )
|
|
{
|
|
switch( stype = *++p )
|
|
{
|
|
case TYPE_DRAWSEGMENT:
|
|
case TYPE_TEXTE:
|
|
case TYPE_DIMENSION:
|
|
case TYPE_MIRE:
|
|
continue;
|
|
|
|
default:
|
|
;
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
;
|
|
break;
|
|
|
|
#if 0 // both these are on same list, so we must scan it twice in order
|
|
// to get VIA priority, using new #else code below.
|
|
// But we are not using separate lists for TRACKs and SEGVIAs, because
|
|
// items are ordered (sorted) in the linked
|
|
// list by netcode AND by physical distance:
|
|
// when created, if a track or via is connected to an existing track or
|
|
// via, it is put in linked list after this existing track or via
|
|
// So usually, connected tracks or vias are grouped in this list
|
|
// So the algorithm (used in rastnest computations) which computes the
|
|
// track connectivity is faster (more than 100 time regarding to
|
|
// a non ordered list) because when it searches for a connexion, first
|
|
// it tests the near (near in term of linked list) 50 items
|
|
// from the current item (track or via) in test.
|
|
// Usually, because of this sort, a connected item (if exists) is
|
|
// found.
|
|
// If not found (and only in this case) an exhaustive (and time
|
|
// consuming) search is made, but this case is statistically rare.
|
|
case TYPE_VIA:
|
|
case TYPE_TRACK:
|
|
result = IterateForward( m_Track, inspector, testData, p );
|
|
|
|
// skip over any types handled in the above call.
|
|
for( ; ; )
|
|
{
|
|
switch( stype = *++p )
|
|
{
|
|
case TYPE_VIA:
|
|
case TYPE_TRACK:
|
|
continue;
|
|
|
|
default:
|
|
;
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
break;
|
|
|
|
#else
|
|
case TYPE_VIA:
|
|
result = IterateForward( m_Track, inspector, testData, p );
|
|
++p;
|
|
break;
|
|
|
|
case TYPE_TRACK:
|
|
result = IterateForward( m_Track, inspector, testData, p );
|
|
++p;
|
|
break;
|
|
#endif
|
|
|
|
case TYPE_MARKER_PCB:
|
|
|
|
// MARKER_PCBS are in the m_markers std::vector
|
|
for( unsigned i = 0; i<m_markers.size(); ++i )
|
|
{
|
|
result = m_markers[i]->Visit( inspector, testData, p );
|
|
if( result == SEARCH_QUIT )
|
|
break;
|
|
}
|
|
|
|
++p;
|
|
break;
|
|
|
|
case TYPE_ZONE_CONTAINER:
|
|
|
|
// TYPE_ZONE_CONTAINER are in the m_ZoneDescriptorList std::vector
|
|
for( unsigned i = 0; i< m_ZoneDescriptorList.size(); ++i )
|
|
{
|
|
result = m_ZoneDescriptorList[i]->Visit( inspector,
|
|
testData,
|
|
p );
|
|
if( result == SEARCH_QUIT )
|
|
break;
|
|
}
|
|
|
|
++p;
|
|
break;
|
|
|
|
case TYPE_ZONE:
|
|
result = IterateForward( m_Zone, inspector, testData, p );
|
|
++p;
|
|
break;
|
|
|
|
default: // catch EOT or ANY OTHER type here and return.
|
|
done = true;
|
|
break;
|
|
}
|
|
|
|
if( result == SEARCH_QUIT )
|
|
break;
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
|
|
/* now using PcbGeneralLocateAndDisplay(), but this remains a useful example
|
|
* of how the INSPECTOR can be used in a lightweight way.
|
|
* // see pcbstruct.h
|
|
* BOARD_ITEM* BOARD::FindPadOrModule( const wxPoint& refPos, int layer )
|
|
* {
|
|
* class PadOrModule : public INSPECTOR
|
|
* {
|
|
* public:
|
|
* BOARD_ITEM* found;
|
|
* int layer;
|
|
* int layer_mask;
|
|
*
|
|
* PadOrModule( int alayer ) :
|
|
* found(0), layer(alayer), layer_mask( g_TabOneLayerMask[alayer] )
|
|
* {}
|
|
*
|
|
* SEARCH_RESULT Inspect( EDA_ITEM* testItem, const void* testData
|
|
* )
|
|
* {
|
|
* BOARD_ITEM* item = (BOARD_ITEM*) testItem;
|
|
* const wxPoint& refPos = *(const wxPoint*) testData;
|
|
*
|
|
* if( item->Type() == TYPE_PAD )
|
|
* {
|
|
* D_PAD* pad = (D_PAD*) item;
|
|
* if( pad->HitTest( refPos ) )
|
|
* {
|
|
* if( layer_mask & pad->m_Masque_Layer )
|
|
* {
|
|
* found = item;
|
|
* return SEARCH_QUIT;
|
|
* }
|
|
* else if( !found )
|
|
* {
|
|
* MODULE* parent = (MODULE*) pad->m_Parent;
|
|
* if( IsModuleLayerVisible( parent->GetLayer() ) )
|
|
* found = item;
|
|
* }
|
|
* }
|
|
* }
|
|
*
|
|
* else if( item->Type() == TYPE_MODULE )
|
|
* {
|
|
* MODULE* module = (MODULE*) item;
|
|
*
|
|
* // consider only visible modules
|
|
* if( IsModuleLayerVisible( module->GetLayer() ) )
|
|
* {
|
|
* if( module->HitTest( refPos ) )
|
|
* {
|
|
* if( layer == module->GetLayer() )
|
|
* {
|
|
* found = item;
|
|
* return SEARCH_QUIT;
|
|
* }
|
|
*
|
|
* // layer mismatch, save in case we don't find a
|
|
* // future layer match hit.
|
|
* if( !found )
|
|
* found = item;
|
|
* }
|
|
* }
|
|
* }
|
|
* return SEARCH_CONTINUE;
|
|
* }
|
|
* };
|
|
*
|
|
* PadOrModule inspector( layer );
|
|
*
|
|
* // search only for PADs first, then MODULES, and preferably a layer match
|
|
* static const KICAD_T scanTypes[] = { TYPE_PAD, TYPE_MODULE, EOT };
|
|
*
|
|
* // visit this BOARD with the above inspector
|
|
* Visit( &inspector, &refPos, scanTypes );
|
|
*
|
|
* return inspector.found;
|
|
* }
|
|
*/
|
|
|
|
|
|
/**
|
|
* Function FindNet
|
|
* searches for a net with the given netcode.
|
|
* @param aNetcode The netcode to search for.
|
|
* @return NETINFO_ITEM* - the net or NULL if not found.
|
|
*/
|
|
NETINFO_ITEM* BOARD::FindNet( int aNetcode ) const
|
|
{
|
|
// the first valid netcode is 1 and the last is m_NetInfo->GetCount()-1.
|
|
// zero is reserved for "no connection" and is not used.
|
|
// NULL is returned for non valid netcodes
|
|
NETINFO_ITEM* net = m_NetInfo->GetNetItem( aNetcode );
|
|
|
|
#if defined(DEBUG)
|
|
if( net ) // item can be NULL if anetcode is not valid
|
|
{
|
|
if( aNetcode != net->GetNet() )
|
|
{
|
|
printf( "FindNet() anetcode %d != GetNet() %d (net: %s)\n",
|
|
aNetcode, net->GetNet(), TO_UTF8( net->GetNetname() ) );
|
|
}
|
|
}
|
|
#endif
|
|
|
|
return net;
|
|
}
|
|
|
|
|
|
/**
|
|
* Function FindNet overlaid
|
|
* searches for a net with the given name.
|
|
* @param aNetname A Netname to search for.
|
|
* @return NETINFO_ITEM* - the net or NULL if not found.
|
|
*/
|
|
NETINFO_ITEM* BOARD::FindNet( const wxString& aNetname ) const
|
|
{
|
|
// the first valid netcode is 1.
|
|
// zero is reserved for "no connection" and is not used.
|
|
if( aNetname.IsEmpty() )
|
|
return NULL;
|
|
|
|
int ncount = m_NetInfo->GetCount();
|
|
|
|
// Search for a netname = aNetname
|
|
#if 0
|
|
|
|
// Use a sequential search: easy to understand, but slow
|
|
for( int ii = 1; ii < ncount; ii++ )
|
|
{
|
|
NETINFO_ITEM* item = m_NetInfo->GetNetItem( ii );
|
|
if( item && item->GetNetname() == aNetname )
|
|
{
|
|
return item;
|
|
}
|
|
}
|
|
|
|
#else
|
|
|
|
// Use a fast binary search,
|
|
// this is possible because Nets are alphabetically ordered in list
|
|
// see NETINFO_LIST::BuildListOfNets() and
|
|
// NETINFO_LIST::Build_Pads_Full_List()
|
|
int imax = ncount - 1;
|
|
int index = imax;
|
|
while( ncount > 0 )
|
|
{
|
|
int ii = ncount;
|
|
ncount >>= 1;
|
|
|
|
if( (ii & 1) && ( ii > 1 ) )
|
|
ncount++;
|
|
|
|
NETINFO_ITEM* item = m_NetInfo->GetNetItem( index );
|
|
if( item == NULL )
|
|
return NULL;
|
|
int icmp = item->GetNetname().Cmp( aNetname );
|
|
|
|
if( icmp == 0 ) // found !
|
|
{
|
|
return item;
|
|
}
|
|
if( icmp < 0 ) // must search after item
|
|
{
|
|
index += ncount;
|
|
if( index > imax )
|
|
index = imax;
|
|
continue;
|
|
}
|
|
if( icmp > 0 ) // must search before item
|
|
{
|
|
index -= ncount;
|
|
if( index < 1 )
|
|
index = 1;
|
|
continue;
|
|
}
|
|
}
|
|
|
|
#endif
|
|
return NULL;
|
|
}
|
|
|
|
|
|
MODULE* BOARD::FindModuleByReference( const wxString& aReference ) const
|
|
{
|
|
struct FindModule : public INSPECTOR
|
|
{
|
|
MODULE* found;
|
|
FindModule() : found( 0 ) {}
|
|
|
|
// implement interface INSPECTOR
|
|
SEARCH_RESULT Inspect( EDA_ITEM* item, const void* data )
|
|
{
|
|
MODULE* module = (MODULE*) item;
|
|
const wxString& ref = *(const wxString*) data;
|
|
|
|
if( ref == module->GetReference() )
|
|
{
|
|
found = module;
|
|
return SEARCH_QUIT;
|
|
}
|
|
return SEARCH_CONTINUE;
|
|
}
|
|
} inspector;
|
|
|
|
// search only for MODULES
|
|
static const KICAD_T scanTypes[] = { TYPE_MODULE, EOT };
|
|
|
|
// visit this BOARD with the above inspector
|
|
BOARD* nonconstMe = (BOARD*) this;
|
|
nonconstMe->Visit( &inspector, &aReference, scanTypes );
|
|
|
|
return inspector.found;
|
|
}
|
|
|
|
|
|
// Sort nets by decreasing pad count
|
|
static bool s_SortByNodes( const NETINFO_ITEM* a, const NETINFO_ITEM* b )
|
|
{
|
|
return b->GetNodesCount() < a->GetNodesCount();
|
|
}
|
|
|
|
|
|
/**
|
|
* Function ReturnSortedNetnamesList
|
|
* @param aNames An array string to fill with net names.
|
|
* @param aSortbyPadsCount : true = sort by active pads count, false = no sort
|
|
* (i.e. leave the sort by net names)
|
|
* @return int - net names count.
|
|
*/
|
|
int BOARD::ReturnSortedNetnamesList( wxArrayString& aNames,
|
|
bool aSortbyPadsCount )
|
|
{
|
|
if( m_NetInfo->GetCount() == 0 )
|
|
return 0;
|
|
|
|
// Build the list
|
|
std::vector <NETINFO_ITEM*> netBuffer;
|
|
|
|
netBuffer.reserve( m_NetInfo->GetCount() );
|
|
|
|
for( unsigned ii = 1; ii < m_NetInfo->GetCount(); ii++ )
|
|
{
|
|
if( m_NetInfo->GetNetItem( ii )->GetNet() > 0 )
|
|
netBuffer.push_back( m_NetInfo->GetNetItem( ii ) );
|
|
}
|
|
|
|
// sort the list
|
|
if( aSortbyPadsCount )
|
|
sort( netBuffer.begin(), netBuffer.end(), s_SortByNodes );
|
|
|
|
for( unsigned ii = 0; ii < netBuffer.size(); ii++ )
|
|
aNames.Add( netBuffer[ii]->GetNetname() );
|
|
|
|
return netBuffer.size();
|
|
}
|
|
|
|
|
|
bool BOARD::Save( FILE* aFile ) const
|
|
{
|
|
bool rc = false;
|
|
BOARD_ITEM* item;
|
|
|
|
// save the nets
|
|
for( unsigned ii = 0; ii < m_NetInfo->GetCount(); ii++ )
|
|
if( !m_NetInfo->GetNetItem( ii )->Save( aFile ) )
|
|
goto out;
|
|
|
|
// Saved nets do not include netclass names, so save netclasses after nets.
|
|
m_NetClasses.Save( aFile );
|
|
|
|
// save the modules
|
|
for( item = m_Modules; item; item = item->Next() )
|
|
if( !item->Save( aFile ) )
|
|
goto out;
|
|
|
|
for( item = m_Drawings; item; item = item->Next() )
|
|
{
|
|
switch( item->Type() )
|
|
{
|
|
case TYPE_TEXTE:
|
|
case TYPE_DRAWSEGMENT:
|
|
case TYPE_MIRE:
|
|
case TYPE_DIMENSION:
|
|
if( !item->Save( aFile ) )
|
|
goto out;
|
|
break;
|
|
|
|
default:
|
|
|
|
// future: throw exception here
|
|
#if defined(DEBUG)
|
|
printf( "BOARD::Save() ignoring m_Drawings type %d\n",
|
|
item->Type() );
|
|
#endif
|
|
break;
|
|
}
|
|
}
|
|
|
|
// do not save MARKER_PCBs, they can be regenerated easily
|
|
|
|
// save the tracks & vias
|
|
fprintf( aFile, "$TRACK\n" );
|
|
for( item = m_Track; item; item = item->Next() )
|
|
if( !item->Save( aFile ) )
|
|
goto out;
|
|
|
|
fprintf( aFile, "$EndTRACK\n" );
|
|
|
|
// save the zones
|
|
fprintf( aFile, "$ZONE\n" );
|
|
for( item = m_Zone; item; item = item->Next() )
|
|
if( !item->Save( aFile ) )
|
|
goto out;
|
|
|
|
fprintf( aFile, "$EndZONE\n" );
|
|
|
|
// save the zone edges
|
|
for( unsigned ii = 0; ii < m_ZoneDescriptorList.size(); ii++ )
|
|
{
|
|
ZONE_CONTAINER* edge_zone = m_ZoneDescriptorList[ii];
|
|
edge_zone->Save( aFile );
|
|
}
|
|
|
|
|
|
if( fprintf( aFile, "$EndBOARD\n" ) != sizeof("$EndBOARD\n") - 1 )
|
|
goto out;
|
|
|
|
rc = true; // wrote all OK
|
|
|
|
out:
|
|
return rc;
|
|
}
|
|
|
|
|
|
/*
|
|
* Function RedrawAreasOutlines
|
|
* Redraw all areas outlines on layer aLayer ( redraw all if aLayer < 0 )
|
|
*/
|
|
void BOARD::RedrawAreasOutlines( EDA_DRAW_PANEL* panel, wxDC* aDC, int aDrawMode, int aLayer )
|
|
{
|
|
if( !aDC )
|
|
return;
|
|
|
|
for( int ii = 0; ii < GetAreaCount(); ii++ )
|
|
{
|
|
ZONE_CONTAINER* edge_zone = GetArea( ii );
|
|
if( (aLayer < 0) || ( aLayer == edge_zone->GetLayer() ) )
|
|
edge_zone->Draw( panel, aDC, aDrawMode );
|
|
}
|
|
}
|
|
|
|
|
|
/**
|
|
* Function RedrawFilledAreas
|
|
* Redraw all areas outlines on layer aLayer ( redraw all if aLayer < 0 )
|
|
*/
|
|
void BOARD::RedrawFilledAreas( EDA_DRAW_PANEL* panel, wxDC* aDC, int aDrawMode, int aLayer )
|
|
{
|
|
if( !aDC )
|
|
return;
|
|
|
|
for( int ii = 0; ii < GetAreaCount(); ii++ )
|
|
{
|
|
ZONE_CONTAINER* edge_zone = GetArea( ii );
|
|
if( (aLayer < 0) || ( aLayer == edge_zone->GetLayer() ) )
|
|
edge_zone->DrawFilledArea( panel, aDC, aDrawMode );
|
|
}
|
|
}
|
|
|
|
|
|
/**
|
|
* Function HitTestForAnyFilledArea
|
|
* tests if the given wxPoint is within the bounds of a filled area of this
|
|
* zone.
|
|
* the test is made on zones on layer from aStartLayer to aEndLayer
|
|
* Note: if a zone has its flag BUSY (in .m_State) is set, it is ignored.
|
|
* @param aRefPos A wxPoint to test
|
|
* @param aStartLayer the first layer to test
|
|
* @param aEndLayer the last layer (-1 to ignore it) to test
|
|
* @return ZONE_CONTAINER* return a pointer to the ZONE_CONTAINER found, else
|
|
* NULL
|
|
*/
|
|
ZONE_CONTAINER* BOARD::HitTestForAnyFilledArea( const wxPoint& aRefPos,
|
|
int aStartLayer,
|
|
int aEndLayer )
|
|
{
|
|
if( aEndLayer < 0 )
|
|
aEndLayer = aStartLayer;
|
|
if( aEndLayer < aStartLayer )
|
|
EXCHG( aEndLayer, aStartLayer );
|
|
|
|
for( unsigned ia = 0; ia < m_ZoneDescriptorList.size(); ia++ )
|
|
{
|
|
ZONE_CONTAINER* area = m_ZoneDescriptorList[ia];
|
|
int layer = area->GetLayer();
|
|
if( (layer < aStartLayer) || (layer > aEndLayer) )
|
|
continue;
|
|
if( area->GetState( BUSY ) ) // In locate functions we must skip
|
|
// tagged items with BUSY flag set.
|
|
continue;
|
|
if( area->HitTestFilledArea( aRefPos ) )
|
|
return area;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
|
|
/**
|
|
* Function SetAreasNetCodesFromNetNames
|
|
* Set the .m_NetCode member of all copper areas, according to the area Net
|
|
* Name
|
|
* The SetNetCodesFromNetNames is an equivalent to net name, for fast
|
|
* comparisons.
|
|
* However the Netcode is an arbitrary equivalence, it must be set after each
|
|
* netlist read
|
|
* or net change
|
|
* Must be called after pad netcodes are calculated
|
|
* @return : error count
|
|
* For non copper areas, netcode is set to 0
|
|
*/
|
|
int BOARD::SetAreasNetCodesFromNetNames( void )
|
|
{
|
|
int error_count = 0;
|
|
|
|
for( int ii = 0; ii < GetAreaCount(); ii++ )
|
|
{
|
|
if( !GetArea( ii )->IsOnCopperLayer() )
|
|
{
|
|
GetArea( ii )->SetNet( 0 );
|
|
continue;
|
|
}
|
|
|
|
if( GetArea( ii )->GetNet() != 0 ) // i.e. if this zone is
|
|
// connected to a net
|
|
{
|
|
const NETINFO_ITEM* net = FindNet( GetArea( ii )->m_Netname );
|
|
if( net )
|
|
{
|
|
GetArea( ii )->SetNet( net->GetNet() );
|
|
}
|
|
else
|
|
{
|
|
error_count++;
|
|
GetArea( ii )->SetNet( -1 ); // keep Net Name and set
|
|
// m_NetCode to -1 : error flag
|
|
}
|
|
}
|
|
}
|
|
|
|
return error_count;
|
|
}
|
|
|
|
|
|
#if defined(DEBUG)
|
|
|
|
/**
|
|
* Function Show
|
|
* is used to output the object tree, currently for debugging only.
|
|
* @param nestLevel An aid to prettier tree indenting, and is the level
|
|
* of nesting of this object within the overall tree.
|
|
* @param os The ostream& to output to.
|
|
*/
|
|
void BOARD::Show( int nestLevel, std::ostream& os )
|
|
{
|
|
BOARD_ITEM* p;
|
|
|
|
// for now, make it look like XML:
|
|
NestedSpace( nestLevel,
|
|
os ) << '<' << GetClass().Lower().mb_str() << ">\n";
|
|
|
|
// specialization of the output:
|
|
NestedSpace( nestLevel + 1, os ) << "<modules>\n";
|
|
p = m_Modules;
|
|
for( ; p; p = p->Next() )
|
|
p->Show( nestLevel + 2, os );
|
|
|
|
NestedSpace( nestLevel + 1, os ) << "</modules>\n";
|
|
|
|
NestedSpace( nestLevel + 1, os ) << "<pdrawings>\n";
|
|
p = m_Drawings;
|
|
for( ; p; p = p->Next() )
|
|
p->Show( nestLevel + 2, os );
|
|
|
|
NestedSpace( nestLevel + 1, os ) << "</pdrawings>\n";
|
|
|
|
NestedSpace( nestLevel + 1, os ) << "<tracks>\n";
|
|
p = m_Track;
|
|
for( ; p; p = p->Next() )
|
|
p->Show( nestLevel + 2, os );
|
|
|
|
NestedSpace( nestLevel + 1, os ) << "</tracks>\n";
|
|
|
|
NestedSpace( nestLevel + 1, os ) << "<zones>\n";
|
|
p = m_Zone;
|
|
for( ; p; p = p->Next() )
|
|
p->Show( nestLevel + 2, os );
|
|
|
|
NestedSpace( nestLevel + 1, os ) << "</zones>\n";
|
|
|
|
/*
|
|
* NestedSpace( nestLevel+1, os ) << "<zone_container>\n";
|
|
* for( ZONE_CONTAINERS::iterator i=m_ZoneDescriptorList.begin();
|
|
* i!=m_ZoneDescriptorList.end(); ++i )
|
|
* (*i)->Show( nestLevel+2, os );
|
|
* NestedSpace( nestLevel+1, os ) << "</zone_container>\n";
|
|
*/
|
|
|
|
p = (BOARD_ITEM*) m_Son;
|
|
for( ; p; p = p->Next() )
|
|
{
|
|
p->Show( nestLevel + 1, os );
|
|
}
|
|
|
|
NestedSpace( nestLevel, os ) << "</" << GetClass().Lower().mb_str()
|
|
<< ">\n";
|
|
}
|
|
|
|
|
|
#endif
|