From 21205f3bdf00520e1ec197a8f930462cf3aa9af1 Mon Sep 17 00:00:00 2001 From: xenia Date: Sat, 25 May 2024 23:34:33 -0400 Subject: [PATCH] replace manual register mux with addressing --- src/project.v | 185 ++++++++++++++------------------------------------ 1 file changed, 52 insertions(+), 133 deletions(-) diff --git a/src/project.v b/src/project.v index 7436e35..113e084 100644 --- a/src/project.v +++ b/src/project.v @@ -47,39 +47,40 @@ module tt_um_xeniarose_sha256 ( reg [7 : 0] io_out; assign uio_out = io_out; - reg [ 31 : 0 ] A_reg; - reg [ 31 : 0 ] B_reg; - reg [ 31 : 0 ] C_reg; - reg [ 31 : 0 ] D_reg; - reg [ 31 : 0 ] E_reg; - reg [ 31 : 0 ] F_reg; - reg [ 31 : 0 ] G_reg; - reg [ 31 : 0 ] H_reg; + reg [ 31 : 0 ] register_file [ 9 : 0 ]; - reg [ 31 : 0 ] W_reg; - reg [ 31 : 0 ] K_reg; + `define A_reg register_file[0] + `define B_reg register_file[1] + `define C_reg register_file[2] + `define D_reg register_file[3] + `define E_reg register_file[4] + `define F_reg register_file[5] + `define G_reg register_file[6] + `define H_reg register_file[7] + `define W_reg register_file[8] + `define K_reg register_file[9] wire [ 31 : 0 ] s1 = - {E_reg[5:0],E_reg[31:6]} ^ {E_reg[10:0],E_reg[31:11]} ^ {E_reg[24:0],E_reg[31:25]}; - wire [ 31 : 0 ] ch = (E_reg & F_reg) ^ ((~E_reg) & G_reg); - wire [ 31 : 0 ] temp1 = H_reg + s1 + ch + K_reg + W_reg; + {`E_reg[5:0],`E_reg[31:6]} ^ {`E_reg[10:0],`E_reg[31:11]} ^ {`E_reg[24:0],`E_reg[31:25]}; + wire [ 31 : 0 ] ch = (`E_reg & `F_reg) ^ ((~`E_reg) & `G_reg); + wire [ 31 : 0 ] temp1 = `H_reg + s1 + ch + `K_reg + `W_reg; wire [ 31 : 0 ] s0 = - {A_reg[1:0],A_reg[31:2]} ^ {A_reg[12:0],A_reg[31:13]} ^ {A_reg[21:0],A_reg[31:22]}; - wire [ 31 : 0 ] maj = (A_reg & B_reg) ^ (A_reg & C_reg) ^ (B_reg & C_reg); + {`A_reg[1:0],`A_reg[31:2]} ^ {`A_reg[12:0],`A_reg[31:13]} ^ {`A_reg[21:0],`A_reg[31:22]}; + wire [ 31 : 0 ] maj = (`A_reg & `B_reg) ^ (`A_reg & `C_reg) ^ (`B_reg & `C_reg); wire [ 31 : 0 ] temp2 = s0 + maj; always @(posedge clk or negedge rst_n) begin : io_proc if (!rst_n) begin - A_reg <= 32'h0; - B_reg <= 32'h0; - C_reg <= 32'h0; - D_reg <= 32'h0; - E_reg <= 32'h0; - F_reg <= 32'h0; - G_reg <= 32'h0; - H_reg <= 32'h0; - W_reg <= 32'h0; - K_reg <= 32'h0; + register_file[0] <= 32'h0; + register_file[1] <= 32'h0; + register_file[2] <= 32'h0; + register_file[3] <= 32'h0; + register_file[4] <= 32'h0; + register_file[5] <= 32'h0; + register_file[6] <= 32'h0; + register_file[7] <= 32'h0; + register_file[8] <= 32'h0; + register_file[9] <= 32'h0; io_out <= 8'h0; io_ready <= 0; @@ -89,120 +90,38 @@ module tt_um_xeniarose_sha256 ( if (io_clk) begin if (!io_we) begin case (io_addr) - 0: begin - A_reg <= temp1 + temp2; - B_reg <= A_reg; - C_reg <= B_reg; - D_reg <= C_reg; - E_reg <= D_reg + temp1; - F_reg <= E_reg; - G_reg <= F_reg; - H_reg <= G_reg; + 63: begin + `A_reg <= temp1 + temp2; + `B_reg <= `A_reg; + `C_reg <= `B_reg; + `D_reg <= `C_reg; + `E_reg <= `D_reg + temp1; + `F_reg <= `E_reg; + `G_reg <= `F_reg; + `H_reg <= `G_reg; end - 4: begin W_reg[ 7 : 0] <= uio_in; end - 5: begin W_reg[15 : 8] <= uio_in; end - 6: begin W_reg[23 : 16] <= uio_in; end - 7: begin W_reg[31 : 24] <= uio_in; end - - 8: begin K_reg[ 7 : 0] <= uio_in; end - 9: begin K_reg[15 : 8] <= uio_in; end - 10: begin K_reg[23 : 16] <= uio_in; end - 11: begin K_reg[31 : 24] <= uio_in; end - - 32: begin A_reg[ 7 : 0] <= uio_in; end - 33: begin A_reg[15 : 8] <= uio_in; end - 34: begin A_reg[23 : 16] <= uio_in; end - 35: begin A_reg[31 : 24] <= uio_in; end - - 36: begin B_reg[ 7 : 0] <= uio_in; end - 37: begin B_reg[15 : 8] <= uio_in; end - 38: begin B_reg[23 : 16] <= uio_in; end - 39: begin B_reg[31 : 24] <= uio_in; end - - 40: begin C_reg[ 7 : 0] <= uio_in; end - 41: begin C_reg[15 : 8] <= uio_in; end - 42: begin C_reg[23 : 16] <= uio_in; end - 43: begin C_reg[31 : 24] <= uio_in; end - - 44: begin D_reg[ 7 : 0] <= uio_in; end - 45: begin D_reg[15 : 8] <= uio_in; end - 46: begin D_reg[23 : 16] <= uio_in; end - 47: begin D_reg[31 : 24] <= uio_in; end - - 48: begin E_reg[ 7 : 0] <= uio_in; end - 49: begin E_reg[15 : 8] <= uio_in; end - 50: begin E_reg[23 : 16] <= uio_in; end - 51: begin E_reg[31 : 24] <= uio_in; end - - 52: begin F_reg[ 7 : 0] <= uio_in; end - 53: begin F_reg[15 : 8] <= uio_in; end - 54: begin F_reg[23 : 16] <= uio_in; end - 55: begin F_reg[31 : 24] <= uio_in; end - - 56: begin G_reg[ 7 : 0] <= uio_in; end - 57: begin G_reg[15 : 8] <= uio_in; end - 58: begin G_reg[23 : 16] <= uio_in; end - 59: begin G_reg[31 : 24] <= uio_in; end - - 60: begin H_reg[ 7 : 0] <= uio_in; end - 61: begin H_reg[15 : 8] <= uio_in; end - 62: begin H_reg[23 : 16] <= uio_in; end - 63: begin H_reg[31 : 24] <= uio_in; end + default: begin + case (io_addr[1:0]) + 2'h0: begin register_file[io_addr[5:2]][7 : 0] <= uio_in; end + 2'h1: begin register_file[io_addr[5:2]][15 : 8] <= uio_in; end + 2'h2: begin register_file[io_addr[5:2]][23 : 16] <= uio_in; end + 2'h3: begin register_file[io_addr[5:2]][31 : 24] <= uio_in; end + endcase + end endcase end else begin case (io_addr) - 0: begin io_out[7 : 0] <= 8'h0; end + 63: begin io_out <= 8'h0; end - 4: begin io_out <= W_reg[ 7 : 0]; end - 5: begin io_out <= W_reg[15 : 8]; end - 6: begin io_out <= W_reg[23 : 16]; end - 7: begin io_out <= W_reg[31 : 24]; end - - 8: begin io_out <= K_reg[ 7 : 0]; end - 9: begin io_out <= K_reg[15 : 8]; end - 10: begin io_out <= K_reg[23 : 16]; end - 11: begin io_out <= K_reg[31 : 24]; end - - 32: begin io_out <= A_reg[ 7 : 0]; end - 33: begin io_out <= A_reg[15 : 8]; end - 34: begin io_out <= A_reg[23 : 16]; end - 35: begin io_out <= A_reg[31 : 24]; end - - 36: begin io_out <= B_reg[ 7 : 0]; end - 37: begin io_out <= B_reg[15 : 8]; end - 38: begin io_out <= B_reg[23 : 16]; end - 39: begin io_out <= B_reg[31 : 24]; end - - 40: begin io_out <= C_reg[ 7 : 0]; end - 41: begin io_out <= C_reg[15 : 8]; end - 42: begin io_out <= C_reg[23 : 16]; end - 43: begin io_out <= C_reg[31 : 24]; end - - 44: begin io_out <= D_reg[ 7 : 0]; end - 45: begin io_out <= D_reg[15 : 8]; end - 46: begin io_out <= D_reg[23 : 16]; end - 47: begin io_out <= D_reg[31 : 24]; end - - 48: begin io_out <= E_reg[ 7 : 0]; end - 49: begin io_out <= E_reg[15 : 8]; end - 50: begin io_out <= E_reg[23 : 16]; end - 51: begin io_out <= E_reg[31 : 24]; end - - 52: begin io_out <= F_reg[ 7 : 0]; end - 53: begin io_out <= F_reg[15 : 8]; end - 54: begin io_out <= F_reg[23 : 16]; end - 55: begin io_out <= F_reg[31 : 24]; end - - 56: begin io_out <= G_reg[ 7 : 0]; end - 57: begin io_out <= G_reg[15 : 8]; end - 58: begin io_out <= G_reg[23 : 16]; end - 59: begin io_out <= G_reg[31 : 24]; end - - 60: begin io_out <= H_reg[ 7 : 0]; end - 61: begin io_out <= H_reg[15 : 8]; end - 62: begin io_out <= H_reg[23 : 16]; end - 63: begin io_out <= H_reg[31 : 24]; end + default: begin + case (io_addr[1:0]) + 2'h0: begin io_out <= register_file[io_addr[5:2]][7 : 0]; end + 2'h1: begin io_out <= register_file[io_addr[5:2]][15 : 8]; end + 2'h2: begin io_out <= register_file[io_addr[5:2]][23 : 16]; end + 2'h3: begin io_out <= register_file[io_addr[5:2]][31 : 24]; end + endcase + end endcase end end