diff --git a/bsp/rp2040/m_default/cdc_uart.c b/bsp/rp2040/m_default/cdc_uart.c
index 500477d..1f8b6fd 100644
--- a/bsp/rp2040/m_default/cdc_uart.c
+++ b/bsp/rp2040/m_default/cdc_uart.c
@@ -35,11 +35,16 @@
 
 static uint8_t rx_buf[CFG_TUD_CDC_RX_BUFSIZE];
 static uint8_t tx_buf[CFG_TUD_CDC_TX_BUFSIZE];
+static bool hwflow = false;
+static int lc_brate = PINOUT_UART_BAUDRATE,
+           lc_data = 8, lc_parity = 0, lc_stop = 1;
 
 void cdc_uart_init(void) {
     gpio_set_function(PINOUT_UART_TX, GPIO_FUNC_UART);
     gpio_set_function(PINOUT_UART_RX, GPIO_FUNC_UART);
-    uart_init(PINOUT_UART_INTERFACE, PINOUT_UART_BAUDRATE);
+    uart_init(PINOUT_UART_INTERFACE, lc_brate/*PINOUT_UART_BAUDRATE*/);
+    uart_set_hw_flow(PINOUT_UART_INTERFACE, hwflow, hwflow);
+    uart_set_format(PINOUT_UART_INTERFACE, lc_data, lc_stop, lc_parity);
 
     bi_decl(bi_2pins_with_func(PINOUT_UART_TX, PINOUT_UART_RX, GPIO_FUNC_UART));
 }
@@ -71,7 +76,11 @@ void cdc_uart_task(void) {
     }
 }
 
+bool cdc_uart_get_hwflow(void) {
+    return hwflow;
+}
 bool cdc_uart_set_hwflow(bool enable) {
+    hwflow = enable;
     uart_set_hw_flow(PINOUT_UART_INTERFACE, enable, enable);
     return true;
 }
diff --git a/bsp/rp2040/m_sump/sump_hw.c b/bsp/rp2040/m_sump/sump_hw.c
index a9bcc1a..92f03c0 100644
--- a/bsp/rp2040/m_sump/sump_hw.c
+++ b/bsp/rp2040/m_sump/sump_hw.c
@@ -57,6 +57,8 @@ static uint32_t pio_prog_offset;
 static uint32_t dma_curr_idx = 0;
 static uint32_t oldprio;
 
+static bool overclock = false;
+
 uint32_t sump_hw_get_sysclk(void) { return clock_get_hz(clk_sys); }
 
 void sump_hw_get_cpu_name(char cpu[32]) {
@@ -302,6 +304,12 @@ void sump_hw_capture_stop(void) {
 }
 
 void sump_hw_init(void) {
+    // TODO: make this configurable
+    if (overclock) {
+        vreg_set_voltage(VREG_VOLTAGE_1_15);
+        set_sys_clock_khz(200000, true);
+    }
+
     // claim DMA channels
     dma_claim_mask(SUMP_DMA_MASK);
 
@@ -337,10 +345,6 @@ void sump_hw_init(void) {
 }
 
 void sump_hw_stop(void) {
-    // TODO: make this configurable
-    vreg_set_voltage(VREG_VOLTAGE_1_15);
-    set_sys_clock_khz(200000, true);
-
     // IRQ and PIO fast stop
     irq_set_enabled(SAMPLING_DMA_IRQ, false);
     pio_sm_set_enabled(SAMPLING_PIO, SAMPLING_PIO_SM, false);
@@ -360,7 +364,6 @@ void sump_hw_stop(void) {
 }
 
 void sump_hw_deinit(void) {
-    // TODO: make this configurable
     set_sys_clock_khz(133333, false);
     vreg_set_voltage(VREG_VOLTAGE_DEFAULT);
 
@@ -379,3 +382,19 @@ void sump_hw_deinit(void) {
     for (uint32_t i = SUMP_DMA_CH_FIRST; i <= SUMP_DMA_CH_LAST; ++i) dma_channel_unclaim(i);
 }
 
+uint8_t sump_hw_get_overclock(void) {
+    return overclock ? 1 : 0;
+}
+void sump_hw_set_overclock(uint8_t v) {
+    overclock = v != 0;
+
+    if (overclock) {
+        // TODO: make this configurable
+        vreg_set_voltage(VREG_VOLTAGE_1_15);
+        set_sys_clock_khz(200000, true);
+    } else {
+        set_sys_clock_khz(133333, false);
+        vreg_set_voltage(VREG_VOLTAGE_DEFAULT);
+    }
+}
+
diff --git a/src/m_default/_default.c b/src/m_default/_default.c
index c67a551..ad20b39 100644
--- a/src/m_default/_default.c
+++ b/src/m_default/_default.c
@@ -151,10 +151,16 @@ static void handle_cmd_cb(uint8_t cmd) {
         break;
     case mdef_cmd_uart_flowcnt:
 #ifdef DBOARD_HAS_UART
-        if (cdc_uart_set_hwflow(vnd_cfg_read_byte() != 0))
-            vnd_cfg_write_resp(cfg_resp_ok, 0, NULL);
-        else
-            vnd_cfg_write_str(cfg_resp_illcmd, "UART flow control setting not supported on this device");
+        resp = vnd_cfg_read_byte();
+        if (resp == 0xc3) {
+            resp = cdc_uart_get_hwflow() ? 1 : 0;
+            vnd_cfg_write_resp(cfg_resp_ok, 1, &resp);
+        } else {
+            if (cdc_uart_set_hwflow(resp != 0))
+                vnd_cfg_write_resp(cfg_resp_ok, 0, NULL);
+            else
+                vnd_cfg_write_str(cfg_resp_illcmd, "UART flow control setting not supported on this device");
+        }
 #else
         vnd_cfg_write_str(cfg_resp_illcmd, "UART not implemented on this device");
 #endif
diff --git a/src/m_default/cdc.h b/src/m_default/cdc.h
index 469e784..75b3d54 100644
--- a/src/m_default/cdc.h
+++ b/src/m_default/cdc.h
@@ -9,6 +9,7 @@
 void cdc_uart_init(void);
 void cdc_uart_deinit(void);
 void cdc_uart_task(void);
+bool cdc_uart_get_hwflow(void);
 bool cdc_uart_set_hwflow(bool enable);
 uint32_t cdc_uart_set_coding(uint32_t brate,
         uint8_t stop, uint8_t parity, uint8_t data);
diff --git a/src/m_sump/_sump.c b/src/m_sump/_sump.c
index c42baeb..51d1f1d 100644
--- a/src/m_sump/_sump.c
+++ b/src/m_sump/_sump.c
@@ -11,7 +11,11 @@
 /* CDC SUMP */
 #include "m_sump/sump.h"
 
-enum m_default_feature {
+enum m_sump_cmds {
+    msump_cmd_getovclk = mode_cmd__specific,
+    msump_cmd_setovclk
+};
+enum m_sump_feature {
     msump_feat_sump      = 1<<0,
 };
 
@@ -63,6 +67,14 @@ static void handle_cmd_cb(uint8_t cmd) {
 #endif
         vnd_cfg_write_resp(cfg_resp_ok, 1, &resp);
         break;
+    case msump_cmd_getovclk:
+        resp = sump_hw_get_overclock();
+        vnd_cfg_write_resp(cfg_resp_ok, 1, &resp);
+        break;
+    case msump_cmd_setovclk:
+        sump_hw_set_overclock(vnd_cfg_read_byte());
+        vnd_cfg_write_resp(cfg_resp_ok, 0, NULL);
+        break;
     default:
         vnd_cfg_write_strf(cfg_resp_illcmd, "unknown mode4 command %02x", cmd);
         break;
diff --git a/src/m_sump/sump.h b/src/m_sump/sump.h
index 6b582ba..60ae8b6 100644
--- a/src/m_sump/sump.h
+++ b/src/m_sump/sump.h
@@ -85,4 +85,7 @@ void sump_hw_capture_start(uint8_t width, int flags, uint32_t chunk_size, uint8_
 void sump_hw_capture_stop(void);
 void sump_hw_stop(void);
 
+uint8_t sump_hw_get_overclock(void);
+void sump_hw_set_overclock(uint8_t v);
+
 #endif