blackmagic/hardware/blackmagic.sch

v 20100214 2
C 51600 50700 1 0 0 EMBEDDED3.3V-plus-1.sym
[
P 51800 50700 51800 50900 1 0 0
{
T 51850 50750 5 6 0 1 0 0 1
pinnumber=1
T 51850 50750 5 6 0 0 0 0 1
pinseq=1
T 51850 50750 5 6 0 1 0 0 1
pinlabel=1
T 51850 50750 5 6 0 1 0 0 1
pintype=pwr
}
L 51650 50900 51950 50900 3 0 0 0 -1 -1
T 51675 50950 9 8 1 0 0 0 1
+3.3V
T 51900 50700 8 8 0 0 0 0 1
net=+3.3V:1
]
C 41900 54200 1 0 0 EMBEDDED5V-plus-1.sym
[
P 42100 54200 42100 54400 1 0 0
{
T 42150 54250 5 6 0 1 0 0 1
pinnumber=1
T 42150 54250 5 6 0 0 0 0 1
pinseq=1
T 42150 54250 5 6 0 1 0 0 1
pinlabel=1
T 42150 54250 5 6 0 1 0 0 1
pintype=pwr
}
L 41950 54400 42250 54400 3 0 0 0 -1 -1
T 41975 54450 9 8 1 0 0 0 1
+5V
T 42200 54200 8 8 0 0 0 0 1
net=+5V:1
]
C 42600 53300 1 0 0 EMBEDDEDUSBLC6-2.sym
[
B 43000 53300 1000 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 43000 54350 5 10 0 0 0 0 1
device=USBLC6-2
P 43000 53900 42700 53900 1 0 1
{
T 42900 53950 5 8 1 1 0 6 1
pinnumber=1
T 42900 53850 5 8 0 1 0 8 1
pinseq=1
T 43050 53900 5 8 0 1 0 2 1
pintype=io
T 43050 53900 9 8 1 1 0 1 1
pinlabel=IO1
}
P 43000 53700 42700 53700 1 0 1
{
T 42900 53750 5 8 1 1 0 6 1
pinnumber=2
T 42900 53650 5 8 0 1 0 8 1
pinseq=2
T 43050 53700 5 8 0 1 0 2 1
pintype=pwr
T 43050 53700 9 8 1 1 0 1 1
pinlabel=GND
}
P 43000 53500 42700 53500 1 0 1
{
T 42900 53550 5 8 1 1 0 6 1
pinnumber=3
T 42900 53450 5 8 0 1 0 8 1
pinseq=3
T 43050 53500 5 8 0 1 0 2 1
pintype=io
T 43050 53500 9 8 1 1 0 1 1
pinlabel=IO2
}
P 44300 53500 44000 53500 1 0 0
{
T 44100 53550 5 8 1 1 0 0 1
pinnumber=4
T 44100 53450 5 8 0 1 0 2 1
pinseq=4
T 43950 53500 5 8 0 1 0 8 1
pintype=io
T 43950 53500 9 8 1 1 0 7 1
pinlabel=IO2
}
P 44300 53700 44000 53700 1 0 0
{
T 44100 53750 5 8 1 1 0 0 1
pinnumber=5
T 44100 53650 5 8 0 1 0 2 1
pinseq=5
T 43950 53700 5 8 0 1 0 8 1
pintype=pwr
T 43950 53700 9 8 1 1 0 7 1
pinlabel=VBUS
}
P 44300 53900 44000 53900 1 0 0
{
T 44100 53950 5 8 1 1 0 0 1
pinnumber=6
T 44100 53850 5 8 0 1 0 2 1
pinseq=6
T 43950 53900 5 8 0 1 0 8 1
pintype=io
T 43950 53900 9 8 1 1 0 7 1
pinlabel=IO1
}
T 44100 54200 8 10 0 1 0 6 1
refdes=U?
T 43000 54750 5 10 0 0 0 0 1
footprint=SOT666
T 43000 54550 5 10 0 0 0 0 1
numslots=0
T 43000 54950 5 10 0 0 0 0 1
description=Very low capacitance ESD protection
T 43000 54150 9 8 1 0 0 0 1
USBLC6-2
]
{
T 43000 54350 5 10 0 0 0 0 1
device=USBLC6-2
T 44000 54200 5 10 1 1 0 6 1
refdes=U2
T 43000 54750 5 10 0 0 0 0 1
footprint=SOT666
T 42600 53300 5 10 0 0 0 0 1
value=USBLC6-2
}
N 40300 54000 40100 54000 4
N 40100 54000 40100 53000 4
C 40000 52700 1 0 0 EMBEDDEDgnd-1.sym
[
P 40100 52800 40100 53000 1 0 1
{
T 40158 52861 5 4 0 1 0 0 1
pinnumber=1
T 40158 52861 5 4 0 0 0 0 1
pinseq=1
T 40158 52861 5 4 0 1 0 0 1
pinlabel=1
T 40158 52861 5 4 0 1 0 0 1
pintype=pwr
}
L 40000 52800 40200 52800 3 0 0 0 -1 -1
L 40055 52750 40145 52750 3 0 0 0 -1 -1
L 40080 52710 40120 52710 3 0 0 0 -1 -1
T 40300 52750 8 10 0 0 0 0 1
net=GND:1
]
N 40300 53800 40100 53800 4
N 40300 53400 40100 53400 4
N 40300 53200 40100 53200 4
C 42000 52700 1 0 0 EMBEDDEDgnd-1.sym
[
P 42100 52800 42100 53000 1 0 1
{
T 42158 52861 5 4 0 1 0 0 1
pinnumber=1
T 42158 52861 5 4 0 0 0 0 1
pinseq=1
T 42158 52861 5 4 0 1 0 0 1
pinlabel=1
T 42158 52861 5 4 0 1 0 0 1
pintype=pwr
}
L 42000 52800 42200 52800 3 0 0 0 -1 -1
L 42055 52750 42145 52750 3 0 0 0 -1 -1
L 42080 52710 42120 52710 3 0 0 0 -1 -1
T 42300 52750 8 10 0 0 0 0 1
net=GND:1
]
N 41900 53200 42100 53200 4
N 42100 53200 42100 53000 4
N 41900 54000 42100 54000 4
N 42100 54000 42100 54200 4
N 42700 53700 42500 53700 4
N 42500 53700 42500 53000 4
C 42400 52700 1 0 0 EMBEDDEDgnd-1.sym
[
P 42500 52800 42500 53000 1 0 1
{
T 42558 52861 5 4 0 1 0 0 1
pinnumber=1
T 42558 52861 5 4 0 0 0 0 1
pinseq=1
T 42558 52861 5 4 0 1 0 0 1
pinlabel=1
T 42558 52861 5 4 0 1 0 0 1
pintype=pwr
}
L 42400 52800 42600 52800 3 0 0 0 -1 -1
L 42455 52750 42545 52750 3 0 0 0 -1 -1
L 42480 52710 42520 52710 3 0 0 0 -1 -1
T 42700 52750 8 10 0 0 0 0 1
net=GND:1
]
N 41900 53600 42200 53600 4
N 42200 53600 42200 53500 4
N 42200 53500 42700 53500 4
N 41900 53800 42200 53800 4
N 42200 53800 42200 53900 4
N 42200 53900 42700 53900 4
C 44300 54100 1 0 0 EMBEDDED5V-plus-1.sym
[
P 44500 54100 44500 54300 1 0 0
{
T 44550 54150 5 6 0 1 0 0 1
pinnumber=1
T 44550 54150 5 6 0 0 0 0 1
pinseq=1
T 44550 54150 5 6 0 1 0 0 1
pinlabel=1
T 44550 54150 5 6 0 1 0 0 1
pintype=pwr
}
L 44350 54300 44650 54300 3 0 0 0 -1 -1
T 44375 54350 9 8 1 0 0 0 1
+5V
T 44600 54100 8 8 0 0 0 0 1
net=+5V:1
]
N 44300 53700 44500 53700 4
N 44500 53700 44500 54100 4
N 45200 53900 45600 53900 4
{
T 45700 53900 5 10 1 1 0 1 1
netname=USB_DM
}
C 54600 50700 1 180 1 EMBEDDEDheader20.sym
[
B 54900 48600 400 2000 3 0 0 0 -1 -1 0 0 -1 -1 -1 -1
T 54900 48350 5 10 0 0 180 6 1
device=HEADER20
T 54900 48500 2 10 0 1 180 6 1
refdes=U?
P 54900 48700 54600 48700 1 0 1
{
T 54836 48650 5 8 1 1 180 0 1
pinnumber=1
T 54836 48650 5 8 0 0 180 0 1
pinseq=1
T 54836 48650 5 8 0 1 180 0 1
pinlabel=1
T 54836 48650 5 8 0 1 180 0 1
pintype=pas
}
P 55300 48700 55600 48700 1 0 1
{
T 55400 48650 5 8 1 1 180 6 1
pinnumber=2
T 55400 48650 5 8 0 0 180 6 1
pinseq=2
T 55400 48650 5 8 0 1 180 6 1
pinlabel=2
T 55400 48650 5 8 0 1 180 6 1
pintype=pas
}
P 54900 48900 54600 48900 1 0 1
{
T 54820 48850 5 8 1 1 180 0 1
pinnumber=3
T 54820 48850 5 8 0 0 180 0 1
pinseq=3
T 54820 48850 5 8 0 1 180 0 1
pinlabel=3
T 54820 48850 5 8 0 1 180 0 1
pintype=pas
}
P 55300 48900 55600 48900 1 0 1
{
T 55400 48850 5 8 1 1 180 6 1
pinnumber=4
T 55400 48850 5 8 0 0 180 6 1
pinseq=4
T 55400 48850 5 8 0 1 180 6 1
pinlabel=4
T 55400 48850 5 8 0 1 180 6 1
pintype=pas
}
P 54900 49100 54600 49100 1 0 1
{
T 54820 49050 5 8 1 1 180 0 1
pinnumber=5
T 54820 49050 5 8 0 0 180 0 1
pinseq=5
T 54820 49050 5 8 0 1 180 0 1
pinlabel=5
T 54820 49050 5 8 0 1 180 0 1
pintype=pas
}
P 55300 49100 55600 49100 1 0 1
{
T 55400 49050 5 8 1 1 180 6 1
pinnumber=6
T 55400 49050 5 8 0 0 180 6 1
pinseq=6
T 55400 49050 5 8 0 1 180 6 1
pinlabel=6
T 55400 49050 5 8 0 1 180 6 1
pintype=pas
}
P 54900 49300 54600 49300 1 0 1
{
T 54820 49250 5 8 1 1 180 0 1
pinnumber=7
T 54820 49250 5 8 0 0 180 0 1
pinseq=7
T 54820 49250 5 8 0 1 180 0 1
pinlabel=7
T 54820 49250 5 8 0 1 180 0 1
pintype=pas
}
P 55300 49300 55600 49300 1 0 1
{
T 55400 49250 5 8 1 1 180 6 1
pinnumber=8
T 55400 49250 5 8 0 0 180 6 1
pinseq=8
T 55400 49250 5 8 0 1 180 6 1
pinlabel=8
T 55400 49250 5 8 0 1 180 6 1
pintype=pas
}
P 54900 49500 54600 49500 1 0 1
{
T 54796 49450 5 8 1 1 180 0 1
pinnumber=9
T 54796 49450 5 8 0 0 180 0 1
pinseq=9
T 54796 49450 5 8 0 1 180 0 1
pinlabel=9
T 54796 49450 5 8 0 1 180 0 1
pintype=pas
}
P 55300 49500 55600 49500 1 0 1
{
T 55400 49450 5 8 1 1 180 6 1
pinnumber=10
T 55400 49450 5 8 0 0 180 6 1
pinseq=10
T 55400 49450 5 8 0 1 180 6 1
pinlabel=10
T 55400 49450 5 8 0 1 180 6 1
pintype=pas
}
P 54900 49700 54600 49700 1 0 1
{
T 54822 49650 5 8 1 1 180 0 1
pinnumber=11
T 54822 49650 5 8 0 0 180 0 1
pinseq=11
T 54822 49650 5 8 0 1 180 0 1
pinlabel=11
T 54822 49650 5 8 0 1 180 0 1
pintype=pas
}
P 55300 49700 55600 49700 1 0 1
{
T 55400 49650 5 8 1 1 180 6 1
pinnumber=12
T 55400 49650 5 8 0 0 180 6 1
pinseq=12
T 55400 49650 5 8 0 1 180 6 1
pinlabel=12
T 55400 49650 5 8 0 1 180 6 1
pintype=pas
}
P 54900 49900 54600 49900 1 0 1
{
T 54806 49850 5 8 1 1 180 0 1
pinnumber=13
T 54806 49850 5 8 0 0 180 0 1
pinseq=13
T 54806 49850 5 8 0 1 180 0 1
pinlabel=13
T 54806 49850 5 8 0 1 180 0 1
pintype=pas
}
P 55300 49900 55600 49900 1 0 1
{
T 55400 49850 5 8 1 1 180 6 1
pinnumber=14
T 55400 49850 5 8 0 0 180 6 1
pinseq=14
T 55400 49850 5 8 0 1 180 6 1
pinlabel=14
T 55400 49850 5 8 0 1 180 6 1
pintype=pas
}
P 54900 50100 54600 50100 1 0 1
{
T 54806 50050 5 8 1 1 180 0 1
pinnumber=15
T 54806 50050 5 8 0 0 180 0 1
pinseq=15
T 54806 50050 5 8 0 1 180 0 1
pinlabel=15
T 54806 50050 5 8 0 1 180 0 1
pintype=pas
}
P 55300 50100 55600 50100 1 0 1
{
T 55400 50050 5 8 1 1 180 6 1
pinnumber=16
T 55400 50050 5 8 0 0 180 6 1
pinseq=16
T 55400 50050 5 8 0 1 180 6 1
pinlabel=16
T 55400 50050 5 8 0 1 180 6 1
pintype=pas
}
P 54900 50300 54600 50300 1 0 1
{
T 54806 50250 5 8 1 1 180 0 1
pinnumber=17
T 54806 50250 5 8 0 0 180 0 1
pinseq=17
T 54806 50250 5 8 0 1 180 0 1
pinlabel=17
T 54806 50250 5 8 0 1 180 0 1
pintype=pas
}
P 55300 50300 55600 50300 1 0 1
{
T 55400 50250 5 8 1 1 180 6 1
pinnumber=18
T 55400 50250 5 8 0 0 180 6 1
pinseq=18
T 55400 50250 5 8 0 1 180 6 1
pinlabel=18
T 55400 50250 5 8 0 1 180 6 1
pintype=pas
}
P 54900 50500 54600 50500 1 0 1
{
T 54832 50450 5 8 1 1 180 0 1
pinnumber=19
T 54832 50450 5 8 0 0 180 0 1
pinseq=19
T 54832 50450 5 8 0 1 180 0 1
pinlabel=19
T 54832 50450 5 8 0 1 180 0 1
pintype=pas
}
P 55300 50500 55600 50500 1 0 1
{
T 55400 50450 5 8 1 1 180 6 1
pinnumber=20
T 55400 50450 5 8 0 0 180 6 1
pinseq=20
T 55400 50450 5 8 0 1 180 6 1
pinlabel=20
T 55400 50450 5 8 0 1 180 6 1
pintype=pas
}
L 55100 48600 55100 50600 3 0 0 0 -1 -1
L 54900 50400 55300 50400 3 0 0 0 -1 -1
L 54900 50200 55300 50200 3 0 0 0 -1 -1
L 54900 50000 55300 50000 3 0 0 0 -1 -1
L 54900 49800 55300 49800 3 0 0 0 -1 -1
L 54900 49600 55300 49600 3 0 0 0 -1 -1
L 54900 49400 55300 49400 3 0 0 0 -1 -1
L 54900 49200 55300 49200 3 0 0 0 -1 -1
L 54900 49000 55300 49000 3 0 0 0 -1 -1
L 54900 48800 55300 48800 3 0 0 0 -1 -1
]
{
T 54900 48350 5 10 0 0 180 6 1
device=HEADER20
T 55000 48500 5 10 1 1 180 6 1
refdes=J1
T 54600 50700 5 10 0 0 0 0 1
value=Box Right Angle
T 54600 50700 5 10 0 0 0 0 1
footprint=HEADER20
}
N 53800 50300 54200 50300 4
N 54200 48700 54200 50500 4
N 55600 50500 56000 50500 4
N 56000 50500 56000 48700 4
C 55900 48400 1 0 0 EMBEDDEDgnd-1.sym
[
P 56000 48500 56000 48700 1 0 1
{
T 56058 48561 5 4 0 1 0 0 1
pinnumber=1
T 56058 48561 5 4 0 0 0 0 1
pinseq=1
T 56058 48561 5 4 0 1 0 0 1
pinlabel=1
T 56058 48561 5 4 0 1 0 0 1
pintype=pwr
}
L 55900 48500 56100 48500 3 0 0 0 -1 -1
L 55955 48450 56045 48450 3 0 0 0 -1 -1
L 55980 48410 56020 48410 3 0 0 0 -1 -1
T 56200 48450 8 10 0 0 0 0 1
net=GND:1
]
N 55600 50300 56000 50300 4
N 55600 50100 56000 50100 4
N 55600 49900 56000 49900 4
N 55600 49700 56000 49700 4
N 55600 49500 56000 49500 4
N 55600 49300 56400 49300 4
{
T 56500 49300 5 10 1 1 0 1 1
netname=BOOT0
}
N 55600 49100 56400 49100 4
{
T 56500 49100 5 10 1 1 0 1 1
netname=U1TX
}
N 55600 48900 56400 48900 4
{
T 56500 48900 5 10 1 1 0 1 1
netname=U1RX
}
N 54600 50100 53800 50100 4
N 54600 49900 53800 49900 4
N 54600 49500 53800 49500 4
N 54600 49300 53800 49300 4
N 54600 49100 53800 49100 4
C 51700 48200 1 0 0 EMBEDDEDgnd-1.sym
[
P 51800 48300 51800 48500 1 0 1
{
T 51858 48361 5 4 0 1 0 0 1
pinnumber=1
T 51858 48361 5 4 0 0 0 0 1
pinseq=1
T 51858 48361 5 4 0 1 0 0 1
pinlabel=1
T 51858 48361 5 4 0 1 0 0 1
pintype=pwr
}
L 51700 48300 51900 48300 3 0 0 0 -1 -1
L 51755 48250 51845 48250 3 0 0 0 -1 -1
L 51780 48210 51820 48210 3 0 0 0 -1 -1
T 52000 48250 8 10 0 0 0 0 1
net=GND:1
]
N 52000 48700 51800 48700 4
N 51600 49300 52000 49300 4
{
T 51500 49300 5 10 1 1 0 7 1
netname=xTMS
}
N 51800 48500 51800 49700 4
N 52000 49100 51600 49100 4
{
T 51500 49100 5 10 1 1 0 7 1
netname=xTDI
}
N 51800 50700 51800 50300 4
N 51800 50300 52000 50300 4
N 52000 49500 51600 49500 4
{
T 51500 49500 5 10 1 1 0 7 1
netname=xTCK
}
N 52000 49900 51600 49900 4
{
T 51500 49900 5 10 1 1 0 7 1
netname=xTDO
}
N 52000 48900 51600 48900 4
{
T 51500 48900 5 10 1 1 0 7 1
netname=xnTRST
}
N 52000 50100 51600 50100 4
{
T 51500 50100 5 10 1 1 0 7 1
netname=xnSRST
}
C 49800 53300 1 0 0 EMBEDDEDNCP1117.sym
[
T 50200 53900 9 8 1 0 0 0 1
IN
T 50748 53900 9 8 1 0 0 0 1
OUT
T 50600 54300 9 8 1 0 0 3 1
NCP1117
B 50100 53600 1000 600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 51400 54800 5 10 0 0 0 0 1
device=NCP1117
T 50456 53701 9 8 1 0 0 0 1
GND
P 50100 53900 49800 53900 1 0 1
{
T 49900 53950 5 8 1 1 0 0 1
pinnumber=3
T 49900 53950 5 8 0 0 0 0 1
pinseq=3
}
P 50600 53300 50600 53600 1 0 0
{
T 50500 53400 5 8 1 1 0 0 1
pinnumber=1
T 50500 53400 5 8 0 0 0 0 1
pinseq=1
}
P 51100 53900 51400 53900 1 0 1
{
T 51230 53950 5 8 1 1 0 0 1
pinnumber=4
T 51230 53950 5 8 0 0 0 0 1
pinseq=4
}
T 51200 54300 8 10 0 1 0 6 1
refdes=U?
T 51400 54600 5 10 0 0 0 0 1
pins=3
T 51400 54200 5 10 0 0 0 0 1
net=GND:1
T 51400 54400 5 10 0 0 0 0 1
footprint=SOT223
]
{
T 51200 55000 5 10 0 0 0 0 1
device=NCP1117
T 51200 54300 5 10 1 1 0 6 1
refdes=U3
T 51200 54600 5 10 0 0 0 0 1
footprint=SOT223
T 49600 53500 5 10 0 0 0 0 1
net=VDD:4
T 49800 53300 5 10 0 0 0 0 1
value=NCP1117ST33T3G
}
C 48600 53900 1 0 0 EMBEDDED5V-plus-1.sym
[
P 48800 53900 48800 54100 1 0 0
{
T 48850 53950 5 6 0 1 0 0 1
pinnumber=1
T 48850 53950 5 6 0 0 0 0 1
pinseq=1
T 48850 53950 5 6 0 1 0 0 1
pinlabel=1
T 48850 53950 5 6 0 1 0 0 1
pintype=pwr
}
L 48650 54100 48950 54100 3 0 0 0 -1 -1
T 48675 54150 9 8 1 0 0 0 1
+5V
T 48900 53900 8 8 0 0 0 0 1
net=+5V:1
]
N 48800 53900 49800 53900 4
C 48700 52900 1 0 0 EMBEDDEDgnd-1.sym
[
P 48800 53000 48800 53200 1 0 1
{
T 48858 53061 5 4 0 1 0 0 1
pinnumber=1
T 48858 53061 5 4 0 0 0 0 1
pinseq=1
T 48858 53061 5 4 0 1 0 0 1
pinlabel=1
T 48858 53061 5 4 0 1 0 0 1
pintype=pwr
}
L 48700 53000 48900 53000 3 0 0 0 -1 -1
L 48755 52950 48845 52950 3 0 0 0 -1 -1
L 48780 52910 48820 52910 3 0 0 0 -1 -1
T 49000 52950 8 10 0 0 0 0 1
net=GND:1
]
N 48800 53200 58000 53200 4
{
T 58100 53200 5 10 1 1 0 1 1
netname=VSS
}
N 50600 53300 50600 53200 4
N 51400 53900 58000 53900 4
{
T 58100 53900 5 10 1 1 0 1 1
netname=VDD
}
C 51500 53900 1 0 0 EMBEDDED3.3V-plus-1.sym
[
P 51700 53900 51700 54100 1 0 0
{
T 51750 53950 5 6 0 1 0 0 1
pinnumber=1
T 51750 53950 5 6 0 0 0 0 1
pinseq=1
T 51750 53950 5 6 0 1 0 0 1
pinlabel=1
T 51750 53950 5 6 0 1 0 0 1
pintype=pwr
}
L 51550 54100 51850 54100 3 0 0 0 -1 -1
T 51575 54150 9 8 1 0 0 0 1
+3.3V
T 51800 53900 8 8 0 0 0 0 1
net=+3.3V:1
]
C 55000 47200 1 0 0 EMBEDDEDgnd-1.sym
[
P 55100 47300 55100 47500 1 0 1
{
T 55158 47361 5 4 0 1 0 0 1
pinnumber=1
T 55158 47361 5 4 0 0 0 0 1
pinseq=1
T 55158 47361 5 4 0 1 0 0 1
pinlabel=1
T 55158 47361 5 4 0 1 0 0 1
pintype=pwr
}
L 55000 47300 55200 47300 3 0 0 0 -1 -1
L 55055 47250 55145 47250 3 0 0 0 -1 -1
L 55080 47210 55120 47210 3 0 0 0 -1 -1
T 55300 47250 8 10 0 0 0 0 1
net=GND:1
]
C 55600 47200 1 0 0 EMBEDDEDgnd-1.sym
[
P 55700 47300 55700 47500 1 0 1
{
T 55758 47361 5 4 0 1 0 0 1
pinnumber=1
T 55758 47361 5 4 0 0 0 0 1
pinseq=1
T 55758 47361 5 4 0 1 0 0 1
pinlabel=1
T 55758 47361 5 4 0 1 0 0 1
pintype=pwr
}
L 55600 47300 55800 47300 3 0 0 0 -1 -1
L 55655 47250 55745 47250 3 0 0 0 -1 -1
L 55680 47210 55720 47210 3 0 0 0 -1 -1
T 55900 47250 8 10 0 0 0 0 1
net=GND:1
]
C 40200 53000 1 0 0 EMBEDDEDUSB_MINI_B.sym
[
B 40600 53000 1000 1200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 40600 54450 5 10 0 0 0 0 1
device=USB_MINI_B
P 40600 53800 40300 53800 1 0 1
{
T 40500 53850 5 8 1 1 0 6 1
pinnumber=7
T 40500 53750 5 8 0 1 0 8 1
pinseq=7
T 40650 53800 5 8 0 1 0 2 1
pintype=pwr
T 40650 53800 9 8 1 1 0 1 1
pinlabel=GND
}
P 40600 53400 40300 53400 1 0 1
{
T 40500 53450 5 8 1 1 0 6 1
pinnumber=8
T 40500 53350 5 8 0 1 0 8 1
pinseq=8
T 40650 53400 5 8 0 1 0 2 1
pintype=pwr
T 40650 53400 9 8 1 1 0 1 1
pinlabel=GND
}
P 40600 53200 40300 53200 1 0 1
{
T 40500 53250 5 8 1 1 0 6 1
pinnumber=9
T 40500 53150 5 8 0 1 0 8 1
pinseq=9
T 40650 53200 5 8 0 1 0 2 1
pintype=pwr
T 40650 53200 9 8 1 1 0 1 1
pinlabel=GND
}
P 41900 53200 41600 53200 1 0 0
{
T 41700 53250 5 8 1 1 0 0 1
pinnumber=5
T 41700 53150 5 8 0 1 0 2 1
pinseq=5
T 41550 53200 5 8 0 1 0 8 1
pintype=pwr
T 41550 53200 9 8 1 1 0 7 1
pinlabel=GND
}
P 41900 53400 41600 53400 1 0 0
{
T 41700 53450 5 8 1 1 0 0 1
pinnumber=4
T 41700 53350 5 8 0 1 0 2 1
pinseq=4
T 41550 53400 5 8 0 1 0 8 1
pintype=io
T 41550 53400 9 8 1 1 0 7 1
pinlabel=ID
}
P 41900 53600 41600 53600 1 0 0
{
T 41700 53650 5 8 1 1 0 0 1
pinnumber=3
T 41700 53550 5 8 0 1 0 2 1
pinseq=3
T 41550 53600 5 8 0 1 0 8 1
pintype=io
T 41550 53600 9 8 1 1 0 7 1
pinlabel=D+
}
T 41700 54300 8 10 0 1 0 6 1
refdes=U?
T 40600 54850 5 10 0 0 0 0 1
footprint=USB_MINI_B
T 40600 54650 5 10 0 0 0 0 1
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Copyright (C) 2011  Black Sphere Technologies.  Licensed CC-BY-SA.
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Revision 1.0 - First production release
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Drawn by: Gareth McMullin <gareth@blacksphere.co.nz>
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{
T 52900 53600 5 10 0 0 270 0 1
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T 52200 53550 5 8 1 1 90 4 1
refdes=C8
T 53100 53600 5 10 0 0 270 0 1
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T 52550 53550 5 8 1 1 90 5 1
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T 52200 53800 5 10 0 1 180 0 1
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C 52900 53800 1 270 0 EMBEDDEDcapacitor-np-small.sym
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T 53600 53600 5 10 0 0 270 0 1
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T 53100 53400 5 8 0 1 270 8 1
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P 53100 53800 53100 53700 1 0 0
{
T 53150 53650 5 8 0 1 270 6 1
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T 53050 53650 5 8 0 1 270 8 1
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T 53100 53600 9 8 0 1 270 0 1
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T 53100 53600 5 8 0 1 270 2 1
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{
T 53600 53600 5 10 0 0 270 0 1
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T 52900 53550 5 8 1 1 90 4 1
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T 53800 53600 5 10 0 0 270 0 1
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T 53250 53550 5 8 1 1 90 5 1
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T 52900 53800 5 10 0 1 180 0 1
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C 53600 53800 1 270 0 EMBEDDEDcapacitor-np-small.sym
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T 54000 53550 8 8 0 1 270 4 1
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{
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T 53800 53400 5 8 0 1 270 8 1
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P 53800 53800 53800 53700 1 0 0
{
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{
T 54300 53600 5 10 0 0 270 0 1
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T 53600 53550 5 8 1 1 90 4 1
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T 54500 53600 5 10 0 0 270 0 1
symversion=0.1
T 53950 53550 5 8 1 1 90 5 1
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T 53600 53800 5 10 0 1 180 0 1
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C 54300 53800 1 270 0 EMBEDDEDcapacitor-np-small.sym
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T 55000 53600 5 10 0 0 270 0 1
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{
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T 54500 53400 5 8 0 1 270 8 1
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P 54500 53800 54500 53700 1 0 0
{
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{
T 55000 53600 5 10 0 0 270 0 1
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T 54300 53550 5 8 1 1 90 4 1
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T 55200 53600 5 10 0 0 270 0 1
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T 54650 53550 5 8 1 1 90 5 1
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T 54300 53800 5 10 0 1 180 0 1
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C 55000 53800 1 270 0 EMBEDDEDcapacitor-np-small.sym
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T 55700 53600 5 10 0 0 270 0 1
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{
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T 55200 53400 9 8 0 1 270 6 1
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T 55200 53400 5 8 0 1 270 8 1
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P 55200 53800 55200 53700 1 0 0
{
T 55250 53650 5 8 0 1 270 6 1
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T 55150 53650 5 8 0 1 270 8 1
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T 55200 53600 9 8 0 1 270 0 1
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T 55200 53600 5 8 0 1 270 2 1
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{
T 55700 53600 5 10 0 0 270 0 1
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T 55000 53550 5 8 1 1 90 4 1
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T 55900 53600 5 10 0 0 270 0 1
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T 55350 53550 5 8 1 1 90 5 1
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T 55000 53800 5 10 0 1 180 0 1
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C 55700 53800 1 270 0 EMBEDDEDcapacitor-np-small.sym
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T 56800 53600 5 10 0 0 270 0 1
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T 57000 53600 5 10 0 0 270 0 1
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T 56100 53550 8 8 0 1 270 4 1
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T 56400 53600 5 10 0 0 270 0 1
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L 55900 53575 55900 53700 3 0 0 0 -1 -1
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{
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T 55900 53400 5 8 0 1 270 8 1
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P 55900 53800 55900 53700 1 0 0
{
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T 55850 53650 5 8 0 1 270 8 1
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{
T 56400 53600 5 10 0 0 270 0 1
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T 55700 53550 5 8 1 1 90 4 1
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T 56600 53600 5 10 0 0 270 0 1
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T 56050 53550 5 8 1 1 90 5 1
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T 55700 53800 5 10 0 1 180 0 1
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N 48800 53800 48800 53900 4
N 51700 53800 51700 53900 4
N 48800 53300 48800 53200 4
N 49500 53800 49500 53900 4
N 49500 53300 49500 53200 4
N 52400 53800 52400 53900 4
N 53100 53800 53100 53900 4
N 53100 53300 53100 53200 4
N 53800 53800 53800 53900 4
N 54500 53800 54500 53900 4
N 54500 53300 54500 53200 4
N 55200 53300 55200 53200 4
N 55900 53300 55900 53200 4
N 51700 53300 51700 53200 4
C 54200 44900 1 0 0 EMBEDDEDled-small.sym
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{
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P 54200 45000 54300 45000 1 0 0
{
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}
T 54300 45500 8 10 0 0 0 0 1
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T 54300 45100 8 8 0 1 0 4 1
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{
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T 54300 45500 5 10 0 0 0 0 1
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T 54200 44900 5 10 0 1 0 0 1
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T 54600 45050 5 8 1 1 0 0 1
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N 54700 45000 55300 45000 4
C 54200 44500 1 0 0 EMBEDDEDled-small.sym
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P 54200 44600 54300 44600 1 0 0
{
T 54300 44650 5 8 0 1 0 0 1
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}
T 54300 45100 8 10 0 0 0 0 1
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{
T 54300 44700 5 8 1 1 0 4 1
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T 54300 45100 5 10 0 0 0 0 1
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T 54200 44500 5 10 0 1 0 0 1
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N 54700 44600 55300 44600 4
C 54200 44100 1 0 0 EMBEDDEDled-small.sym
[
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{
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P 54200 44200 54300 44200 1 0 0
{
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}
T 54300 44700 8 10 0 0 0 0 1
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{
T 54300 44300 5 8 1 1 0 4 1
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T 54300 44700 5 10 0 0 0 0 1
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T 54200 44100 5 10 0 1 0 0 1
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N 54700 44200 55300 44200 4
C 54200 43700 1 0 0 EMBEDDEDled-small.sym
[
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{
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P 54200 43800 54300 43800 1 0 0
{
T 54300 43850 5 8 0 1 0 0 1
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}
T 54300 44300 8 10 0 0 0 0 1
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T 54300 43900 8 8 0 1 0 4 1
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{
T 54300 43900 5 8 1 1 0 4 1
refdes=D4
T 54300 44300 5 10 0 0 0 0 1
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T 54200 43700 5 10 0 1 0 0 1
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T 54600 43850 5 8 1 1 0 0 1
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N 54700 43800 55300 43800 4
C 53200 44900 1 0 0 EMBEDDEDresistor-small.sym
[
T 53450 45100 8 8 0 1 0 3 1
refdes=R?
T 53600 45250 5 10 0 0 0 0 1
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P 53200 45000 53300 45000 1 0 0
{
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P 53700 45000 53600 45000 1 0 0
{
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T 53700 45050 5 8 0 0 0 0 1
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{
T 53600 45250 5 10 0 0 0 0 1
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T 53250 45050 5 8 1 1 0 6 1
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T 53650 45050 5 8 1 1 0 0 1
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T 53200 44900 5 10 0 0 0 0 1
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N 53700 45000 54200 45000 4
C 53200 44500 1 0 0 EMBEDDEDresistor-small.sym
[
T 53450 44700 8 8 0 1 0 3 1
refdes=R?
T 53600 44850 5 10 0 0 0 0 1
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P 53200 44600 53300 44600 1 0 0
{
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P 53700 44600 53600 44600 1 0 0
{
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{
T 53600 44850 5 10 0 0 0 0 1
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T 53250 44650 5 8 1 1 0 6 1
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T 53650 44650 5 8 1 1 0 0 1
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T 53200 44500 5 10 0 0 0 0 1
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N 53700 44600 54200 44600 4
C 53200 44100 1 0 0 EMBEDDEDresistor-small.sym
[
T 53450 44300 8 8 0 1 0 3 1
refdes=R?
T 53600 44450 5 10 0 0 0 0 1
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P 53200 44200 53300 44200 1 0 0
{
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P 53700 44200 53600 44200 1 0 0
{
T 53700 44250 5 8 0 1 0 0 1
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T 53700 44250 5 8 0 0 0 0 1
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{
T 53600 44450 5 10 0 0 0 0 1
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T 53250 44250 5 8 1 1 0 6 1
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T 53650 44250 5 8 1 1 0 0 1
value=390E
T 53200 44100 5 10 0 0 0 0 1
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N 53700 44200 54200 44200 4
C 53200 43700 1 0 0 EMBEDDEDresistor-small.sym
[
T 53450 43900 8 8 0 1 0 3 1
refdes=R?
T 53600 44050 5 10 0 0 0 0 1
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B 53300 43750 300 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 53200 43800 53300 43800 1 0 0
{
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T 53300 43850 5 8 0 0 0 0 1
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T 53300 43850 5 8 0 1 0 0 1
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P 53700 43800 53600 43800 1 0 0
{
T 53700 43850 5 8 0 1 0 0 1
pinnumber=2
T 53700 43850 5 8 0 0 0 0 1
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}
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{
T 53600 44050 5 10 0 0 0 0 1
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T 53250 43850 5 8 1 1 0 6 1
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T 53650 43850 5 8 1 1 0 0 1
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T 53200 43700 5 10 0 0 0 0 1
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N 53700 43800 54200 43800 4
C 52600 47700 1 0 0 EMBEDDEDresistor-small.sym
[
T 52850 47900 8 8 0 1 0 3 1
refdes=R?
T 53000 48050 5 10 0 0 0 0 1
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B 52700 47750 300 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 52600 47800 52700 47800 1 0 0
{
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T 52700 47850 5 8 0 0 0 0 1
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P 53100 47800 53000 47800 1 0 0
{
T 53100 47850 5 8 0 1 0 0 1
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T 53100 47850 5 8 0 0 0 0 1
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T 53100 47850 5 8 0 1 0 0 1
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T 53100 47850 5 8 0 1 0 0 1
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{
T 53000 48050 5 10 0 0 0 0 1
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T 52850 47900 5 8 1 1 0 3 1
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T 52850 47700 5 8 1 1 0 5 1
value=100E
T 52600 47700 5 10 0 0 0 0 1
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C 53600 47500 1 0 0 EMBEDDEDbjt-npn-small.sym
[
T 54000 47800 8 8 0 1 0 4 1
refdes=Q?
L 53900 47600 53831 47673 3 0 0 0 -1 -1
L 53901 47600 53803 47609 3 0 0 0 -1 -1
L 53700 47700 53900 47600 3 0 0 0 -1 -1
L 53700 47900 53900 48000 3 0 0 0 -1 -1
P 53900 47600 53900 47500 1 0 1
{
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T 53800 47550 5 6 0 0 0 0 1
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T 53800 47550 5 6 0 1 0 0 1
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}
P 53900 48100 53900 48000 1 0 0
{
T 53800 47950 5 6 0 1 0 0 1
pinnumber=3
T 53800 47950 5 6 0 0 0 0 1
pinseq=3
T 53800 47950 5 6 0 1 0 0 1
pinlabel=3
T 53800 47950 5 6 0 1 0 0 1
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}
P 53600 47800 53700 47800 1 0 0
{
T 53700 47850 5 6 0 1 0 0 1
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T 53700 47850 5 6 0 0 0 0 1
pinseq=1
T 53700 47850 5 6 0 1 0 0 1
pinlabel=1
T 53700 47850 5 6 0 1 0 0 1
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}
T 54200 48000 5 10 0 0 0 0 1
device=NPN_TRANSISTOR
L 53700 48000 53700 47600 3 0 0 0 -1 -1
]
{
T 54200 48000 5 10 0 0 0 0 1
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T 54000 47800 5 8 1 1 0 4 1
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T 53850 48050 5 8 1 1 0 6 1
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T 53600 47500 5 10 0 1 0 0 1
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C 54600 47500 1 90 0 EMBEDDEDresistor-small.sym
[
T 54400 47750 8 8 0 1 90 3 1
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T 54250 47900 5 10 0 0 90 0 1
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B 54450 47600 100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 54500 47500 54500 47600 1 0 0
{
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T 54450 47600 5 8 0 0 90 0 1
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T 54450 47600 5 8 0 1 90 0 1
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T 54450 47600 5 8 0 1 90 0 1
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P 54500 48000 54500 47900 1 0 0
{
T 54450 48000 5 8 0 1 90 0 1
pinnumber=2
T 54450 48000 5 8 0 0 90 0 1
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T 54450 48000 5 8 0 1 90 0 1
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C 55300 47500 1 90 0 EMBEDDEDcapacitor-small.sym
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C 45100 50600 1 0 0 EMBEDDED3.3V-plus-1.sym
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T 45350 50650 5 6 0 0 0 0 1
pinseq=1
T 45350 50650 5 6 0 1 0 0 1
pinnumber=1
}
L 45150 50800 45450 50800 3 0 0 0 -1 -1
T 45175 50850 9 8 1 0 0 0 1
+3.3V
T 45400 50600 8 8 0 0 0 0 1
net=+3.3V:1
]
N 45100 50200 45300 50200 4
N 45300 49400 45300 50600 4
N 45100 50400 45300 50400 4
N 45100 50000 45300 50000 4
N 45100 49800 45300 49800 4
N 45100 49600 45300 49600 4
N 45100 49400 45300 49400 4
C 45200 43300 1 0 0 EMBEDDEDgnd-1.sym
[
P 45300 43400 45300 43600 1 0 1
{
T 45358 43461 5 4 0 1 0 0 1
pintype=pwr
T 45358 43461 5 4 0 1 0 0 1
pinlabel=1
T 45358 43461 5 4 0 0 0 0 1
pinseq=1
T 45358 43461 5 4 0 1 0 0 1
pinnumber=1
}
L 45200 43400 45400 43400 3 0 0 0 -1 -1
L 45255 43350 45345 43350 3 0 0 0 -1 -1
L 45280 43310 45320 43310 3 0 0 0 -1 -1
T 45500 43350 8 10 0 0 0 0 1
net=GND:1
]
N 45100 44600 45300 44600 4
N 45300 44600 45300 43600 4
N 45100 44400 45300 44400 4
N 45100 44200 45300 44200 4
N 45100 44000 45300 44000 4
N 45100 43800 45300 43800 4
C 45900 45000 1 0 1 EMBEDDEDresistor-small.sym
[
T 45650 45200 8 8 0 1 0 3 1
refdes=R?
T 45500 45350 5 10 0 0 0 6 1
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B 45500 45050 300 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 45900 45100 45800 45100 1 0 0
{
T 45800 45150 5 8 0 1 0 6 1
pinnumber=1
T 45800 45150 5 8 0 0 0 6 1
pinseq=1
T 45800 45150 5 8 0 1 0 6 1
pinlabel=1
T 45800 45150 5 8 0 1 0 6 1
pintype=pas
}
P 45400 45100 45500 45100 1 0 0
{
T 45400 45150 5 8 0 1 0 6 1
pinnumber=2
T 45400 45150 5 8 0 0 0 6 1
pinseq=2
T 45400 45150 5 8 0 1 0 6 1
pinlabel=2
T 45400 45150 5 8 0 1 0 6 1
pintype=pas
}
]
{
T 45500 45350 5 10 0 0 0 6 1
device=RESISTOR
T 45650 45200 5 8 1 1 0 3 1
refdes=R7
T 45650 45000 5 8 1 1 0 5 1
value=330E
T 45900 45000 5 10 0 0 0 6 1
footprint=0603
}
C 46200 45000 1 0 0 EMBEDDEDresistor-small.sym
[
T 46450 45200 8 8 0 1 0 3 1
refdes=R?
T 46600 45350 5 10 0 0 0 0 1
device=RESISTOR
B 46300 45050 300 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 46200 45100 46300 45100 1 0 0
{
T 46300 45150 5 8 0 1 0 0 1
pinnumber=1
T 46300 45150 5 8 0 0 0 0 1
pinseq=1
T 46300 45150 5 8 0 1 0 0 1
pinlabel=1
T 46300 45150 5 8 0 1 0 0 1
pintype=pas
}
P 46700 45100 46600 45100 1 0 0
{
T 46700 45150 5 8 0 1 0 0 1
pinnumber=2
T 46700 45150 5 8 0 0 0 0 1
pinseq=2
T 46700 45150 5 8 0 1 0 0 1
pinlabel=2
T 46700 45150 5 8 0 1 0 0 1
pintype=pas
}
]
{
T 46600 45350 5 10 0 0 0 0 1
device=RESISTOR
T 46450 45200 5 8 1 1 0 3 1
refdes=R6
T 46450 45000 5 8 1 1 0 5 1
value=10M
T 46200 45000 5 10 0 0 0 0 1
footprint=0603
}
C 46200 44300 1 0 0 EMBEDDEDxtal-small.sym
[
B 46425 44425 50 150 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 46400 45200 5 10 0 0 0 0 1
numslots=0
T 46400 45400 5 10 0 0 0 0 1
description=crystal
T 46450 44700 8 8 0 1 0 4 1
refdes=X?
T 46400 45000 5 10 0 0 0 0 1
device=CRYSTAL
L 46400 44500 46300 44500 3 0 0 0 -1 -1
L 46600 44500 46500 44500 3 0 0 0 -1 -1
L 46500 44600 46500 44400 3 0 0 0 -1 -1
L 46400 44600 46400 44400 3 0 0 0 -1 -1
P 46700 44500 46600 44500 1 0 0
{
T 46650 44550 5 8 0 1 0 0 1
pinnumber=2
T 46650 44450 5 8 0 1 0 2 1
pinseq=2
T 46600 44500 9 8 0 1 0 6 1
pinlabel=2
T 46600 44500 5 8 0 1 0 8 1
pintype=pas
}
P 46200 44500 46300 44500 1 0 0
{
T 46350 44550 5 8 0 1 0 6 1
pinnumber=1
T 46350 44450 5 8 0 1 0 8 1
pinseq=1
T 46400 44500 9 8 0 1 0 0 1
pinlabel=1
T 46400 44500 5 8 0 1 0 2 1
pintype=pas
}
]
{
T 46400 45000 5 10 0 0 0 0 1
device=CRYSTAL
T 46450 44700 5 8 1 1 0 4 1
refdes=X1
T 46450 44350 5 8 1 1 0 5 1
value=8 MHz
}
N 45100 45100 45400 45100 4
C 46300 43700 1 90 0 EMBEDDEDcapacitor-np-small.sym
[
T 45400 43900 5 10 0 0 90 0 1
symversion=0.1
T 45200 43900 5 10 0 0 90 0 1
numslots=0
T 45000 43900 5 10 0 0 90 0 1
description=capacitor
T 45900 43950 8 8 0 1 90 4 1
refdes=C?
T 45600 43900 5 10 0 0 90 0 1
device=CAPACITOR
L 46100 43925 46100 43800 3 0 0 0 -1 -1
L 46100 44100 46100 43975 3 0 0 0 -1 -1
L 46000 43975 46200 43975 3 0 0 0 -1 -1
L 46000 43925 46200 43925 3 0 0 0 -1 -1
P 46100 44200 46100 44100 1 0 0
{
T 46050 44150 5 8 0 1 90 0 1
pinnumber=2
T 46150 44150 5 8 0 1 90 2 1
pinseq=2
T 46100 44100 9 8 0 1 90 6 1
pinlabel=2
T 46100 44100 5 8 0 1 90 8 1
pintype=pas
}
P 46100 43700 46100 43800 1 0 0
{
T 46050 43850 5 8 0 1 90 6 1
pinnumber=1
T 46150 43850 5 8 0 1 90 8 1
pinseq=1
T 46100 43900 9 8 0 1 90 0 1
pinlabel=1
T 46100 43900 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 45600 43900 5 10 0 0 90 0 1
device=CAPACITOR
T 45900 43950 5 8 1 1 90 4 1
refdes=C3
T 45400 43900 5 10 0 0 90 0 1
symversion=0.1
T 46250 43950 5 8 1 1 90 5 1
value=18p
T 46300 43700 5 10 0 1 0 0 1
footprint=0603
}
C 47000 43700 1 90 0 EMBEDDEDcapacitor-np-small.sym
[
T 46100 43900 5 10 0 0 90 0 1
symversion=0.1
T 45900 43900 5 10 0 0 90 0 1
numslots=0
T 45700 43900 5 10 0 0 90 0 1
description=capacitor
T 46600 43950 8 8 0 1 90 4 1
refdes=C?
T 46300 43900 5 10 0 0 90 0 1
device=CAPACITOR
L 46800 43925 46800 43800 3 0 0 0 -1 -1
L 46800 44100 46800 43975 3 0 0 0 -1 -1
L 46700 43975 46900 43975 3 0 0 0 -1 -1
L 46700 43925 46900 43925 3 0 0 0 -1 -1
P 46800 44200 46800 44100 1 0 0
{
T 46750 44150 5 8 0 1 90 0 1
pinnumber=2
T 46850 44150 5 8 0 1 90 2 1
pinseq=2
T 46800 44100 9 8 0 1 90 6 1
pinlabel=2
T 46800 44100 5 8 0 1 90 8 1
pintype=pas
}
P 46800 43700 46800 43800 1 0 0
{
T 46750 43850 5 8 0 1 90 6 1
pinnumber=1
T 46850 43850 5 8 0 1 90 8 1
pinseq=1
T 46800 43900 9 8 0 1 90 0 1
pinlabel=1
T 46800 43900 5 8 0 1 90 2 1
pintype=pas
}
]
{
T 46300 43900 5 10 0 0 90 0 1
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T 46600 43950 5 8 1 1 90 4 1
refdes=C4
T 46100 43900 5 10 0 0 90 0 1
symversion=0.1
T 46950 43950 5 8 1 1 90 5 1
value=18p
T 47000 43700 5 10 0 1 0 0 1
footprint=0603
}
N 46100 44200 46100 45100 4
N 46700 45100 46800 45100 4
N 46800 44200 46800 45400 4
C 46000 43400 1 0 0 EMBEDDEDgnd-1.sym
[
P 46100 43500 46100 43700 1 0 1
{
T 46158 43561 5 4 0 1 0 0 1
pintype=pwr
T 46158 43561 5 4 0 1 0 0 1
pinlabel=1
T 46158 43561 5 4 0 0 0 0 1
pinseq=1
T 46158 43561 5 4 0 1 0 0 1
pinnumber=1
}
L 46000 43500 46200 43500 3 0 0 0 -1 -1
L 46055 43450 46145 43450 3 0 0 0 -1 -1
L 46080 43410 46120 43410 3 0 0 0 -1 -1
T 46300 43450 8 10 0 0 0 0 1
net=GND:1
]
C 46700 43400 1 0 0 EMBEDDEDgnd-1.sym
[
P 46800 43500 46800 43700 1 0 1
{
T 46858 43561 5 4 0 1 0 0 1
pintype=pwr
T 46858 43561 5 4 0 1 0 0 1
pinlabel=1
T 46858 43561 5 4 0 0 0 0 1
pinseq=1
T 46858 43561 5 4 0 1 0 0 1
pinnumber=1
}
L 46700 43500 46900 43500 3 0 0 0 -1 -1
L 46755 43450 46845 43450 3 0 0 0 -1 -1
L 46780 43410 46820 43410 3 0 0 0 -1 -1
T 47000 43450 8 10 0 0 0 0 1
net=GND:1
]
N 45300 45400 46800 45400 4
N 45100 45300 45300 45300 4
N 45300 45300 45300 45400 4
N 41900 47800 42300 47800 4
N 41900 47600 42300 47600 4
C 41900 47700 1 90 0 EMBEDDEDtestpt.sym
[
P 41900 47800 41750 47800 1 0 0
{
T 41900 47800 5 10 0 1 90 0 1
pinlabel=1
T 41900 47800 5 10 0 1 90 0 1
pintype=io
T 41700 48000 5 10 0 0 90 0 1
pinnumber=1
T 41900 48000 5 10 0 0 90 0 1
pinseq=1
}
L 41700 47750 41750 47800 3 0 0 0 -1 -1
L 41750 47800 41700 47850 3 0 0 0 -1 -1
L 41700 47750 41650 47800 3 0 0 0 -1 -1
L 41650 47800 41700 47850 3 0 0 0 -1 -1
T 41600 47800 8 10 0 1 90 0 1
refdes=TP?
T 41000 48100 8 10 0 0 90 0 1
device=TESTPOINT
T 41200 48100 8 10 0 0 90 0 1
footprint=none
T 40800 48100 8 10 0 0 90 0 1
numslots=0
]
{
T 41600 47800 5 10 1 1 0 7 1
refdes=TP1
T 41000 48100 5 10 0 0 90 0 1
device=TESTPOINT
T 41200 48100 5 10 0 0 90 0 1
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}
N 41900 47400 42300 47400 4
C 41900 47300 1 90 0 EMBEDDEDtestpt.sym
[
P 41900 47400 41750 47400 1 0 0
{
T 41900 47400 5 10 0 1 90 0 1
pinlabel=1
T 41900 47400 5 10 0 1 90 0 1
pintype=io
T 41700 47600 5 10 0 0 90 0 1
pinnumber=1
T 41900 47600 5 10 0 0 90 0 1
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L 41700 47350 41750 47400 3 0 0 0 -1 -1
L 41750 47400 41700 47450 3 0 0 0 -1 -1
L 41700 47350 41650 47400 3 0 0 0 -1 -1
L 41650 47400 41700 47450 3 0 0 0 -1 -1
T 41600 47400 8 10 0 1 90 0 1
refdes=TP?
T 41000 47700 8 10 0 0 90 0 1
device=TESTPOINT
T 41200 47700 8 10 0 0 90 0 1
footprint=none
T 40800 47700 8 10 0 0 90 0 1
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]
{
T 41000 47700 5 10 0 0 90 0 1
device=TESTPOINT
T 41200 47700 5 10 0 0 90 0 1
footprint=none
T 41600 47400 5 10 1 1 0 7 1
refdes=TP3
}
C 41900 47500 1 90 0 EMBEDDEDtestpt.sym
[
P 41900 47600 41750 47600 1 0 0
{
T 41900 47600 5 10 0 1 90 0 1
pinlabel=1
T 41900 47600 5 10 0 1 90 0 1
pintype=io
T 41700 47800 5 10 0 0 90 0 1
pinnumber=1
T 41900 47800 5 10 0 0 90 0 1
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}
L 41700 47550 41750 47600 3 0 0 0 -1 -1
L 41750 47600 41700 47650 3 0 0 0 -1 -1
L 41700 47550 41650 47600 3 0 0 0 -1 -1
L 41650 47600 41700 47650 3 0 0 0 -1 -1
T 41600 47600 8 10 0 1 90 0 1
refdes=TP?
T 41000 47900 8 10 0 0 90 0 1
device=TESTPOINT
T 41200 47900 8 10 0 0 90 0 1
footprint=none
T 40800 47900 8 10 0 0 90 0 1
numslots=0
]
{
T 41600 47600 5 10 1 1 0 7 1
refdes=TP2
T 41000 47900 5 10 0 0 90 0 1
device=TESTPOINT
T 41200 47900 5 10 0 0 90 0 1
footprint=none
}
N 45500 48000 45100 48000 4
C 45500 47900 1 270 1 EMBEDDEDtestpt.sym
[
P 45500 48000 45650 48000 1 0 0
{
T 45500 48000 5 10 0 1 90 2 1
pinlabel=1
T 45500 48000 5 10 0 1 90 2 1
pintype=io
T 45700 48200 5 10 0 0 90 2 1
pinnumber=1
T 45500 48200 5 10 0 0 90 2 1
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L 45700 47950 45650 48000 3 0 0 0 -1 -1
L 45650 48000 45700 48050 3 0 0 0 -1 -1
L 45700 47950 45750 48000 3 0 0 0 -1 -1
L 45750 48000 45700 48050 3 0 0 0 -1 -1
T 45800 48000 8 10 0 1 90 2 1
refdes=TP?
T 46400 48300 8 10 0 0 90 2 1
device=TESTPOINT
T 46200 48300 8 10 0 0 90 2 1
footprint=none
T 46600 48300 8 10 0 0 90 2 1
numslots=0
]
{
T 45800 48000 5 10 1 1 0 1 1
refdes=TP4
T 46400 48300 5 10 0 0 90 2 1
device=TESTPOINT
T 46200 48300 5 10 0 0 90 2 1
footprint=none
}
N 42300 48200 41900 48200 4
{
T 41800 48200 5 10 1 1 0 7 1
netname=USB_DM
}
N 42300 48000 41900 48000 4
{
T 41800 48000 5 10 1 1 0 7 1
netname=USB_DP
}
N 42300 48800 41900 48800 4
{
T 41800 48800 5 10 1 1 0 7 1
netname=USB_PU
}
N 45100 48600 45500 48600 4
{
T 45600 48600 5 10 1 1 0 1 1
netname=xTPWR
}
N 45100 48400 45500 48400 4
{
T 45600 48400 5 10 1 1 0 1 1
netname=xnTRST
}
N 42300 50000 41900 50000 4
{
T 41800 50000 5 10 1 1 0 7 1
netname=xnSRST_OUT
}
N 42300 49800 41900 49800 4
{
T 41800 49800 5 10 1 1 0 7 1
netname=xTDI
}
N 42300 49600 41900 49600 4
{
T 41800 49600 5 10 1 1 0 7 1
netname=xTMS
}
N 42300 49400 41900 49400 4
{
T 41800 49400 5 10 1 1 0 7 1
netname=xTCK
}
N 42300 49200 41900 49200 4
{
T 41800 49200 5 10 1 1 0 7 1
netname=xTDO
}
N 42300 49000 41900 49000 4
{
T 41800 49000 5 10 1 1 0 7 1
netname=xnSRST
}
N 45100 48200 45500 48200 4
{
T 45600 48200 5 10 1 1 0 1 1
netname=LED0
}
N 45100 46600 45500 46600 4
{
T 45600 46600 5 10 1 1 0 1 1
netname=LED1
}
N 45100 46400 45500 46400 4
{
T 45600 46400 5 10 1 1 0 1 1
netname=LED2
}
N 42300 48600 41900 48600 4
{
T 41800 48600 5 10 1 1 0 7 1
netname=U1TX
}
N 42300 48400 41900 48400 4
{
T 41800 48400 5 10 1 1 0 7 1
netname=U1RX
}
N 45100 47800 46900 47800 4
C 46700 47800 1 0 0 EMBEDDED3.3V-plus-1.sym
[
P 46900 47800 46900 48000 1 0 0
{
T 46950 47850 5 6 0 1 0 0 1
pintype=pwr
T 46950 47850 5 6 0 1 0 0 1
pinlabel=1
T 46950 47850 5 6 0 0 0 0 1
pinseq=1
T 46950 47850 5 6 0 1 0 0 1
pinnumber=1
}
L 46750 48000 47050 48000 3 0 0 0 -1 -1
T 46775 48050 9 8 1 0 0 0 1
+3.3V
T 47000 47800 8 8 0 0 0 0 1
net=+3.3V:1
]
N 45100 46200 46700 46200 4
C 46600 46400 1 90 0 EMBEDDEDresistor-small.sym
[
T 46400 46650 8 8 0 1 90 3 1
refdes=R?
T 46250 46800 5 10 0 0 90 0 1
device=RESISTOR
B 46450 46500 100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 46500 46400 46500 46500 1 0 0
{
T 46450 46500 5 8 0 1 90 0 1
pinnumber=1
T 46450 46500 5 8 0 0 90 0 1
pinseq=1
T 46450 46500 5 8 0 1 90 0 1
pinlabel=1
T 46450 46500 5 8 0 1 90 0 1
pintype=pas
}
P 46500 46900 46500 46800 1 0 0
{
T 46450 46900 5 8 0 1 90 0 1
pinnumber=2
T 46450 46900 5 8 0 0 90 0 1
pinseq=2
T 46450 46900 5 8 0 1 90 0 1
pinlabel=2
T 46450 46900 5 8 0 1 90 0 1
pintype=pas
}
]
{
T 46250 46800 5 10 0 0 90 0 1
device=RESISTOR
T 46400 46650 5 8 1 1 90 3 1
refdes=R14
T 46600 46650 5 8 1 1 90 5 1
value=1K
T 46600 46400 5 10 0 0 90 0 1
footprint=0603
}
C 46300 46900 1 0 0 EMBEDDED3.3V-plus-1.sym
[
P 46500 46900 46500 47100 1 0 0
{
T 46550 46950 5 6 0 1 0 0 1
pintype=pwr
T 46550 46950 5 6 0 1 0 0 1
pinlabel=1
T 46550 46950 5 6 0 0 0 0 1
pinseq=1
T 46550 46950 5 6 0 1 0 0 1
pinnumber=1
}
L 46350 47100 46650 47100 3 0 0 0 -1 -1
T 46375 47150 9 8 1 0 0 0 1
+3.3V
T 46600 46900 8 8 0 0 0 0 1
net=+3.3V:1
]
C 45900 49300 1 90 0 EMBEDDEDresistor-small.sym
[
T 45700 49550 8 8 0 1 90 3 1
refdes=R?
T 45550 49700 5 10 0 0 90 0 1
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B 45750 49400 100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 45800 49300 45800 49400 1 0 0
{
T 45750 49400 5 8 0 1 90 0 1
pinnumber=1
T 45750 49400 5 8 0 0 90 0 1
pinseq=1
T 45750 49400 5 8 0 1 90 0 1
pinlabel=1
T 45750 49400 5 8 0 1 90 0 1
pintype=pas
}
P 45800 49800 45800 49700 1 0 0
{
T 45750 49800 5 8 0 1 90 0 1
pinnumber=2
T 45750 49800 5 8 0 0 90 0 1
pinseq=2
T 45750 49800 5 8 0 1 90 0 1
pinlabel=2
T 45750 49800 5 8 0 1 90 0 1
pintype=pas
}
]
{
T 45550 49700 5 10 0 0 90 0 1
device=RESISTOR
T 45700 49550 5 8 1 1 90 3 1
refdes=R5
T 45900 49550 5 8 1 1 90 5 1
value=1K
T 45900 49300 5 10 0 0 90 0 1
footprint=0603
}
N 45100 49100 45800 49100 4
N 45800 49100 45800 49300 4
C 45600 49800 1 0 0 EMBEDDED3.3V-plus-1.sym
[
P 45800 49800 45800 50000 1 0 0
{
T 45850 49850 5 6 0 1 0 0 1
pintype=pwr
T 45850 49850 5 6 0 1 0 0 1
pinlabel=1
T 45850 49850 5 6 0 0 0 0 1
pinseq=1
T 45850 49850 5 6 0 1 0 0 1
pinnumber=1
}
L 45650 50000 45950 50000 3 0 0 0 -1 -1
T 45675 50050 9 8 1 0 0 0 1
+3.3V
T 45900 49800 8 8 0 0 0 0 1
net=+3.3V:1
]
C 47100 48800 1 0 1 EMBEDDEDresistor-small.sym
[
T 46850 49000 8 8 0 1 0 3 1
refdes=R?
T 46700 49150 5 10 0 0 0 6 1
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B 46700 48850 300 100 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 47100 48900 47000 48900 1 0 0
{
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pinnumber=1
T 47000 48950 5 8 0 0 0 6 1
pinseq=1
T 47000 48950 5 8 0 1 0 6 1
pinlabel=1
T 47000 48950 5 8 0 1 0 6 1
pintype=pas
}
P 46600 48900 46700 48900 1 0 0
{
T 46600 48950 5 8 0 1 0 6 1
pinnumber=2
T 46600 48950 5 8 0 0 0 6 1
pinseq=2
T 46600 48950 5 8 0 1 0 6 1
pinlabel=2
T 46600 48950 5 8 0 1 0 6 1
pintype=pas
}
]
{
T 46700 49150 5 10 0 0 0 6 1
device=RESISTOR
T 46850 49000 5 8 1 1 0 3 1
refdes=R13
T 46850 48800 5 8 1 1 0 5 1
value=10K
T 47100 48800 5 10 0 0 0 6 1
footprint=0603
}
N 45100 48900 46600 48900 4
C 47200 48600 1 0 0 EMBEDDEDgnd-1.sym
[
P 47300 48700 47300 48900 1 0 1
{
T 47358 48761 5 4 0 1 0 0 1
pintype=pwr
T 47358 48761 5 4 0 1 0 0 1
pinlabel=1
T 47358 48761 5 4 0 0 0 0 1
pinseq=1
T 47358 48761 5 4 0 1 0 0 1
pinnumber=1
}
L 47200 48700 47400 48700 3 0 0 0 -1 -1
L 47255 48650 47345 48650 3 0 0 0 -1 -1
L 47280 48610 47320 48610 3 0 0 0 -1 -1
T 47500 48650 8 10 0 0 0 0 1
net=GND:1
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N 47100 48900 47300 48900 4
C 46500 49300 1 90 0 EMBEDDEDresistor-small.sym
[
T 46300 49550 8 8 0 1 90 3 1
refdes=R?
T 46150 49700 5 10 0 0 90 0 1
device=RESISTOR
B 46350 49400 100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 46400 49300 46400 49400 1 0 0
{
T 46350 49400 5 8 0 1 90 0 1
pinnumber=1
T 46350 49400 5 8 0 0 90 0 1
pinseq=1
T 46350 49400 5 8 0 1 90 0 1
pinlabel=1
T 46350 49400 5 8 0 1 90 0 1
pintype=pas
}
P 46400 49800 46400 49700 1 0 0
{
T 46350 49800 5 8 0 1 90 0 1
pinnumber=2
T 46350 49800 5 8 0 0 90 0 1
pinseq=2
T 46350 49800 5 8 0 1 90 0 1
pinlabel=2
T 46350 49800 5 8 0 1 90 0 1
pintype=pas
}
]
{
T 46150 49700 5 10 0 0 90 0 1
device=RESISTOR
T 46300 49550 5 8 1 1 90 3 1
refdes=R12
T 46500 49550 5 8 1 1 90 5 1
value=1K
T 46500 49300 5 10 0 0 90 0 1
footprint=0603
}
N 46400 49300 46400 48900 4
N 46400 49800 46400 50000 4
N 46400 50000 46600 50000 4
{
T 46700 50000 5 10 1 1 0 1 1
netname=BOOT0
}
C 47300 46200 1 0 1 EMBEDDEDswitch-pushbutton-no.sym
[
T 46900 46800 8 10 0 0 0 6 1
device=SWITCH_PUSHBUTTON_NO
L 47000 46350 47000 46300 3 0 0 0 -1 -1
L 47000 46400 47000 46450 3 0 0 0 -1 -1
L 46975 46400 47000 46350 3 0 0 0 -1 -1
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L 47025 46400 46975 46400 3 0 0 0 -1 -1
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V 46913 46200 14 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 47086 46200 14 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 47100 46300 46900 46300 3 0 0 0 -1 -1
L 46800 46200 46900 46200 3 0 0 0 -1 -1
L 47200 46200 47100 46200 3 0 0 0 -1 -1
P 46800 46200 46700 46200 1 0 1
{
T 46800 46250 5 8 0 1 0 6 1
pinnumber=2
T 46800 46250 5 8 0 0 0 6 1
pinseq=2
T 46800 46250 5 8 0 1 0 6 1
pinlabel=2
T 46800 46250 5 8 0 1 0 6 1
pintype=pas
}
P 47300 46200 47200 46200 1 0 0
{
T 47250 46250 5 8 0 1 0 6 1
pinnumber=1
T 47250 46250 5 8 0 0 0 6 1
pinseq=1
T 47250 46250 5 8 0 1 0 6 1
pinlabel=1
T 47250 46250 5 8 0 1 0 6 1
pintype=pas
}
T 47000 46500 8 8 0 1 0 3 1
refdes=S?
]
{
T 47000 46150 5 8 1 1 0 5 1
refdes=S1
T 46900 46800 5 10 0 0 0 6 1
device=SWITCH_PUSHBUTTON_NO
}
C 47400 45900 1 0 0 EMBEDDEDgnd-1.sym
[
P 47500 46000 47500 46200 1 0 1
{
T 47558 46061 5 4 0 1 0 0 1
pintype=pwr
T 47558 46061 5 4 0 1 0 0 1
pinlabel=1
T 47558 46061 5 4 0 0 0 0 1
pinseq=1
T 47558 46061 5 4 0 1 0 0 1
pinnumber=1
}
L 47400 46000 47600 46000 3 0 0 0 -1 -1
L 47455 45950 47545 45950 3 0 0 0 -1 -1
L 47480 45910 47520 45910 3 0 0 0 -1 -1
T 47700 45950 8 10 0 0 0 0 1
net=GND:1
]
N 47300 46200 47500 46200 4
N 46500 46400 46500 46200 4
C 57300 48100 1 90 0 EMBEDDEDjumper.sym
[
T 56900 48350 8 10 0 1 90 1 1
refdes=J?
T 56800 48400 5 8 0 0 90 0 1
device=JUMPER
B 56700 48100 400 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 57000 48200 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 56800 48200 50 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 57200 48200 57100 48200 1 0 0
{
T 57250 48250 5 8 0 1 90 0 1
pinnumber=1
T 57250 48250 5 8 0 0 90 0 1
pinseq=1
T 57250 48250 5 8 0 1 90 0 1
pinlabel=1
T 57250 48250 5 8 0 1 90 0 1
pintype=pas
}
P 56600 48200 56700 48200 1 0 0
{
T 56650 48250 5 8 0 1 90 0 1
pinnumber=2
T 56650 48250 5 8 0 0 90 0 1
pinseq=2
T 56650 48250 5 8 0 1 90 0 1
pinlabel=2
T 56650 48250 5 8 0 1 90 0 1
pintype=pas
}
]
{
T 56800 48400 5 8 0 0 90 0 1
device=JUMPER
T 56900 48350 5 10 1 1 0 3 1
refdes=J3
}
N 46200 44500 46100 44500 4
N 57600 48200 57200 48200 4
N 46700 44500 46800 44500 4
N 45900 45100 46200 45100 4
N 52400 53300 52400 53200 4
N 55900 53800 55900 53900 4
N 55200 53800 55200 53900 4
N 53800 53300 53800 53200 4