diff --git a/src/target/lmi.c b/src/target/lmi.c
index e331b39..7f3aa0f 100644
--- a/src/target/lmi.c
+++ b/src/target/lmi.c
@@ -84,6 +84,10 @@ bool lmi_probe(target *t)
 		t->driver = lmi_driver_str;
 		target_add_ram(t, 0x20000000, 0x10000);
 		lmi_add_flash(t, 0x80000);
+		/* On Tiva targets, asserting SRST results in the debug
+		 * logic also being reset.  We can't assert SRST and must
+		 * only use the AIRCR SYSRESETREQ. */
+		t->target_options |= CORTEXM_TOPT_INHIBIT_SRST;
 		return true;
 	}
 	return false;
@@ -92,6 +96,9 @@ bool lmi_probe(target *t)
 int lmi_flash_erase(struct target_flash *f, target_addr addr, size_t len)
 {
 	target  *t = f->t;
+
+	target_check_error(t);
+
 	while(len) {
 		target_mem_write32(t, LMI_FLASH_FMA, addr);
 		target_mem_write32(t, LMI_FLASH_FMC,
@@ -99,6 +106,9 @@ int lmi_flash_erase(struct target_flash *f, target_addr addr, size_t len)
 		while (target_mem_read32(t, LMI_FLASH_FMC) &
 		       LMI_FLASH_FMC_ERASE);
 
+		if (target_check_error(t))
+			return -1;
+
 		len -= BLOCK_SIZE;
 		addr += BLOCK_SIZE;
 	}
@@ -110,9 +120,14 @@ int lmi_flash_write(struct target_flash *f,
 {
 	target  *t = f->t;
 
+	target_check_error(t);
+
 	target_mem_write(t, SRAM_BASE, lmi_flash_write_stub,
 	                 sizeof(lmi_flash_write_stub));
 	target_mem_write(t, STUB_BUFFER_BASE, src, len);
+
+	if (target_check_error(t))
+		return -1;
+
 	return cortexm_run_stub(t, SRAM_BASE, dest, STUB_BUFFER_BASE, len, 0);
 }
-