diff --git a/src/adiv5.c b/src/adiv5.c
index 5227cc8..2142527 100644
--- a/src/adiv5.c
+++ b/src/adiv5.c
@@ -134,6 +134,8 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
 
 		ap->cfg = adiv5_ap_read(ap, ADIV5_AP_CFG);
 		ap->base = adiv5_ap_read(ap, ADIV5_AP_BASE);
+		ap->csw = adiv5_ap_read(ap, ADIV5_AP_CSW) &
+			~(ADIV5_AP_CSW_SIZE_MASK | ADIV5_AP_CSW_ADDRINC_MASK);
 
 		/* Should probe further here to make sure it's a valid target.
 		 * AP should be unref'd if not valid.
@@ -191,7 +193,8 @@ ap_mem_read_words(struct target_s *target, uint32_t *dest, uint32_t src, int len
 
 	len >>= 2;
 
-	adiv5_ap_write(ap, ADIV5_AP_CSW, 0xA2000052);
+	adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw |
+		ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE);
 	adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE,
 					ADIV5_AP_TAR, src);
 	adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_READ,
@@ -223,7 +226,8 @@ ap_mem_read_bytes(struct target_s *target, uint8_t *dest, uint32_t src, int len)
 	uint32_t tmp;
 	uint32_t osrc = src;
 
-	adiv5_ap_write(ap, ADIV5_AP_CSW, 0xA2000050);
+	adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw |
+		ADIV5_AP_CSW_SIZE_BYTE | ADIV5_AP_CSW_ADDRINC_SINGLE);
 	adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE,
 					ADIV5_AP_TAR, src);
 	adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_READ,
@@ -257,7 +261,8 @@ ap_mem_write_words(struct target_s *target, uint32_t dest, const uint32_t *src,
 
 	len >>= 2;
 
-	adiv5_ap_write(ap, ADIV5_AP_CSW, 0xA2000052);
+	adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw |
+		ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE);
 	adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE,
 					ADIV5_AP_TAR, dest);
 	while(len--) {
@@ -281,7 +286,8 @@ ap_mem_write_bytes(struct target_s *target, uint32_t dest, const uint8_t *src, i
 	ADIv5_AP_t *ap = adiv5_target_ap(target);
 	uint32_t odest = dest;
 
-	adiv5_ap_write(ap, ADIV5_AP_CSW, 0xA2000050);
+	adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw |
+		ADIV5_AP_CSW_SIZE_BYTE | ADIV5_AP_CSW_ADDRINC_SINGLE);
 	adiv5_dp_low_access(ap->dp, ADIV5_LOW_AP, ADIV5_LOW_WRITE,
 					ADIV5_AP_TAR, dest);
 	while(len--) {
@@ -304,21 +310,24 @@ ap_mem_write_bytes(struct target_s *target, uint32_t dest, const uint8_t *src, i
 
 uint32_t adiv5_ap_mem_read(ADIv5_AP_t *ap, uint32_t addr)
 {
-	adiv5_ap_write(ap, ADIV5_AP_CSW, 0xA2000052);
+	adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw |
+		ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE);
 	adiv5_ap_write(ap, ADIV5_AP_TAR, addr);
 	return adiv5_ap_read(ap, ADIV5_AP_DRW);
 }
 
 void adiv5_ap_mem_write(ADIv5_AP_t *ap, uint32_t addr, uint32_t value)
 {
-	adiv5_ap_write(ap, ADIV5_AP_CSW, 0xA2000052);
+	adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw |
+		ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE);
 	adiv5_ap_write(ap, ADIV5_AP_TAR, addr);
 	adiv5_ap_write(ap, ADIV5_AP_DRW, value);
 }
 
 uint16_t adiv5_ap_mem_read_halfword(ADIv5_AP_t *ap, uint32_t addr)
 {
-	adiv5_ap_write(ap, ADIV5_AP_CSW, 0xA2000051);
+	adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw |
+		ADIV5_AP_CSW_SIZE_HALFWORD | ADIV5_AP_CSW_ADDRINC_SINGLE);
 	adiv5_ap_write(ap, ADIV5_AP_TAR, addr);
 	uint32_t v = adiv5_ap_read(ap, ADIV5_AP_DRW);
 	if (addr & 2)
@@ -333,7 +342,8 @@ void adiv5_ap_mem_write_halfword(ADIv5_AP_t *ap, uint32_t addr, uint16_t value)
 	if (addr & 2)
 		v <<= 16;
 
-	adiv5_ap_write(ap, ADIV5_AP_CSW, 0xA2000051);
+	adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw |
+		ADIV5_AP_CSW_SIZE_HALFWORD | ADIV5_AP_CSW_ADDRINC_SINGLE);
 	adiv5_ap_write(ap, ADIV5_AP_TAR, addr);
 	adiv5_ap_write(ap, ADIV5_AP_DRW, v);
 }
diff --git a/src/cortexm.c b/src/cortexm.c
index 4430e6e..9ec96d6 100644
--- a/src/cortexm.c
+++ b/src/cortexm.c
@@ -459,7 +459,8 @@ cortexm_regs_read(struct target_s *target, void *data)
 	unsigned i;
 
 	/* FIXME: Describe what's really going on here */
-	adiv5_ap_write(ap, ADIV5_AP_CSW, 0xA2000052);
+	adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw |
+		ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE);
 
 	/* Map the banked data registers (0x10-0x1c) to the
 	 * debug registers DHCSR, DCRSR, DCRDR and DEMCR respectively */
@@ -490,7 +491,8 @@ cortexm_regs_write(struct target_s *target, const void *data)
 	unsigned i;
 
 	/* FIXME: Describe what's really going on here */
-	adiv5_ap_write(ap, ADIV5_AP_CSW, 0xA2000052);
+	adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw |
+		ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE);
 
 	/* Map the banked data registers (0x10-0x1c) to the
 	 * debug registers DHCSR, DCRSR, DCRDR and DEMCR respectively */
diff --git a/src/include/adiv5.h b/src/include/adiv5.h
index 0f51bb1..d2d4be0 100644
--- a/src/include/adiv5.h
+++ b/src/include/adiv5.h
@@ -150,6 +150,7 @@ typedef struct ADIv5_AP_s {
 	uint32_t idr;
 	uint32_t cfg;
 	uint32_t base;
+	uint32_t csw;
 
 	void *priv;
 	void (*priv_free)(void *);