diff --git a/src/target/stm32l0.c b/src/target/stm32l0.c
index 5714574..bde8795 100644
--- a/src/target/stm32l0.c
+++ b/src/target/stm32l0.c
@@ -79,69 +79,69 @@
 #include "target_internal.h"
 #include "cortexm.h"
 
-#define STM32Lx_NVM_PECR(p)    ((p) + 0x04)
-#define STM32Lx_NVM_PEKEYR(p)  ((p) + 0x0C)
-#define STM32Lx_NVM_PRGKEYR(p) ((p) + 0x10)
-#define STM32Lx_NVM_OPTKEYR(p) ((p) + 0x14)
-#define STM32Lx_NVM_SR(p)      ((p) + 0x18)
-#define STM32Lx_NVM_OPTR(p)    ((p) + 0x1C)
+#define STM32Lx_NVM_PECR(p)    ((p) + 0x04U)
+#define STM32Lx_NVM_PEKEYR(p)  ((p) + 0x0cU)
+#define STM32Lx_NVM_PRGKEYR(p) ((p) + 0x10U)
+#define STM32Lx_NVM_OPTKEYR(p) ((p) + 0x14U)
+#define STM32Lx_NVM_SR(p)      ((p) + 0x18U)
+#define STM32Lx_NVM_OPTR(p)    ((p) + 0x1cU)
 
-#define STM32L0_NVM_PHYS             (0x40022000ul)
-#define STM32L0_NVM_OPT_SIZE         (12)
-#define STM32L0_NVM_EEPROM_CAT1_SIZE (1 * 512)
-#define STM32L0_NVM_EEPROM_CAT2_SIZE (1 * 1024)
-#define STM32L0_NVM_EEPROM_CAT3_SIZE (2 * 1024)
-#define STM32L0_NVM_EEPROM_CAT5_SIZE (6 * 1024)
+#define STM32L0_NVM_PHYS             (0x40022000UL)
+#define STM32L0_NVM_OPT_SIZE         (12U)
+#define STM32L0_NVM_EEPROM_CAT1_SIZE (1U * 512U)
+#define STM32L0_NVM_EEPROM_CAT2_SIZE (1U * 1024U)
+#define STM32L0_NVM_EEPROM_CAT3_SIZE (2U * 1024U)
+#define STM32L0_NVM_EEPROM_CAT5_SIZE (6U * 1024U)
 
-#define STM32L1_NVM_PHYS        (0x40023c00ul)
-#define STM32L1_NVM_OPT_SIZE    (32)
-#define STM32L1_NVM_EEPROM_SIZE (16 * 1024)
+#define STM32L1_NVM_PHYS        (0x40023c00UL)
+#define STM32L1_NVM_OPT_SIZE    (32U)
+#define STM32L1_NVM_EEPROM_SIZE (16U * 1024U)
 
-#define STM32Lx_NVM_OPT_PHYS    0x1ff80000ul
-#define STM32Lx_NVM_EEPROM_PHYS 0x08080000ul
+#define STM32Lx_NVM_OPT_PHYS    0x1ff80000UL
+#define STM32Lx_NVM_EEPROM_PHYS 0x08080000UL
 
-#define STM32Lx_NVM_PEKEY1  (0x89abcdeful)
-#define STM32Lx_NVM_PEKEY2  (0x02030405ul)
-#define STM32Lx_NVM_PRGKEY1 (0x8c9daebful)
-#define STM32Lx_NVM_PRGKEY2 (0x13141516ul)
-#define STM32Lx_NVM_OPTKEY1 (0xfbead9c8ul)
-#define STM32Lx_NVM_OPTKEY2 (0x24252627ul)
+#define STM32Lx_NVM_PEKEY1  (0x89abcdefUL)
+#define STM32Lx_NVM_PEKEY2  (0x02030405UL)
+#define STM32Lx_NVM_PRGKEY1 (0x8c9daebfUL)
+#define STM32Lx_NVM_PRGKEY2 (0x13141516UL)
+#define STM32Lx_NVM_OPTKEY1 (0xfbead9c8UL)
+#define STM32Lx_NVM_OPTKEY2 (0x24252627UL)
 
-#define STM32Lx_NVM_PECR_OBL_LAUNCH (1 << 18)
-#define STM32Lx_NVM_PECR_ERRIE      (1 << 17)
-#define STM32Lx_NVM_PECR_EOPIE      (1 << 16)
-#define STM32Lx_NVM_PECR_FPRG       (1 << 10)
-#define STM32Lx_NVM_PECR_ERASE      (1 << 9)
-#define STM32Lx_NVM_PECR_FIX        (1 << 8) /* FTDW */
-#define STM32Lx_NVM_PECR_DATA       (1 << 4)
-#define STM32Lx_NVM_PECR_PROG       (1 << 3)
-#define STM32Lx_NVM_PECR_OPTLOCK    (1 << 2)
-#define STM32Lx_NVM_PECR_PRGLOCK    (1 << 1)
-#define STM32Lx_NVM_PECR_PELOCK     (1 << 0)
+#define STM32Lx_NVM_PECR_OBL_LAUNCH (1U << 18U)
+#define STM32Lx_NVM_PECR_ERRIE      (1U << 17U)
+#define STM32Lx_NVM_PECR_EOPIE      (1U << 16U)
+#define STM32Lx_NVM_PECR_FPRG       (1U << 10U)
+#define STM32Lx_NVM_PECR_ERASE      (1U << 9U)
+#define STM32Lx_NVM_PECR_FIX        (1U << 8U) /* FTDW */
+#define STM32Lx_NVM_PECR_DATA       (1U << 4U)
+#define STM32Lx_NVM_PECR_PROG       (1U << 3U)
+#define STM32Lx_NVM_PECR_OPTLOCK    (1U << 2U)
+#define STM32Lx_NVM_PECR_PRGLOCK    (1U << 1U)
+#define STM32Lx_NVM_PECR_PELOCK     (1U << 0U)
 
-#define STM32Lx_NVM_SR_NOTZEROERR (1 << 16)
-#define STM32Lx_NVM_SR_SIZERR     (1 << 10)
-#define STM32Lx_NVM_SR_PGAERR     (1 << 9)
-#define STM32Lx_NVM_SR_WRPERR     (1 << 8)
-#define STM32Lx_NVM_SR_EOP        (1 << 1)
-#define STM32Lx_NVM_SR_BSY        (1 << 0)
+#define STM32Lx_NVM_SR_NOTZEROERR (1U << 16U)
+#define STM32Lx_NVM_SR_SIZERR     (1U << 10U)
+#define STM32Lx_NVM_SR_PGAERR     (1U << 9U)
+#define STM32Lx_NVM_SR_WRPERR     (1U << 8U)
+#define STM32Lx_NVM_SR_EOP        (1U << 1U)
+#define STM32Lx_NVM_SR_BSY        (1U << 0U)
 #define STM32Lx_NVM_SR_ERR_M \
 	(STM32Lx_NVM_SR_WRPERR | STM32Lx_NVM_SR_PGAERR | STM32Lx_NVM_SR_SIZERR | STM32Lx_NVM_SR_NOTZEROERR)
 
-#define STM32L0_NVM_OPTR_BOOT1    (1 << 31)
-#define STM32Lx_NVM_OPTR_WDG_SW   (1 << 20)
-#define STM32L0_NVM_OPTR_WPRMOD   (1 << 8)
-#define STM32Lx_NVM_OPTR_RDPROT_S (0)
-#define STM32Lx_NVM_OPTR_RDPROT_M (0xff)
-#define STM32Lx_NVM_OPTR_RDPROT_0 (0xaa)
-#define STM32Lx_NVM_OPTR_RDPROT_2 (0xcc)
+#define STM32L0_NVM_OPTR_BOOT1    (1U << 31U)
+#define STM32Lx_NVM_OPTR_WDG_SW   (1U << 20U)
+#define STM32L0_NVM_OPTR_WPRMOD   (1U << 8U)
+#define STM32Lx_NVM_OPTR_RDPROT_S (0U)
+#define STM32Lx_NVM_OPTR_RDPROT_M (0xffU)
+#define STM32Lx_NVM_OPTR_RDPROT_0 (0xaaU)
+#define STM32Lx_NVM_OPTR_RDPROT_2 (0xccU)
 
-#define STM32L1_NVM_OPTR_nBFB2      (1 << 23)
-#define STM32L1_NVM_OPTR_nRST_STDBY (1 << 22)
-#define STM32L1_NVM_OPTR_nRST_STOP  (1 << 21)
-#define STM32L1_NVM_OPTR_BOR_LEV_S  (16)
-#define STM32L1_NVM_OPTR_BOR_LEV_M  (0xf)
-#define STM32L1_NVM_OPTR_SPRMOD     (1 << 8)
+#define STM32L1_NVM_OPTR_nBFB2      (1U << 23U)
+#define STM32L1_NVM_OPTR_nRST_STDBY (1U << 22U)
+#define STM32L1_NVM_OPTR_nRST_STOP  (1U << 21U)
+#define STM32L1_NVM_OPTR_BOR_LEV_S  (16U)
+#define STM32L1_NVM_OPTR_BOR_LEV_M  (0xfU)
+#define STM32L1_NVM_OPTR_SPRMOD     (1U << 8U)
 
 static bool stm32lx_nvm_prog_erase(target_flash_s *f, target_addr_t addr, size_t len);
 static bool stm32lx_nvm_prog_write(target_flash_s *f, target_addr_t destination, const void *src, size_t size);