From 634c07c43234985a00f7b2980a9ccefacd4d8a39 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Mon, 3 Jun 2019 19:37:53 +0200 Subject: [PATCH] adiv5: Add TSGEN. --- src/target/adiv5.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/target/adiv5.c b/src/target/adiv5.c index a4af107..5e1384a 100644 --- a/src/target/adiv5.c +++ b/src/target/adiv5.c @@ -174,6 +174,7 @@ static const struct { {0x00c, aa_cortexm, cidc_gipc, PIDR_PN_BIT_STRINGS("Cortex-M4 SCS", "(System Control Space)")}, {0x00d, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETM11", "(Embedded Trace)")}, {0x00e, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 FBP", "(Flash Patch and Breakpoint)")}, + {0x101, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("System TSGEN", "(Time Stamp Generator)")}, {0x490, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 GIC", "(Generic Interrupt Controller)")}, {0x4c7, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 PPB", "(Private Peripheral Bus ROM Table)")}, {0x906, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight CTI", "(Cross Trigger)")},