diff --git a/src/target/cortexm.c b/src/target/cortexm.c
index 36ebf5b..452fe2d 100644
--- a/src/target/cortexm.c
+++ b/src/target/cortexm.c
@@ -297,41 +297,37 @@ bool cortexm_probe(ADIv5_AP_t *ap)
 	 * that is, the actual values are found in the Technical Reference Manual
 	 * for each Cortex-M core.
 	 */
-	uint32_t cpuid = target_mem_read32(t, CORTEXM_CPUID);
-	uint16_t partno = (cpuid >> 4) & 0xfff;
-
-	switch (partno) {
-	case 0xd21:
+	t->cpuid = target_mem_read32(t, CORTEXM_CPUID);
+	uint32_t cpuid_partno = t->cpuid & CPUID_PARTNO_MASK;
+	switch (cpuid_partno) {
+	case CORTEX_M33:
 		t->core = "M33";
 		break;
-
-	case 0xd20:
+	case CORTEX_M23:
 		t->core = "M23";
 		break;
-
-	case 0xc23:
+	case CORTEX_M3:
 		t->core = "M3";
 		break;
-
-	case 0xc24:
+	case CORTEX_M4:
 		t->core = "M4";
 		break;
-
-	case 0xc27:
+	case CORTEX_M7:
 		t->core = "M7";
-		if ((((cpuid >> 20) & 0xf) == 0) && (((cpuid >> 0) & 0xf) < 2)) {
+		if (((t->cpuid & CPUID_REVISION_MASK) == 0) &&
+			(t->cpuid & CPUID_PATCH_MASK) < 2) {
 			DEBUG_WARN("Silicon bug: Single stepping will enter pending "
 					   "exception handler with this M7 core revision!\n");
 		}
 		break;
-
-	case 0xc60:
+	case CORTEX_M0P:
 		t->core = "M0+";
 		break;
-
-	case 0xc20:
+	case CORTEX_M0:
 		t->core = "M0";
 		break;
+	default:
+		DEBUG_WARN("Unexpected CortexM CPUID partno %04x\n", cpuid_partno);
 	}
 
 	t->attach = cortexm_attach;
diff --git a/src/target/cortexm.h b/src/target/cortexm.h
index f230e0b..8208785 100644
--- a/src/target/cortexm.h
+++ b/src/target/cortexm.h
@@ -171,6 +171,19 @@ extern long cortexm_wait_timeout;
 
 #define	CORTEXM_TOPT_INHIBIT_SRST (1 << 2)
 
+enum cortexm_types {
+	CORTEX_M0  = 0xc200,
+	CORTEX_M0P = 0xc600,
+	CORTEX_M3  = 0xc230,
+	CORTEX_M4  = 0xc240,
+	CORTEX_M7  = 0xc270,
+	CORTEX_M23 = 0xd200,
+	CORTEX_M33 = 0xd210,
+};
+#define CPUID_PARTNO_MASK 0xfff0
+#define CPUID_REVISION_MASK 0x00f00000
+#define CPUID_PATCH_MASK 0xf
+
 bool cortexm_probe(ADIv5_AP_t *ap);
 ADIv5_AP_t *cortexm_ap(target *t);
 
diff --git a/src/target/lpc17xx.c b/src/target/lpc17xx.c
index d410181..f62e381 100644
--- a/src/target/lpc17xx.c
+++ b/src/target/lpc17xx.c
@@ -32,9 +32,6 @@
 #define IAP_ENTRYPOINT				0x1FFF1FF1
 #define IAP_RAM_BASE				0x10000000
 
-#define ARM_CPUID					0xE000ED00
-#define CORTEX_M3_CPUID				0x412FC230	// Cortex-M3 r2p0
-#define CORTEX_M3_CPUID_MASK		0xFF00FFF0
 #define MEMMAP						0x400FC040
 #define LPC17xx_JTAG_IDCODE			0x4BA00477
 #define LPC17xx_SWDP_IDCODE			0x2BA01477
@@ -82,8 +79,7 @@ lpc17xx_probe(target *t)
 		return false;
 	}
 
-	uint32_t cpuid = target_mem_read32(t, ARM_CPUID);
-	if (((cpuid & CORTEX_M3_CPUID_MASK) == (CORTEX_M3_CPUID & CORTEX_M3_CPUID_MASK))) {
+	if ((t->cpuid & CPUID_PARTNO_MASK) == CORTEX_M3)  {
 		/*
 		 * Now that we're sure it's a Cortex-M3, we need to halt the
 		 * target and make an IAP call to get the part number.
diff --git a/src/target/lpc43xx.c b/src/target/lpc43xx.c
index a1fb214..c5a837d 100644
--- a/src/target/lpc43xx.c
+++ b/src/target/lpc43xx.c
@@ -25,7 +25,6 @@
 #include "lpc_common.h"
 
 #define LPC43XX_CHIPID	0x40043200
-#define ARM_CPUID	0xE000ED00
 
 #define IAP_ENTRYPOINT_LOCATION	0x10400100
 
@@ -80,19 +79,18 @@ void lpc43xx_add_flash(target *t, uint32_t iap_entry,
 
 bool lpc43xx_probe(target *t)
 {
-	uint32_t chipid, cpuid;
+	uint32_t chipid;
 	uint32_t iap_entry;
 
 	chipid = target_mem_read32(t, LPC43XX_CHIPID);
-	cpuid = target_mem_read32(t, ARM_CPUID);
 
 	switch(chipid) {
 	case 0x4906002B:	/* Parts with on-chip flash */
 	case 0x7906002B:	/* LM43S?? - Undocumented? */
-		switch (cpuid & 0xFF00FFF0) {
+		switch (t->cpuid & 0xFF00FFF0) {
 		case 0x4100C240:
 			t->driver = "LPC43xx Cortex-M4";
-			if (cpuid == 0x410FC241)
+			if (t->cpuid == 0x410FC241)
 			{
 				/* LPC4337 */
 				iap_entry = target_mem_read32(t,
@@ -121,7 +119,7 @@ bool lpc43xx_probe(target *t)
 		return true;
 	case 0x5906002B:	/* Flashless parts */
 	case 0x6906002B:
-		switch (cpuid & 0xFF00FFF0) {
+		switch (t->cpuid & 0xFF00FFF0) {
 		case 0x4100C240:
 			t->driver = "LPC43xx Cortex-M4";
 			break;
diff --git a/src/target/stm32f4.c b/src/target/stm32f4.c
index 33691c7..f51ce44 100644
--- a/src/target/stm32f4.c
+++ b/src/target/stm32f4.c
@@ -106,7 +106,6 @@ static int stm32f4_flash_write(struct target_flash *f,
 #define DBGMCU_IDCODE	0xE0042000
 #define DBGMCU_CR		0xE0042004
 #define DBG_SLEEP		(1 <<  0)
-#define ARM_CPUID	0xE000ED00
 
 #define AXIM_BASE 0x8000000
 #define ITCM_BASE 0x0200000
@@ -208,8 +207,7 @@ bool stm32f4_probe(target *t)
 		/* F405 revision A have a wrong IDCODE, use ARM_CPUID to make the
 		 * distinction with F205. Revision is also wrong (0x2000 instead
 		 * of 0x1000). See F40x/F41x errata. */
-		uint32_t cpuid = target_mem_read32(t, ARM_CPUID);
-		if ((cpuid & 0xFFF0) == 0xC240)
+		if ((t->cpuid & 0xFFF0) == CORTEX_M4)
 			t->idcode = ID_STM32F40X;
 	}
 	switch(t->idcode) {
diff --git a/src/target/target_internal.h b/src/target/target_internal.h
index 66ff201..58475bc 100644
--- a/src/target/target_internal.h
+++ b/src/target/target_internal.h
@@ -120,7 +120,8 @@ struct target_s {
 
 	/* Other stuff */
 	const char *driver;
-	const char *core;
+	uint32_t cpuid;
+	char *core;
 	char cmdline[MAX_CMDLINE];
 	target_addr heapinfo[4];
 	struct target_command_s *commands;