diff --git a/src/Makefile b/src/Makefile index b30922c..fcf5d1f 100644 --- a/src/Makefile +++ b/src/Makefile @@ -32,7 +32,7 @@ SRC = \ nrf51.c \ platform.c \ sam3x.c \ - samd20.c \ + samd.c \ stm32f1.c \ stm32f4.c \ stm32l1.c \ @@ -53,4 +53,3 @@ clean: host_clean -$(RM) platforms/*/*.o platforms/*/*.d mapfile -include *.d - diff --git a/src/cortexm.c b/src/cortexm.c index b7f71eb..12914d3 100644 --- a/src/cortexm.c +++ b/src/cortexm.c @@ -60,8 +60,6 @@ const struct command_s cortexm_cmd_list[] = { #define SIGTRAP 5 #define SIGSEGV 11 -static bool cortexm_attach(struct target_s *target); - static int cortexm_regs_read(struct target_s *target, void *data); static int cortexm_regs_write(struct target_s *target, const void *data); static int cortexm_pc_write(struct target_s *target, const uint32_t val); @@ -261,7 +259,7 @@ cortexm_probe(struct target_s *target) PROBE(lpc43xx_probe); PROBE(sam3x_probe); PROBE(nrf51_probe); - PROBE(samd20_probe); + PROBE(samd_probe); PROBE(lmi_probe); PROBE(kinetis_probe); #undef PROBE @@ -269,8 +267,7 @@ cortexm_probe(struct target_s *target) return true; } -static bool -cortexm_attach(struct target_s *target) +bool cortexm_attach(struct target_s *target) { ADIv5_AP_t *ap = adiv5_target_ap(target); struct cortexm_priv *priv = ap->priv; diff --git a/src/include/cortexm.h b/src/include/cortexm.h index f6170b0..f1fc07a 100644 --- a/src/include/cortexm.h +++ b/src/include/cortexm.h @@ -123,6 +123,7 @@ #define CORTEXM_DWT_FUNC_FUNC_WRITE (6 << 0) #define CORTEXM_DWT_FUNC_FUNC_ACCESS (7 << 0) +bool cortexm_attach(struct target_s *target); void cortexm_detach(struct target_s *target); void cortexm_halt_resume(struct target_s *target, bool step); diff --git a/src/include/target.h b/src/include/target.h index 100c4a0..50f1ebe 100644 --- a/src/include/target.h +++ b/src/include/target.h @@ -224,7 +224,7 @@ bool lpc11xx_probe(struct target_s *target); bool lpc43xx_probe(struct target_s *target); bool sam3x_probe(struct target_s *target); bool nrf51_probe(struct target_s *target); -bool samd20_probe(struct target_s *target); +bool samd_probe(struct target_s *target); bool kinetis_probe(struct target_s *target); #endif diff --git a/src/samd.c b/src/samd.c new file mode 100644 index 0000000..b043c50 --- /dev/null +++ b/src/samd.c @@ -0,0 +1,788 @@ +/* + * This file is part of the Black Magic Debug project. + * + * Copyright (C) 2014 Richard Meadows + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* This file implements Atmel SAM D target specific functions for + * detecting the device, providing the XML memory map and Flash memory + * programming. + * + * Tested with + * * SAMD20E17A (rev C) + * * SAMD20J18A (rev B) + * * SAMD21J18A (rev B) + * * + */ +/* Refer to the SAM D20 Datasheet: + * http://www.atmel.com/Images/Atmel-42129-SAM-D20_Datasheet.pdf + * particularly Sections 12. DSU and 20. NVMCTRL + */ + +#include +#include +#include + +#include "general.h" +#include "jtagtap.h" +#include "adiv5.h" +#include "target.h" +#include "command.h" +#include "gdb_packet.h" +#include "cortexm.h" + +static int samd_flash_erase(struct target_s *target, uint32_t addr, int len); +static int samd_flash_write(struct target_s *target, uint32_t dest, + const uint8_t *src, int len); + +static bool samd_cmd_erase_all(target *t); +static bool samd_cmd_lock_flash(target *t); +static bool samd_cmd_unlock_flash(target *t); +static bool samd_cmd_read_userrow(target *t); +static bool samd_cmd_serial(target *t); +static bool samd_cmd_mbist(target *t); +static bool samd_cmd_ssb(target *t); + +const struct command_s samd_cmd_list[] = { + {"erase_mass", (cmd_handler)samd_cmd_erase_all, "Erase entire flash memory"}, + {"lock_flash", (cmd_handler)samd_cmd_lock_flash, "Locks flash against spurious commands"}, + {"unlock_flash", (cmd_handler)samd_cmd_unlock_flash, "Unlocks flash"}, + {"user_row", (cmd_handler)samd_cmd_read_userrow, "Prints user row from flash"}, + {"serial", (cmd_handler)samd_cmd_serial, "Prints serial number"}, + {"mbist", (cmd_handler)samd_cmd_mbist, "Runs the built-in memory test"}, + {"set_security_bit", (cmd_handler)samd_cmd_ssb, "Sets the Security Bit"}, + {NULL, NULL, NULL} +}; + +/** + * 256KB Flash Max., 32KB RAM Max. The smallest unit of erase is the + * one row = 256 bytes. + */ +static const char samd_xml_memory_map[] = "" +/* ""*/ + "" + " " + " 0x100" + " " + " " + ""; + +/* Non-Volatile Memory Controller (NVMC) Parameters */ +#define SAMD_ROW_SIZE 256 +#define SAMD_PAGE_SIZE 64 + +/* -------------------------------------------------------------------------- */ +/* Non-Volatile Memory Controller (NVMC) Registers */ +/* -------------------------------------------------------------------------- */ + +#define SAMD_NVMC 0x41004000 +#define SAMD_NVMC_CTRLA (SAMD_NVMC + 0x0) +#define SAMD_NVMC_CTRLB (SAMD_NVMC + 0x04) +#define SAMD_NVMC_PARAM (SAMD_NVMC + 0x08) +#define SAMD_NVMC_INTFLAG (SAMD_NVMC + 0x14) +#define SAMD_NVMC_STATUS (SAMD_NVMC + 0x18) +#define SAMD_NVMC_ADDRESS (SAMD_NVMC + 0x1C) + +/* Control A Register (CTRLA) */ +#define SAMD_CTRLA_CMD_KEY 0xA500 +#define SAMD_CTRLA_CMD_ERASEROW 0x0002 +#define SAMD_CTRLA_CMD_WRITEPAGE 0x0004 +#define SAMD_CTRLA_CMD_ERASEAUXROW 0x0005 +#define SAMD_CTRLA_CMD_WRITEAUXPAGE 0x0006 +#define SAMD_CTRLA_CMD_LOCK 0x0040 +#define SAMD_CTRLA_CMD_UNLOCK 0x0041 +#define SAMD_CTRLA_CMD_PAGEBUFFERCLEAR 0x0044 +#define SAMD_CTRLA_CMD_SSB 0x0045 +#define SAMD_CTRLA_CMD_INVALL 0x0046 + +/* Interrupt Flag Register (INTFLAG) */ +#define SAMD_NVMC_READY (1 << 0) + +/* Non-Volatile Memory Calibration and Auxiliary Registers */ +#define SAMD_NVM_USER_ROW_LOW 0x00804000 +#define SAMD_NVM_USER_ROW_HIGH 0x00804004 +#define SAMD_NVM_CALIBRATION 0x00806020 +#define SAMD_NVM_SERIAL(n) (0x0080A00C + (0x30 * ((n + 3) / 4)) + \ + (0x4 * n)) + +/* -------------------------------------------------------------------------- */ +/* Device Service Unit (DSU) Registers */ +/* -------------------------------------------------------------------------- */ + +#define SAMD_DSU 0x41002000 +#define SAMD_DSU_EXT_ACCESS (SAMD_DSU + 0x100) +#define SAMD_DSU_CTRLSTAT (SAMD_DSU_EXT_ACCESS + 0x0) +#define SAMD_DSU_ADDRESS (SAMD_DSU_EXT_ACCESS + 0x4) +#define SAMD_DSU_LENGTH (SAMD_DSU_EXT_ACCESS + 0x8) +#define SAMD_DSU_DID (SAMD_DSU_EXT_ACCESS + 0x018) +#define SAMD_DSU_PID(n) (SAMD_DSU + 0x1FE0 + \ + (0x4 * (n % 4)) - (0x10 * (n / 4))) +#define SAMD_DSU_CID(n) (SAMD_DSU + 0x1FF0 + \ + (0x4 * (n % 4))) + +/* Control and Status Register (CTRLSTAT) */ +#define SAMD_CTRL_CHIP_ERASE (1 << 4) +#define SAMD_CTRL_MBIST (1 << 3) +#define SAMD_CTRL_CRC (1 << 2) +#define SAMD_STATUSA_PERR (1 << 12) +#define SAMD_STATUSA_FAIL (1 << 11) +#define SAMD_STATUSA_BERR (1 << 10) +#define SAMD_STATUSA_CRSTEXT (1 << 9) +#define SAMD_STATUSA_DONE (1 << 8) +#define SAMD_STATUSB_PROT (1 << 16) + +/* Device Identification Register (DID) */ +#define SAMD_DID_MASK 0xFFBC0000 +#define SAMD_DID_CONST_VALUE 0x10000000 +#define SAMD_DID_DEVSEL_MASK 0x0F +#define SAMD_DID_DEVSEL_POS 0 +#define SAMD_DID_REVISION_MASK 0x0F +#define SAMD_DID_REVISION_POS 8 +#define SAMD_DID_SERIES_MASK 0x03 +#define SAMD_DID_SERIES_POS 16 + +/* Peripheral ID */ +#define SAMD_PID_MASK 0x00F7FFFF +#define SAMD_PID_CONST_VALUE 0x0001FCD0 + +/* Component ID */ +#define SAMD_CID_VALUE 0xB105100D + +/* Utility */ +#define MINIMUM(a,b) ((a < b) ? a : b) + +/** + * Reads the SAM D20 Peripheral ID + */ +uint64_t samd_read_pid(struct target_s *target) +{ + ADIv5_AP_t *ap = adiv5_target_ap(target); + uint64_t pid = 0; + uint8_t i, j; + + /* Five PID registers to read LSB first */ + for (i = 0, j = 0; i < 5; i++, j += 8) + pid |= (adiv5_ap_mem_read(ap, SAMD_DSU_PID(i)) & 0xFF) << j; + + return pid; +} +/** + * Reads the SAM D20 Component ID + */ +uint32_t samd_read_cid(struct target_s *target) +{ + ADIv5_AP_t *ap = adiv5_target_ap(target); + uint64_t cid = 0; + uint8_t i, j; + + /* Four CID registers to read LSB first */ + for (i = 0, j = 0; i < 4; i++, j += 8) + cid |= (adiv5_ap_mem_read(ap, SAMD_DSU_CID(i)) & 0xFF) << j; + + return cid; +} + +/** + * Overloads the default cortexm reset function with a version that + * removes the target from extended reset where required. + */ +static void +samd_reset(struct target_s *target) +{ + ADIv5_AP_t *ap = adiv5_target_ap(target); + + /** + * SRST is not asserted here as it appears to reset the adiv5 + * logic, meaning that subsequent adiv5_* calls PLATFORM_FATAL_ERROR. + * + * This is ok as normally you can just connect the debugger and go, + * but if that's not possible (protection or SWCLK being used for + * something else) then having SWCLK low on reset should get you + * debug access (cold-plugging). TODO: Confirm this + * + * See the SAM D20 datasheet §12.6 Debug Operation for more + * details. + * + * jtagtap_srst(true); + * jtagtap_srst(false); + */ + + /* Read DHCSR here to clear S_RESET_ST bit before reset */ + adiv5_ap_mem_read(ap, CORTEXM_DHCSR); + + /* Request system reset from NVIC: SRST doesn't work correctly */ + /* This could be VECTRESET: 0x05FA0001 (reset only core) + * or SYSRESETREQ: 0x05FA0004 (system reset) + */ + adiv5_ap_mem_write(ap, CORTEXM_AIRCR, + CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ); + + /* Exit extended reset */ + if (adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT) & + SAMD_STATUSA_CRSTEXT) { + /* Write bit to clear from extended reset */ + adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, + SAMD_STATUSA_CRSTEXT); + } + + /* Poll for release from reset */ + while(adiv5_ap_mem_read(ap, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST); + + /* Reset DFSR flags */ + adiv5_ap_mem_write(ap, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL); + + /* Clear any target errors */ + target_check_error(target); +} + +/** + * Overloads the default cortexm detached function with a version that + * removes the target from extended reset where required. + * + * Only required for SAM D20 _Revision B_ Silicon + */ +static void +samd20_revB_detach(struct target_s *target) +{ + ADIv5_AP_t *ap = adiv5_target_ap(target); + cortexm_detach(target); + + /* ---- Additional ---- */ + /* Exit extended reset */ + if (adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT) & + SAMD_STATUSA_CRSTEXT) { + /* Write bit to clear from extended reset */ + adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, + SAMD_STATUSA_CRSTEXT); + } +} + +/** + * Overloads the default cortexm halt_resume function with a version + * that removes the target from extended reset where required. + * + * Only required for SAM D20 _Revision B_ Silicon + */ +static void +samd20_revB_halt_resume(struct target_s *target, bool step) +{ + ADIv5_AP_t *ap = adiv5_target_ap(target); + cortexm_halt_resume(target, step); + + /* ---- Additional ---- */ + /* Exit extended reset */ + if (adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT) & + SAMD_STATUSA_CRSTEXT) { + /* Write bit to clear from extended reset */ + adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, + SAMD_STATUSA_CRSTEXT); + } +} + +/** + * Overload the default cortexm attach for when the samd is protected. + * + * If the samd is protected then the default cortexm attach will + * fail as the S_HALT bit in the DHCSR will never go high. This + * function allows users to attach on a temporary basis so they can + * rescue the device. + */ +static bool +samd_protected_attach(struct target_s *target) +{ + /** + * TODO: Notify the user that we're not really attached and + * they should issue the 'monitor erase_mass' command to + * regain access to the chip. + */ + + /* Patch back in the normal cortexm attach for next time */ + target->attach = cortexm_attach; + + /* Allow attach this time */ + return true; +} + +/** + * Use the DSU Device Indentification Register to populate a struct + * describing the SAM D device. + */ +struct samd_descr { + uint8_t series; + char revision; + char pin; + uint8_t mem; + char package[3]; +}; +struct samd_descr samd_parse_device_id(uint32_t did) +{ + struct samd_descr samd; + memset(samd.package, 0, 3); + + uint8_t series = (did >> SAMD_DID_SERIES_POS) + & SAMD_DID_SERIES_MASK; + uint8_t revision = (did >> SAMD_DID_REVISION_POS) + & SAMD_DID_REVISION_MASK; + uint8_t devsel = (did >> SAMD_DID_DEVSEL_POS) + & SAMD_DID_DEVSEL_MASK; + + /* Series */ + switch (series) { + case 0: samd.series = 20; break; + case 1: samd.series = 21; break; + case 2: samd.series = 10; break; + case 3: samd.series = 11; break; + } + /* Revision */ + samd.revision = 'A' + revision; + + switch (samd.series) { + case 20: /* SAM D20 */ + case 21: /* SAM D21 */ + switch (devsel / 5) { + case 0: samd.pin = 'J'; break; + case 1: samd.pin = 'G'; break; + case 2: samd.pin = 'E'; break; + default: samd.pin = 'u'; break; + } + samd.mem = 18 - (devsel % 5); + break; + case 10: /* SAM D10 */ + case 11: /* SAM D11 */ + switch (devsel / 3) { + case 0: samd.package[0] = 'M'; break; + case 1: samd.package[0] = 'S'; samd.package[1] = 'S'; break; + } + samd.pin = 'D'; + samd.mem = 14 - (devsel % 3); + break; + } + + return samd; +} + + +char variant_string[40]; +bool samd_probe(struct target_s *target) +{ + ADIv5_AP_t *ap = adiv5_target_ap(target); + uint32_t cid = samd_read_cid(target); + uint32_t pid = samd_read_pid(target); + + /* Check the ARM Coresight Component and Perhiperal IDs */ + if (cid == SAMD_CID_VALUE && + (pid & SAMD_PID_MASK) == SAMD_PID_CONST_VALUE) { + + /* Read the Device ID */ + uint32_t did = adiv5_ap_mem_read(ap, SAMD_DSU_DID); + + /* If the Device ID matches */ + if ((did & SAMD_DID_MASK) == SAMD_DID_CONST_VALUE) { + + uint32_t ctrlstat = adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT); + struct samd_descr samd = samd_parse_device_id(did); + + /* Protected? */ + int protected = (ctrlstat & SAMD_STATUSB_PROT); + + /* Part String */ + if (protected) { + sprintf(variant_string, + "Atmel SAMD%d%c%dA%s (rev %c) (PROT=1)", + samd.series, samd.pin, samd.mem, + samd.package, samd.revision); + } else { + sprintf(variant_string, + "Atmel SAMD%d%c%dA%s (rev %c)", + samd.series, samd.pin, samd.mem, + samd.package, samd.revision); + } + + /* Setup Target */ + target->driver = variant_string; + target->reset = samd_reset; + + if (samd.series == 20 && samd.revision == 'B') { + /** + * These functions check for and + * extended reset. Appears to be + * related to Errata 35.4.1 ref 12015 + */ + target->detach = samd20_revB_detach; + target->halt_resume = samd20_revB_halt_resume; + } + if (protected) { + /** + * Overload the default cortexm attach + * for when the samd is protected. + * This function allows users to + * attach on a temporary basis so they + * can rescue the device. + */ + target->attach = samd_protected_attach; + } + + target->xml_mem_map = samd_xml_memory_map; + target->flash_erase = samd_flash_erase; + target->flash_write = samd_flash_write; + target_add_commands(target, samd_cmd_list, "SAMD"); + + /* If we're not in reset here */ + if (!connect_assert_srst) { + /* We'll have to release the target from + * extended reset to make attach possible */ + if (adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT) & + SAMD_STATUSA_CRSTEXT) { + + /* Write bit to clear from extended reset */ + adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, + SAMD_STATUSA_CRSTEXT); + } + } + + return true; + } + } + + return false; +} + +/** + * Temporary (until next reset) flash memory locking / unlocking + */ +static void samd_lock_current_address(struct target_s *target) +{ + ADIv5_AP_t *ap = adiv5_target_ap(target); + + /* Issue the unlock command */ + adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_LOCK); +} +static void samd_unlock_current_address(struct target_s *target) +{ + ADIv5_AP_t *ap = adiv5_target_ap(target); + + /* Issue the unlock command */ + adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_UNLOCK); +} + +/** + * Erase flash row by row + */ +static int samd_flash_erase(struct target_s *target, uint32_t addr, int len) +{ + ADIv5_AP_t *ap = adiv5_target_ap(target); + + addr &= ~(SAMD_ROW_SIZE - 1); + len &= ~(SAMD_ROW_SIZE - 1); + + while (len) { + /* Write address of first word in row to erase it */ + /* Must be shifted right for 16-bit address, see Datasheet §20.8.8 Address */ + adiv5_ap_mem_write(ap, SAMD_NVMC_ADDRESS, addr >> 1); + + /* Unlock */ + samd_unlock_current_address(target); + + /* Issue the erase command */ + adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_ERASEROW); + /* Poll for NVM Ready */ + while ((adiv5_ap_mem_read(ap, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) + if(target_check_error(target)) + return -1; + + /* Lock */ + samd_lock_current_address(target); + + addr += SAMD_ROW_SIZE; + len -= SAMD_ROW_SIZE; + } + + return 0; +} + +/** + * Write flash page by page + */ +static int samd_flash_write(struct target_s *target, uint32_t dest, + const uint8_t *src, int len) +{ + ADIv5_AP_t *ap = adiv5_target_ap(target); + + /* Find the size of our 32-bit data buffer */ + uint32_t offset = dest % 4; + uint32_t words = (offset + len + 3) / 4; + uint32_t data[words], i = 0; + + /* Populate the data buffer */ + memset((uint8_t *)data, 0xFF, words * 4); + memcpy((uint8_t *)data + offset, src, len); + + /* The address of the first word involved in the write */ + uint32_t addr = dest & ~0x3; + /* The address of the last word involved in the write */ + uint32_t end = (dest + len - 1) & ~0x3; + + /* The start address of the first page involved in the write */ + uint32_t first_page = dest & ~(SAMD_PAGE_SIZE - 1); + /* The start address of the last page involved in the write */ + uint32_t last_page = (dest + len - 1) & ~(SAMD_PAGE_SIZE - 1); + uint32_t end_of_this_page; + + + for (uint32_t page = first_page; page <= last_page; page += SAMD_PAGE_SIZE) { + end_of_this_page = page + (SAMD_PAGE_SIZE - 4); + + if (addr > page || (page == last_page && end < end_of_this_page)) { + /* Setup write */ + adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | + ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE); + adiv5_ap_write(ap, ADIV5_AP_TAR, addr); + adiv5_dp_write(ap->dp, ADIV5_DP_SELECT, + ((uint32_t)ap->apsel << 24)|(ADIV5_AP_DRW & 0xF0)); + + /* Partial, manual page write */ + for (; addr <= MINIMUM(end, end_of_this_page); addr += 4, i++) { + adiv5_dp_write_ap(ap->dp, ADIV5_AP_DRW, data[i]); + } + + /* Unlock */ + samd_unlock_current_address(target); + + /* Issue the write page command */ + adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, + SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_WRITEPAGE); + } else { + /* Write first word to set address */ + adiv5_ap_mem_write(ap, addr, data[i]); addr += 4; i++; + + /* Unlock */ + samd_unlock_current_address(target); + + /* Set up write */ + adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | + ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE); + adiv5_ap_write(ap, ADIV5_AP_TAR, addr); + adiv5_dp_write(ap->dp, ADIV5_DP_SELECT, + ((uint32_t)ap->apsel << 24)|(ADIV5_AP_DRW & 0xF0)); + + /* Full, automatic page write */ + for (; addr < page + SAMD_PAGE_SIZE; addr += 4, i++) { + adiv5_dp_write_ap(ap->dp, ADIV5_AP_DRW, data[i]); + } + } + + /* Poll for NVM Ready */ + while ((adiv5_ap_mem_read(ap, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) + if(target_check_error(target)) + return -1; + + /* Lock */ + samd_lock_current_address(target); + } + + return 0; +} + +/** + * Uses the Device Service Unit to erase the entire flash + */ +static bool samd_cmd_erase_all(target *t) +{ + ADIv5_AP_t *ap = adiv5_target_ap(t); + + /* Clear the DSU status bits */ + adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, + (SAMD_STATUSA_DONE | SAMD_STATUSA_PERR | SAMD_STATUSA_FAIL)); + + /* Erase all */ + adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, SAMD_CTRL_CHIP_ERASE); + + /* Poll for DSU Ready */ + uint32_t status; + while (((status = adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT)) & + (SAMD_STATUSA_DONE | SAMD_STATUSA_PERR | SAMD_STATUSA_FAIL)) == 0) + if(target_check_error(t)) + return false; + + /* Test the protection error bit in Status A */ + if (status & SAMD_STATUSA_PERR) { + gdb_outf("Erase failed due to a protection error.\n"); + return true; + } + + /* Test the fail bit in Status A */ + if (status & SAMD_STATUSA_FAIL) { + gdb_outf("Erase failed.\n"); + return true; + } + + gdb_outf("Erase successful!\n"); + + return true; +} + +/** + * Sets the NVM region lock bits in the User Row. This value is read + * at startup as the default value for the lock bits, and hence does + * not take effect until a reset. + * + * 0x0000 = Lock, 0xFFFF = Unlock (default) + */ +static bool samd_set_flashlock(target *t, uint16_t value) +{ + ADIv5_AP_t *ap = adiv5_target_ap(t); + + uint32_t high = adiv5_ap_mem_read(ap, SAMD_NVM_USER_ROW_HIGH); + uint32_t low = adiv5_ap_mem_read(ap, SAMD_NVM_USER_ROW_LOW); + + /* Write address of a word in the row to erase it */ + /* Must be shifted right for 16-bit address, see Datasheet §20.8.8 Address */ + adiv5_ap_mem_write(ap, SAMD_NVMC_ADDRESS, SAMD_NVM_USER_ROW_LOW >> 1); + + /* Issue the erase command */ + adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_ERASEAUXROW); + + /* Poll for NVM Ready */ + while ((adiv5_ap_mem_read(ap, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) + if(target_check_error(t)) + return -1; + + /* Modify the high byte of the user row */ + high = (high & 0x0000FFFF) | ((value << 16) & 0xFFFF0000); + + /* Write back */ + adiv5_ap_mem_write(ap, SAMD_NVM_USER_ROW_LOW, low); + adiv5_ap_mem_write(ap, SAMD_NVM_USER_ROW_HIGH, high); + + /* Issue the page write command */ + adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, + SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_WRITEAUXPAGE); + + return true; +} +static bool samd_cmd_lock_flash(target *t) +{ + return samd_set_flashlock(t, 0x0000); +} +static bool samd_cmd_unlock_flash(target *t) +{ + return samd_set_flashlock(t, 0xFFFF); +} +static bool samd_cmd_read_userrow(target *t) +{ + ADIv5_AP_t *ap = adiv5_target_ap(t); + + gdb_outf("User Row: 0x%08x%08x\n", + adiv5_ap_mem_read(ap, SAMD_NVM_USER_ROW_HIGH), + adiv5_ap_mem_read(ap, SAMD_NVM_USER_ROW_LOW)); + + return true; +} +/** + * Reads the 128-bit serial number from the NVM + */ +static bool samd_cmd_serial(target *t) +{ + ADIv5_AP_t *ap = adiv5_target_ap(t); + + gdb_outf("Serial Number: 0x"); + + for (uint32_t i = 0; i < 4; i++) { + gdb_outf("%08x", adiv5_ap_mem_read(ap, SAMD_NVM_SERIAL(i))); + } + + gdb_outf("\n"); + + return true; +} +/** + * Returns the size (in bytes) of the current SAM D20's flash memory. + */ +static uint32_t samd_flash_size(target *t) +{ + ADIv5_AP_t *ap = adiv5_target_ap(t); + + /* Read the Device ID */ + uint32_t did = adiv5_ap_mem_read(ap, SAMD_DSU_DID); + + /* Mask off the device select bits */ + uint8_t devsel = did & SAMD_DID_DEVSEL_MASK; + + /* Shift the maximum flash size (256KB) down as appropriate */ + return (0x40000 >> (devsel % 5)); +} +/** + * Runs the Memory Built In Self Test (MBIST) + */ +static bool samd_cmd_mbist(target *t) +{ + ADIv5_AP_t *ap = adiv5_target_ap(t); + + /* Write the memory parameters to the DSU */ + adiv5_ap_mem_write(ap, SAMD_DSU_ADDRESS, 0); + adiv5_ap_mem_write(ap, SAMD_DSU_LENGTH, samd_flash_size(t)); + + /* Clear the fail bit */ + adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, SAMD_STATUSA_FAIL); + + /* Write the MBIST command */ + adiv5_ap_mem_write(ap, SAMD_DSU_CTRLSTAT, SAMD_CTRL_MBIST); + + /* Poll for DSU Ready */ + uint32_t status; + while (((status = adiv5_ap_mem_read(ap, SAMD_DSU_CTRLSTAT)) & + (SAMD_STATUSA_DONE | SAMD_STATUSA_PERR | SAMD_STATUSA_FAIL)) == 0) + if(target_check_error(t)) + return false; + + /* Test the protection error bit in Status A */ + if (status & SAMD_STATUSA_PERR) { + gdb_outf("MBIST not run due to protection error.\n"); + return true; + } + + /* Test the fail bit in Status A */ + if (status & SAMD_STATUSA_FAIL) { + gdb_outf("MBIST Fail @ 0x%08x\n", + adiv5_ap_mem_read(ap, SAMD_DSU_ADDRESS)); + } else { + gdb_outf("MBIST Passed!\n"); + } + + return true; +} +/** + * Sets the security bit + */ +static bool samd_cmd_ssb(target *t) +{ + ADIv5_AP_t *ap = adiv5_target_ap(t); + + /* Issue the ssb command */ + adiv5_ap_mem_write(ap, SAMD_NVMC_CTRLA, SAMD_CTRLA_CMD_KEY | SAMD_CTRLA_CMD_SSB); + + /* Poll for NVM Ready */ + while ((adiv5_ap_mem_read(ap, SAMD_NVMC_INTFLAG) & SAMD_NVMC_READY) == 0) + if(target_check_error(t)) + return -1; + + gdb_outf("Set the security bit! " + "You will need to issue 'monitor erase_mass' to clear this.\n"); + + return true; +} diff --git a/src/samd20.c b/src/samd20.c deleted file mode 100644 index b252524..0000000 --- a/src/samd20.c +++ /dev/null @@ -1,644 +0,0 @@ -/* - * This file is part of the Black Magic Debug project. - * - * Copyright (C) 2014 Richard Meadows - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -/* This file implements Atmel SAM D20 target specific functions for - * detecting the device, providing the XML memory map and Flash memory - * programming. - */ -/* Refer to the SAM D20 Datasheet: - * http://www.atmel.com/Images/Atmel-42129-SAM-D20_Datasheet.pdf - * particularly Sections 12. DSU and 20. NVMCTRL - */ -/* TODO: Support for the NVMCTRL Security Bit. If this is set then the - * device will probably not even be detected. - */ - -#include -#include -#include - -#include "general.h" -#include "jtagtap.h" -#include "adiv5.h" -#include "target.h" -#include "command.h" -#include "gdb_packet.h" -#include "cortexm.h" - -static int samd20_flash_erase(struct target_s *target, uint32_t addr, int len); -static int samd20_flash_write(struct target_s *target, uint32_t dest, - const uint8_t *src, int len); - -static bool samd20_cmd_erase_all(target *t); -static bool samd20_cmd_lock_flash(target *t); -static bool samd20_cmd_unlock_flash(target *t); -static bool samd20_cmd_read_userrow(target *t); -static bool samd20_cmd_serial(target *t); -static bool samd20_cmd_mbist(target *t); - -const struct command_s samd20_cmd_list[] = { - {"erase_mass", (cmd_handler)samd20_cmd_erase_all, "Erase entire flash memory"}, - {"lock_flash", (cmd_handler)samd20_cmd_lock_flash, "Locks flash against spurious commands"}, - {"unlock_flash", (cmd_handler)samd20_cmd_unlock_flash, "Unlocks flash"}, - {"user_row", (cmd_handler)samd20_cmd_read_userrow, "Prints user row from flash"}, - {"serial", (cmd_handler)samd20_cmd_serial, "Prints serial number"}, - {"mbist", (cmd_handler)samd20_cmd_mbist, "Runs the built-in memory test"}, - {NULL, NULL, NULL} -}; - -/** - * 256KB Flash Max., 32KB RAM Max. The smallest unit of erase is the - * one row = 256 bytes. - */ -static const char samd20_xml_memory_map[] = "" -/* ""*/ - "" - " " - " 0x100" - " " - " " - ""; - -/* Non-Volatile Memory Controller (NVMC) Parameters */ -#define SAMD20_ROW_SIZE 256 -#define SAMD20_PAGE_SIZE 64 - -/* Non-Volatile Memory Controller (NVMC) Registers */ -#define SAMD20_NVMC 0x41004000 -#define SAMD20_NVMC_CMD (SAMD20_NVMC + 0x0) -#define SAMD20_NVMC_PARAM (SAMD20_NVMC + 0x08) -#define SAMD20_NVMC_INTFLAG (SAMD20_NVMC + 0x14) -#define SAMD20_NVMC_STATUS (SAMD20_NVMC + 0x18) -#define SAMD20_NVMC_ADDRESS (SAMD20_NVMC + 0x1C) - -/* Command Register (CMD) */ -#define SAMD20_CMD_KEY 0xA500 -#define SAMD20_CMD_ERASEROW 0x0002 -#define SAMD20_CMD_WRITEPAGE 0x0004 -#define SAMD20_CMD_ERASEAUXROW 0x0005 -#define SAMD20_CMD_WRITEAUXPAGE 0x0006 -#define SAMD20_CMD_LOCK 0x0040 -#define SAMD20_CMD_UNLOCK 0x0041 -#define SAMD20_CMD_PAGEBUFFERCLEAR 0x0044 - -/* Interrupt Flag Register (INTFLAG) */ -#define SAMD20_NVMC_READY (1 << 0) - -/* Non-Volatile Memory Calibration and Auxiliary Registers */ -#define SAMD20_NVM_USER_ROW_LOW 0x00804000 -#define SAMD20_NVM_USER_ROW_HIGH 0x00804004 -#define SAMD20_NVM_CALIBRATION 0x00806020 -#define SAMD20_NVM_SERIAL(n) (0x0080A00C + (0x30 * ((n + 3) / 4)) + \ - (0x4 * n)) - -/* Device Service Unit (DSU) Registers */ -#define SAMD20_DSU 0x41002000 -#define SAMD20_DSU_EXT_ACCESS (SAMD20_DSU + 0x100) -#define SAMD20_DSU_CTRLSTAT (SAMD20_DSU_EXT_ACCESS + 0x0) -#define SAMD20_DSU_ADDRESS (SAMD20_DSU_EXT_ACCESS + 0x4) -#define SAMD20_DSU_LENGTH (SAMD20_DSU_EXT_ACCESS + 0x8) -#define SAMD20_DSU_DID (SAMD20_DSU_EXT_ACCESS + 0x018) -#define SAMD20_DSU_PID(n) (SAMD20_DSU + 0x1FE0 + \ - (0x4 * (n % 4)) - (0x10 * (n / 4))) -#define SAMD20_DSU_CID(n) (SAMD20_DSU + 0x1FF0 + \ - (0x4 * (n % 4))) - -/* Control and Status Register (CTRLSTAT) */ -#define SAMD20_CTRL_CHIP_ERASE (1 << 4) -#define SAMD20_CTRL_MBIST (1 << 3) -#define SAMD20_CTRL_CRC (1 << 2) -#define SAMD20_STATUSA_PERR (1 << 12) -#define SAMD20_STATUSA_FAIL (1 << 11) -#define SAMD20_STATUSA_BERR (1 << 10) -#define SAMD20_STATUSA_CRSTEXT (1 << 9) -#define SAMD20_STATUSA_DONE (1 << 8) - -/* Device Identification Register (DID) */ -#define SAMD20_DID_MASK 0xFFBF0000 -#define SAMD20_DID_CONST_VALUE 0x10000000 -#define SAMD20_DID_DEVSEL_MASK 0x0F -#define SAMD20_DID_DEVSEL_POS 0 -#define SAMD20_DID_REVISION_MASK 0x0F -#define SAMD20_DID_REVISION_POS 8 - -/* Peripheral ID */ -#define SAMD20_PID_MASK 0x00F7FFFF -#define SAMD20_PID_CONST_VALUE 0x0001FCD0 - -/* Component ID */ -#define SAMD20_CID_VALUE 0xB105100D - -/* Utility */ -#define MINIMUM(a,b) ((a < b) ? a : b) - -/** - * Reads the SAM D20 Peripheral ID - */ -uint64_t samd20_read_pid(struct target_s *target) -{ - ADIv5_AP_t *ap = adiv5_target_ap(target); - uint64_t pid = 0; - uint8_t i, j; - - /* Five PID registers to read LSB first */ - for (i = 0, j = 0; i < 5; i++, j += 8) - pid |= (adiv5_ap_mem_read(ap, SAMD20_DSU_PID(i)) & 0xFF) << j; - - return pid; -} -/** - * Reads the SAM D20 Component ID - */ -uint32_t samd20_read_cid(struct target_s *target) -{ - ADIv5_AP_t *ap = adiv5_target_ap(target); - uint64_t cid = 0; - uint8_t i, j; - - /* Four CID registers to read LSB first */ - for (i = 0, j = 0; i < 4; i++, j += 8) - cid |= (adiv5_ap_mem_read(ap, SAMD20_DSU_CID(i)) & 0xFF) << j; - - return cid; -} - -/** - * Overloads the default cortexm reset function with a version that - * removes the target from extended reset where required. - */ -static void -samd20_reset(struct target_s *target) -{ - ADIv5_AP_t *ap = adiv5_target_ap(target); - - /** - * SRST is not asserted here as it appears to reset the adiv5 - * logic, meaning that subsequent adiv5_* calls PLATFORM_FATAL_ERROR. - * - * This is ok as normally you can just connect the debugger and go, - * but if that's not possible (protection or SWCLK being used for - * something else) then having SWCLK low on reset should get you - * debug access (cold-plugging). TODO: Confirm this - * - * See the SAM D20 datasheet §12.6 Debug Operation for more - * details. - * - * jtagtap_srst(true); - * jtagtap_srst(false); - */ - - /* Read DHCSR here to clear S_RESET_ST bit before reset */ - adiv5_ap_mem_read(ap, CORTEXM_DHCSR); - - /* Request system reset from NVIC: SRST doesn't work correctly */ - /* This could be VECTRESET: 0x05FA0001 (reset only core) - * or SYSRESETREQ: 0x05FA0004 (system reset) - */ - adiv5_ap_mem_write(ap, CORTEXM_AIRCR, - CORTEXM_AIRCR_VECTKEY | CORTEXM_AIRCR_SYSRESETREQ); - - /* Exit extended reset */ - if (adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) & - SAMD20_STATUSA_CRSTEXT) { - /* Write bit to clear from extended reset */ - adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, - SAMD20_STATUSA_CRSTEXT); - } - - /* Poll for release from reset */ - while(adiv5_ap_mem_read(ap, CORTEXM_DHCSR) & CORTEXM_DHCSR_S_RESET_ST); - - /* Reset DFSR flags */ - adiv5_ap_mem_write(ap, CORTEXM_DFSR, CORTEXM_DFSR_RESETALL); - - /* Clear any target errors */ - target_check_error(target); -} - -/** - * Overloads the default cortexm detached function with a version that - * removes the target from extended reset where required. - * - * Only required for SAM D20 _Revision B_ Silicon - */ -static void -samd20_revB_detach(struct target_s *target) -{ - ADIv5_AP_t *ap = adiv5_target_ap(target); - cortexm_detach(target); - - /* ---- Additional ---- */ - /* Exit extended reset */ - if (adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) & - SAMD20_STATUSA_CRSTEXT) { - /* Write bit to clear from extended reset */ - adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, - SAMD20_STATUSA_CRSTEXT); - } -} - -/** - * Overloads the default cortexm halt_resume function with a version - * that removes the target from extended reset where required. - * - * Only required for SAM D20 _Revision B_ Silicon - */ -static void -samd20_revB_halt_resume(struct target_s *target, bool step) -{ - ADIv5_AP_t *ap = adiv5_target_ap(target); - cortexm_halt_resume(target, step); - - /* ---- Additional ---- */ - /* Exit extended reset */ - if (adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) & - SAMD20_STATUSA_CRSTEXT) { - /* Write bit to clear from extended reset */ - adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, - SAMD20_STATUSA_CRSTEXT); - } -} - - -char variant_string[30]; -bool samd20_probe(struct target_s *target) -{ - ADIv5_AP_t *ap = adiv5_target_ap(target); - uint32_t cid = samd20_read_cid(target); - uint32_t pid = samd20_read_pid(target); - - /* Check the ARM Coresight Component and Perhiperal IDs */ - if (cid == SAMD20_CID_VALUE && - (pid & SAMD20_PID_MASK) == SAMD20_PID_CONST_VALUE) { - - /* Read the Device ID */ - uint32_t did = adiv5_ap_mem_read(ap, SAMD20_DSU_DID); - - /* If the Device ID matches */ - if ((did & SAMD20_DID_MASK) == SAMD20_DID_CONST_VALUE) { - - uint8_t devsel = (did >> SAMD20_DID_DEVSEL_POS) - & SAMD20_DID_DEVSEL_MASK; - uint8_t revision = (did >> SAMD20_DID_REVISION_POS) - & SAMD20_DID_REVISION_MASK; - - /* Pin Variant */ - char pin_variant; - switch (devsel / 5) { - case 0: pin_variant = 'J'; break; - case 1: pin_variant = 'G'; break; - case 2: pin_variant = 'E'; break; - default: pin_variant = 'u'; break; - } - - /* Mem Variant */ - uint8_t mem_variant = 18 - (devsel % 5); - - /* Revision */ - char revision_variant = 'A' + revision; - - /* Part String */ - sprintf(variant_string, "Atmel SAMD20%c%dA (rev %c)", - pin_variant, mem_variant, revision_variant); - - /* Setup Target */ - target->driver = variant_string; - target->reset = samd20_reset; - - if (revision_variant == 'B') { - /** - * These functions check for and - * extended reset. Appears to be - * related to Errata 35.4.1 ref 12015 - */ - target->detach = samd20_revB_detach; - target->halt_resume = samd20_revB_halt_resume; - } - - target->xml_mem_map = samd20_xml_memory_map; - target->flash_erase = samd20_flash_erase; - target->flash_write = samd20_flash_write; - target_add_commands(target, samd20_cmd_list, "SAMD20"); - - /* If we're not in reset here */ - if (!connect_assert_srst) { - /* We'll have to release the target from - * extended reset to make attach possible */ - if (adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) & - SAMD20_STATUSA_CRSTEXT) { - - /* Write bit to clear from extended reset */ - adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, - SAMD20_STATUSA_CRSTEXT); - } - } - - return true; - } - } - - return false; -} - -/** - * Temporary (until next reset) flash memory locking / unlocking - */ -static void samd20_lock_current_address(struct target_s *target) -{ - ADIv5_AP_t *ap = adiv5_target_ap(target); - - /* Issue the unlock command */ - adiv5_ap_mem_write(ap, SAMD20_NVMC_CMD, SAMD20_CMD_KEY | SAMD20_CMD_LOCK); -} -static void samd20_unlock_current_address(struct target_s *target) -{ - ADIv5_AP_t *ap = adiv5_target_ap(target); - - /* Issue the unlock command */ - adiv5_ap_mem_write(ap, SAMD20_NVMC_CMD, SAMD20_CMD_KEY | SAMD20_CMD_UNLOCK); -} - -/** - * Erase flash row by row - */ -static int samd20_flash_erase(struct target_s *target, uint32_t addr, int len) -{ - ADIv5_AP_t *ap = adiv5_target_ap(target); - - addr &= ~(SAMD20_ROW_SIZE - 1); - len &= ~(SAMD20_ROW_SIZE - 1); - - while (len) { - /* Write address of first word in row to erase it */ - /* Must be shifted right for 16-bit address, see Datasheet §20.8.8 Address */ - adiv5_ap_mem_write(ap, SAMD20_NVMC_ADDRESS, addr >> 1); - - /* Unlock */ - samd20_unlock_current_address(target); - - /* Issue the erase command */ - adiv5_ap_mem_write(ap, SAMD20_NVMC_CMD, SAMD20_CMD_KEY | SAMD20_CMD_ERASEROW); - /* Poll for NVM Ready */ - while ((adiv5_ap_mem_read(ap, SAMD20_NVMC_INTFLAG) & SAMD20_NVMC_READY) == 0) - if(target_check_error(target)) - return -1; - - /* Lock */ - samd20_lock_current_address(target); - - addr += SAMD20_ROW_SIZE; - len -= SAMD20_ROW_SIZE; - } - - return 0; -} - -/** - * Write flash page by page - */ -static int samd20_flash_write(struct target_s *target, uint32_t dest, - const uint8_t *src, int len) -{ - ADIv5_AP_t *ap = adiv5_target_ap(target); - - /* Find the size of our 32-bit data buffer */ - uint32_t offset = dest % 4; - uint32_t words = (offset + len + 3) / 4; - uint32_t data[words], i = 0; - - /* Populate the data buffer */ - memset((uint8_t *)data, 0xFF, words * 4); - memcpy((uint8_t *)data + offset, src, len); - - /* The address of the first word involved in the write */ - uint32_t addr = dest & ~0x3; - /* The address of the last word involved in the write */ - uint32_t end = (dest + len - 1) & ~0x3; - - /* The start address of the first page involved in the write */ - uint32_t first_page = dest & ~(SAMD20_PAGE_SIZE - 1); - /* The start address of the last page involved in the write */ - uint32_t last_page = (dest + len - 1) & ~(SAMD20_PAGE_SIZE - 1); - uint32_t end_of_this_page; - - - for (uint32_t page = first_page; page <= last_page; page += SAMD20_PAGE_SIZE) { - end_of_this_page = page + (SAMD20_PAGE_SIZE - 4); - - if (addr > page || (page == last_page && end < end_of_this_page)) { - /* Setup write */ - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_ap_write(ap, ADIV5_AP_TAR, addr); - adiv5_dp_write(ap->dp, ADIV5_DP_SELECT, - ((uint32_t)ap->apsel << 24)|(ADIV5_AP_DRW & 0xF0)); - - /* Partial, manual page write */ - for (; addr <= MINIMUM(end, end_of_this_page); addr += 4, i++) { - adiv5_dp_write_ap(ap->dp, ADIV5_AP_DRW, data[i]); - } - - /* Unlock */ - samd20_unlock_current_address(target); - - /* Issue the write page command */ - adiv5_ap_mem_write(ap, SAMD20_NVMC_CMD, - SAMD20_CMD_KEY | SAMD20_CMD_WRITEPAGE); - } else { - /* Write first word to set address */ - adiv5_ap_mem_write(ap, addr, data[i]); addr += 4; i++; - - /* Unlock */ - samd20_unlock_current_address(target); - - /* Set up write */ - adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | - ADIV5_AP_CSW_SIZE_WORD | ADIV5_AP_CSW_ADDRINC_SINGLE); - adiv5_ap_write(ap, ADIV5_AP_TAR, addr); - adiv5_dp_write(ap->dp, ADIV5_DP_SELECT, - ((uint32_t)ap->apsel << 24)|(ADIV5_AP_DRW & 0xF0)); - - /* Full, automatic page write */ - for (; addr < page + SAMD20_PAGE_SIZE; addr += 4, i++) { - adiv5_dp_write_ap(ap->dp, ADIV5_AP_DRW, data[i]); - } - } - - /* Poll for NVM Ready */ - while ((adiv5_ap_mem_read(ap, SAMD20_NVMC_INTFLAG) & SAMD20_NVMC_READY) == 0) - if(target_check_error(target)) - return -1; - - /* Lock */ - samd20_lock_current_address(target); - } - - return 0; -} - -/** - * Uses the Device Service Unit to erase the entire flash - */ -static bool samd20_cmd_erase_all(target *t) -{ - ADIv5_AP_t *ap = adiv5_target_ap(t); - - /* Erase all */ - adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, SAMD20_CTRL_CHIP_ERASE); - - /* Poll for DSU Ready */ - while ((adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT) & SAMD20_STATUSA_DONE) == 0) - if(target_check_error(t)) - return false; - - return true; -} - -/** - * Sets the NVM region lock bits in the User Row. This value is read - * at startup as the default value for the lock bits, and hence does - * not take effect until a reset. - * - * 0x0000 = Lock, 0xFFFF = Unlock (default) - */ -static bool samd20_set_flashlock(target *t, uint16_t value) -{ - ADIv5_AP_t *ap = adiv5_target_ap(t); - - uint32_t high = adiv5_ap_mem_read(ap, SAMD20_NVM_USER_ROW_HIGH); - uint32_t low = adiv5_ap_mem_read(ap, SAMD20_NVM_USER_ROW_LOW); - - /* Write address of a word in the row to erase it */ - /* Must be shifted right for 16-bit address, see Datasheet §20.8.8 Address */ - adiv5_ap_mem_write(ap, SAMD20_NVMC_ADDRESS, SAMD20_NVM_USER_ROW_LOW >> 1); - - /* Issue the erase command */ - adiv5_ap_mem_write(ap, SAMD20_NVMC_CMD, SAMD20_CMD_KEY | SAMD20_CMD_ERASEAUXROW); - - /* Poll for NVM Ready */ - while ((adiv5_ap_mem_read(ap, SAMD20_NVMC_INTFLAG) & SAMD20_NVMC_READY) == 0) - if(target_check_error(t)) - return -1; - - /* Modify the high byte of the user row */ - high = (high & 0x0000FFFF) | ((value << 16) & 0xFFFF0000); - - /* Write back */ - adiv5_ap_mem_write(ap, SAMD20_NVM_USER_ROW_LOW, low); - adiv5_ap_mem_write(ap, SAMD20_NVM_USER_ROW_HIGH, high); - - /* Issue the page write command */ - adiv5_ap_mem_write(ap, SAMD20_NVMC_CMD, - SAMD20_CMD_KEY | SAMD20_CMD_WRITEAUXPAGE); - - return true; -} -static bool samd20_cmd_lock_flash(target *t) -{ - return samd20_set_flashlock(t, 0x0000); -} -static bool samd20_cmd_unlock_flash(target *t) -{ - return samd20_set_flashlock(t, 0xFFFF); -} -static bool samd20_cmd_read_userrow(target *t) -{ - ADIv5_AP_t *ap = adiv5_target_ap(t); - - gdb_outf("User Row: 0x%08x%08x\n", - adiv5_ap_mem_read(ap, SAMD20_NVM_USER_ROW_HIGH), - adiv5_ap_mem_read(ap, SAMD20_NVM_USER_ROW_LOW)); - - return true; -} -/** - * Reads the 128-bit serial number from the NVM - */ -static bool samd20_cmd_serial(target *t) -{ - ADIv5_AP_t *ap = adiv5_target_ap(t); - - gdb_outf("Serial Number: 0x"); - - for (uint32_t i = 0; i < 4; i++) { - gdb_outf("%08x", adiv5_ap_mem_read(ap, SAMD20_NVM_SERIAL(i))); - } - - gdb_outf("\n"); - - return true; -} -/** - * Returns the size (in bytes) of the current SAM D20's flash memory. - */ -static uint32_t samd20_flash_size(target *t) -{ - ADIv5_AP_t *ap = adiv5_target_ap(t); - - /* Read the Device ID */ - uint32_t did = adiv5_ap_mem_read(ap, SAMD20_DSU_DID); - - /* Mask off the device select bits */ - uint8_t devsel = did & SAMD20_DID_DEVSEL_MASK; - - /* Shift the maximum flash size (256KB) down as appropriate */ - return (0x40000 >> (devsel % 5)); -} -/** - * Runs the Memory Built In Self Test (MBIST) - */ -static bool samd20_cmd_mbist(target *t) -{ - ADIv5_AP_t *ap = adiv5_target_ap(t); - - /* Write the memory parameters to the DSU */ - adiv5_ap_mem_write(ap, SAMD20_DSU_ADDRESS, 0); - adiv5_ap_mem_write(ap, SAMD20_DSU_LENGTH, samd20_flash_size(t)); - - /* Clear the fail bit */ - adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, SAMD20_STATUSA_FAIL); - - /* Write the MBIST command */ - adiv5_ap_mem_write(ap, SAMD20_DSU_CTRLSTAT, SAMD20_CTRL_MBIST); - - /* Poll for DSU Ready */ - uint32_t status; - while (((status = adiv5_ap_mem_read(ap, SAMD20_DSU_CTRLSTAT)) & - (SAMD20_STATUSA_DONE | SAMD20_STATUSA_PERR | SAMD20_STATUSA_FAIL)) == 0) - if(target_check_error(t)) - return false; - - /* Test the protection error bit in Status A */ - if (status & SAMD20_STATUSA_PERR) { - gdb_outf("MBIST not run due to protection error.\n"); - return true; - } - - /* Test the fail bit in Status A */ - if (status & SAMD20_STATUSA_FAIL) { - gdb_outf("MBIST Fail @ 0x%08x\n", - adiv5_ap_mem_read(ap, SAMD20_DSU_ADDRESS)); - } else { - gdb_outf("MBIST Passed!\n"); - } - - return true; -}