From 98faaceb709f8915031db63a0623a55e076d3503 Mon Sep 17 00:00:00 2001 From: Richard Meadows Date: Mon, 16 Jul 2018 20:05:56 +0000 Subject: [PATCH] [efm32] Add support for EFM32 devices with different DI and MSC layouts * DI layout is identified by attempting to read OUI from both layouts * MSC address is passed to flashstub in r3 Retested EZR32LG230 (EZR Leopard Gecko M3) Tested EFR32BG13P532F512GM32 (EFR Blue Gecko) Achieves aims of PR #264 (I think) Thanks to @dholth and @ryankurte for inspiration Fixes Issue #226 --- src/target/efm32.c | 745 ++++++++++++++++++++++++-------- src/target/flashstub/efm32.c | 32 +- src/target/flashstub/efm32.stub | 42 +- 3 files changed, 577 insertions(+), 242 deletions(-) diff --git a/src/target/efm32.c b/src/target/efm32.c index a67abed..615feaa 100644 --- a/src/target/efm32.c +++ b/src/target/efm32.c @@ -18,14 +18,15 @@ */ /* This file implements EFM32 target specific functions for - * detecting the device, providing the XML memory map and Flash memory + * detecting the device, providing the memory map and Flash memory * programming. * - * Both EFM32 (microcontroller only) and EZR32 (microcontroller+radio) - * devices should be supported through this driver. + * EFM32, EZR32 and EFR32 devices are all currently supported through + * this driver. * * Tested with: * * EZR32LG230 (EZR Leopard Gecko M3) + * * EFR32BG13P532F512GM32 (EFR Blue Gecko) * * */ @@ -54,10 +55,12 @@ static const uint16_t efm32_flash_write_stub[] = { static bool efm32_cmd_erase_all(target *t); static bool efm32_cmd_serial(target *t); +static bool efm32_cmd_efm_info(target *t); const struct command_s efm32_cmd_list[] = { {"erase_mass", (cmd_handler)efm32_cmd_erase_all, "Erase entire flash memory"}, {"serial", (cmd_handler)efm32_cmd_serial, "Prints unique number"}, + {"efm_info", (cmd_handler)efm32_cmd_efm_info, "Prints information about the device"}, {NULL, NULL, NULL} }; @@ -67,16 +70,13 @@ const struct command_s efm32_cmd_list[] = { /* Memory System Controller (MSC) Registers */ /* -------------------------------------------------------------------------- */ -#define EFM32_MSC 0x400c0000 -#define EFM32_MSC_WRITECTRL (EFM32_MSC+0x008) -#define EFM32_MSC_WRITECMD (EFM32_MSC+0x00c) -#define EFM32_MSC_ADDRB (EFM32_MSC+0x010) -#define EFM32_MSC_WDATA (EFM32_MSC+0x018) -#define EFM32_MSC_STATUS (EFM32_MSC+0x01c) -#define EFM32_MSC_LOCK (EFM32_MSC+0x03c) -#define EFM32_MSC_CMD (EFM32_MSC+0x040) -#define EFM32_MSC_TIMEBASE (EFM32_MSC+0x050) -#define EFM32_MSC_MASSLOCK (EFM32_MSC+0x054) +#define EFM32_MSC_WRITECTRL(msc) (msc+0x008) +#define EFM32_MSC_WRITECMD(msc) (msc+0x00c) +#define EFM32_MSC_ADDRB(msc) (msc+0x010) +#define EFM32_MSC_WDATA(msc) (msc+0x018) +#define EFM32_MSC_STATUS(msc) (msc+0x01c) +#define EFM32_MSC_LOCK(msc) (msc+(msc == 0x400e0000?0x40:0x3c)) +#define EFM32_MSC_MASSLOCK(msc) (msc+0x054) #define EFM32_MSC_LOCK_LOCKKEY 0x1b71 #define EFM32_MSC_MASSLOCK_LOCKKEY 0x631a @@ -100,135 +100,416 @@ const struct command_s efm32_cmd_list[] = { /* -------------------------------------------------------------------------- */ #define EFM32_INFO 0x0fe00000 -#define EFM32_USER_DATA (EFM32_INFO+0x0000) -#define EFM32_LOCK_BITS (EFM32_INFO+0x4000) -#define EFM32_DI (EFM32_INFO+0x8000) +#define EFM32_USER_DATA (EFM32_INFO+0x0000) +#define EFM32_LOCK_BITS (EFM32_INFO+0x4000) +#define EFM32_V1_DI (EFM32_INFO+0x8000) +#define EFM32_V2_DI (EFM32_INFO+0x81B0) /* -------------------------------------------------------------------------- */ -/* Device Information (DI) Area */ +/* Device Information (DI) Area - Version 1 V1 */ /* -------------------------------------------------------------------------- */ -#define EFM32_DI_CMU_LFRCOCTRL (EFM32_DI+0x020) -#define EFM32_DI_CMU_HFRCOCTRL (EFM32_DI+0x028) -#define EFM32_DI_CMU_AUXHFRCOCTRL (EFM32_DI+0x030) -#define EFM32_DI_ADC0_CAL (EFM32_DI+0x040) -#define EFM32_DI_ADC0_BIASPROG (EFM32_DI+0x048) -#define EFM32_DI_DAC0_CAL (EFM32_DI+0x050) -#define EFM32_DI_DAC0_BIASPROG (EFM32_DI+0x058) -#define EFM32_DI_ACMP0_CTRL (EFM32_DI+0x060) -#define EFM32_DI_ACMP1_CTRL (EFM32_DI+0x068) -#define EFM32_DI_CMU_LCDCTRL (EFM32_DI+0x078) -#define EFM32_DI_DAC0_OPACTRL (EFM32_DI+0x0A0) -#define EFM32_DI_DAC0_OPAOFFSET (EFM32_DI+0x0A8) -#define EFM32_DI_EMU_BUINACT (EFM32_DI+0x0B0) -#define EFM32_DI_EMU_BUACT (EFM32_DI+0x0B8) -#define EFM32_DI_EMU_BUBODBUVINCAL (EFM32_DI+0x0C0) -#define EFM32_DI_EMU_BUBODUNREGCAL (EFM32_DI+0x0C8) -#define EFM32_DI_MCM_REV_MIN (EFM32_DI+0x1AA) -#define EFM32_DI_MCM_REV_MAJ (EFM32_DI+0x1AB) -#define EFM32_DI_RADIO_REV_MIN (EFM32_DI+0x1AC) -#define EFM32_DI_RADIO_REV_MAJ (EFM32_DI+0x1AD) -#define EFM32_DI_RADIO_OPN (EFM32_DI+0x1AE) -#define EFM32_DI_DI_CRC (EFM32_DI+0x1B0) -#define EFM32_DI_CAL_TEMP_0 (EFM32_DI+0x1B2) -#define EFM32_DI_ADC0_CAL_1V25 (EFM32_DI+0x1B4) -#define EFM32_DI_ADC0_CAL_2V5 (EFM32_DI+0x1B6) -#define EFM32_DI_ADC0_CAL_VDD (EFM32_DI+0x1B8) -#define EFM32_DI_ADC0_CAL_5VDIFF (EFM32_DI+0x1BA) -#define EFM32_DI_ADC0_CAL_2XVDD (EFM32_DI+0x1BC) -#define EFM32_DI_ADC0_TEMP_0_READ_1V25 (EFM32_DI+0x1BE) -#define EFM32_DI_DAC0_CAL_1V25 (EFM32_DI+0x1C8) -#define EFM32_DI_DAC0_CAL_2V5 (EFM32_DI+0x1CC) -#define EFM32_DI_DAC0_CAL_VDD (EFM32_DI+0x1D0) -#define EFM32_DI_AUXHFRCO_CALIB_BAND_1 (EFM32_DI+0x1D4) -#define EFM32_DI_AUXHFRCO_CALIB_BAND_7 (EFM32_DI+0x1D5) -#define EFM32_DI_AUXHFRCO_CALIB_BAND_11 (EFM32_DI+0x1D6) -#define EFM32_DI_AUXHFRCO_CALIB_BAND_14 (EFM32_DI+0x1D7) -#define EFM32_DI_AUXHFRCO_CALIB_BAND_21 (EFM32_DI+0x1D8) -#define EFM32_DI_AUXHFRCO_CALIB_BAND_28 (EFM32_DI+0x1D9) -#define EFM32_DI_HFRCO_CALIB_BAND_1 (EFM32_DI+0x1DC) -#define EFM32_DI_HFRCO_CALIB_BAND_7 (EFM32_DI+0x1DD) -#define EFM32_DI_HFRCO_CALIB_BAND_11 (EFM32_DI+0x1DE) -#define EFM32_DI_HFRCO_CALIB_BAND_14 (EFM32_DI+0x1DF) -#define EFM32_DI_HFRCO_CALIB_BAND_21 (EFM32_DI+0x1E0) -#define EFM32_DI_HFRCO_CALIB_BAND_28 (EFM32_DI+0x1E1) -#define EFM32_DI_MEM_INFO_PAGE_SIZE (EFM32_DI+0x1E7) -#define EFM32_DI_RADIO_ID (EFM32_DI+0x1EE) -#define EFM32_DI_EUI64_0 (EFM32_DI+0x1F0) -#define EFM32_DI_EUI64_1 (EFM32_DI+0x1F4) -#define EFM32_DI_MEM_INFO_FLASH (EFM32_DI+0x1F8) -#define EFM32_DI_MEM_INFO_RAM (EFM32_DI+0x1FA) -#define EFM32_DI_PART_NUMBER (EFM32_DI+0x1FC) -#define EFM32_DI_PART_FAMILY (EFM32_DI+0x1FE) -#define EFM32_DI_PROD_REV (EFM32_DI+0x1FF) +#define EFM32_V1_DI_CMU_LFRCOCTRL (EFM32_V1_DI+0x020) +#define EFM32_V1_DI_CMU_HFRCOCTRL (EFM32_V1_DI+0x028) +#define EFM32_V1_DI_CMU_AUXHFRCOCTRL (EFM32_V1_DI+0x030) +#define EFM32_V1_DI_ADC0_CAL (EFM32_V1_DI+0x040) +#define EFM32_V1_DI_ADC0_BIASPROG (EFM32_V1_DI+0x048) +#define EFM32_V1_DI_DAC0_CAL (EFM32_V1_DI+0x050) +#define EFM32_V1_DI_DAC0_BIASPROG (EFM32_V1_DI+0x058) +#define EFM32_V1_DI_ACMP0_CTRL (EFM32_V1_DI+0x060) +#define EFM32_V1_DI_ACMP1_CTRL (EFM32_V1_DI+0x068) +#define EFM32_V1_DI_CMU_LCDCTRL (EFM32_V1_DI+0x078) +#define EFM32_V1_DI_DAC0_OPACTRL (EFM32_V1_DI+0x0A0) +#define EFM32_V1_DI_DAC0_OPAOFFSET (EFM32_V1_DI+0x0A8) +#define EFM32_V1_DI_EMU_BUINACT (EFM32_V1_DI+0x0B0) +#define EFM32_V1_DI_EMU_BUACT (EFM32_V1_DI+0x0B8) +#define EFM32_V1_DI_EMU_BUBODBUVINCAL (EFM32_V1_DI+0x0C0) +#define EFM32_V1_DI_EMU_BUBODUNREGCAL (EFM32_V1_DI+0x0C8) +#define EFM32_V1_DI_MCM_REV_MIN (EFM32_V1_DI+0x1AA) +#define EFM32_V1_DI_MCM_REV_MAJ (EFM32_V1_DI+0x1AB) +#define EFM32_V1_DI_RADIO_REV_MIN (EFM32_V1_DI+0x1AC) +#define EFM32_V1_DI_RADIO_REV_MAJ (EFM32_V1_DI+0x1AD) +#define EFM32_V1_DI_RADIO_OPN (EFM32_V1_DI+0x1AE) +#define EFM32_V1_DI_V1_DI_CRC (EFM32_V1_DI+0x1B0) +#define EFM32_V1_DI_CAL_TEMP_0 (EFM32_V1_DI+0x1B2) +#define EFM32_V1_DI_ADC0_CAL_1V25 (EFM32_V1_DI+0x1B4) +#define EFM32_V1_DI_ADC0_CAL_2V5 (EFM32_V1_DI+0x1B6) +#define EFM32_V1_DI_ADC0_CAL_VDD (EFM32_V1_DI+0x1B8) +#define EFM32_V1_DI_ADC0_CAL_5VDIFF (EFM32_V1_DI+0x1BA) +#define EFM32_V1_DI_ADC0_CAL_2XVDD (EFM32_V1_DI+0x1BC) +#define EFM32_V1_DI_ADC0_TEMP_0_READ_1V25 (EFM32_V1_DI+0x1BE) +#define EFM32_V1_DI_DAC0_CAL_1V25 (EFM32_V1_DI+0x1C8) +#define EFM32_V1_DI_DAC0_CAL_2V5 (EFM32_V1_DI+0x1CC) +#define EFM32_V1_DI_DAC0_CAL_VDD (EFM32_V1_DI+0x1D0) +#define EFM32_V1_DI_AUXHFRCO_CALIB_BAND_1 (EFM32_V1_DI+0x1D4) +#define EFM32_V1_DI_AUXHFRCO_CALIB_BAND_7 (EFM32_V1_DI+0x1D5) +#define EFM32_V1_DI_AUXHFRCO_CALIB_BAND_11 (EFM32_V1_DI+0x1D6) +#define EFM32_V1_DI_AUXHFRCO_CALIB_BAND_14 (EFM32_V1_DI+0x1D7) +#define EFM32_V1_DI_AUXHFRCO_CALIB_BAND_21 (EFM32_V1_DI+0x1D8) +#define EFM32_V1_DI_AUXHFRCO_CALIB_BAND_28 (EFM32_V1_DI+0x1D9) +#define EFM32_V1_DI_HFRCO_CALIB_BAND_1 (EFM32_V1_DI+0x1DC) +#define EFM32_V1_DI_HFRCO_CALIB_BAND_7 (EFM32_V1_DI+0x1DD) +#define EFM32_V1_DI_HFRCO_CALIB_BAND_11 (EFM32_V1_DI+0x1DE) +#define EFM32_V1_DI_HFRCO_CALIB_BAND_14 (EFM32_V1_DI+0x1DF) +#define EFM32_V1_DI_HFRCO_CALIB_BAND_21 (EFM32_V1_DI+0x1E0) +#define EFM32_V1_DI_HFRCO_CALIB_BAND_28 (EFM32_V1_DI+0x1E1) +#define EFM32_V1_DI_MEM_INFO_PAGE_SIZE (EFM32_V1_DI+0x1E7) +#define EFM32_V1_DI_RADIO_ID (EFM32_V1_DI+0x1EE) +#define EFM32_V1_DI_EUI64_0 (EFM32_V1_DI+0x1F0) +#define EFM32_V1_DI_EUI64_1 (EFM32_V1_DI+0x1F4) +#define EFM32_V1_DI_MEM_INFO_FLASH (EFM32_V1_DI+0x1F8) +#define EFM32_V1_DI_MEM_INFO_RAM (EFM32_V1_DI+0x1FA) +#define EFM32_V1_DI_PART_NUMBER (EFM32_V1_DI+0x1FC) +#define EFM32_V1_DI_PART_FAMILY (EFM32_V1_DI+0x1FE) +#define EFM32_V1_DI_PROD_REV (EFM32_V1_DI+0x1FF) /* top 24 bits of eui */ -#define EFM32_DI_EUI_SILABS 0x000b57 - -#define EFM32_DI_PART_FAMILY_GECKO 71 -#define EFM32_DI_PART_FAMILY_GIANT_GECKO 72 -#define EFM32_DI_PART_FAMILY_TINY_GECKO 73 -#define EFM32_DI_PART_FAMILY_LEOPARD_GECKO 74 -#define EFM32_DI_PART_FAMILY_WONDER_GECKO 75 -#define EFM32_DI_PART_FAMILY_ZERO_GECKO 76 -#define EFM32_DI_PART_FAMILY_HAPPY_GECKO 77 -#define EFM32_DI_PART_FAMILY_EZR_WONDER_GECKO 120 -#define EFM32_DI_PART_FAMILY_EZR_LEOPARD_GECKO 121 +#define EFM32_V1_DI_EUI_SILABS 0x000b57 /* -------------------------------------------------------------------------- */ -/* Helper functions */ +/* Device Information (DI) Area - Version 2 V2 */ +/* -------------------------------------------------------------------------- */ + +#define EFM32_V2_DI_CAL (EFM32_V2_DI+0x000) /* CRC of DI-page and calibration temperature */ +#define EFM32_V2_DI_EXTINFO (EFM32_V2_DI+0x020) /* External Component description */ +#define EFM32_V2_DI_EUI48L (EFM32_V2_DI+0x028) /* EUI48 OUI and Unique identifier */ +#define EFM32_V2_DI_EUI48H (EFM32_V2_DI+0x02C) /* OUI */ +#define EFM32_V2_DI_CUSTOMINFO (EFM32_V2_DI+0x030) /* Custom information */ +#define EFM32_V2_DI_MEMINFO (EFM32_V2_DI+0x034) /* Flash page size and misc. chip information */ +#define EFM32_V2_DI_UNIQUEL (EFM32_V2_DI+0x040) /* Low 32 bits of device unique number */ +#define EFM32_V2_DI_UNIQUEH (EFM32_V2_DI+0x044) /* High 32 bits of device unique number */ +#define EFM32_V2_DI_MSIZE (EFM32_V2_DI+0x048) /* Flash and SRAM Memory size in kB */ +#define EFM32_V2_DI_PART (EFM32_V2_DI+0x04C) /* Part description */ +#define EFM32_V2_DI_DEVINFOREV (EFM32_V2_DI+0x050) /* Device information page revision */ +#define EFM32_V2_DI_EMUTEMP (EFM32_V2_DI+0x054) /* EMU Temperature Calibration Information */ +#define EFM32_V2_DI_ADC0CAL0 (EFM32_V2_DI+0x060) /* ADC0 calibration register 0 */ +#define EFM32_V2_DI_ADC0CAL1 (EFM32_V2_DI+0x064) /* ADC0 calibration register 1 */ +#define EFM32_V2_DI_ADC0CAL2 (EFM32_V2_DI+0x068) /* ADC0 calibration register 2 */ +#define EFM32_V2_DI_ADC0CAL3 (EFM32_V2_DI+0x06C) /* ADC0 calibration register 3 */ +#define EFM32_V2_DI_HFRCOCAL0 (EFM32_V2_DI+0x080) /* HFRCO Calibration Register (4 MHz) */ +#define EFM32_V2_DI_HFRCOCAL3 (EFM32_V2_DI+0x08C) /* HFRCO Calibration Register (7 MHz) */ +#define EFM32_V2_DI_HFRCOCAL6 (EFM32_V2_DI+0x098) /* HFRCO Calibration Register (13 MHz) */ +#define EFM32_V2_DI_HFRCOCAL7 (EFM32_V2_DI+0x09C) /* HFRCO Calibration Register (16 MHz) */ +#define EFM32_V2_DI_HFRCOCAL8 (EFM32_V2_DI+0x0A0) +#define EFM32_V2_DI_HFRCOCAL10 (EFM32_V2_DI+0x0A8) +#define EFM32_V2_DI_HFRCOCAL11 (EFM32_V2_DI+0x0AC) +#define EFM32_V2_DI_HFRCOCAL12 (EFM32_V2_DI+0x0B0) +#define EFM32_V2_DI_AUXHFRCOCAL0 (EFM32_V2_DI+0x0E0) +#define EFM32_V2_DI_AUXHFRCOCAL3 (EFM32_V2_DI+0x0EC) +#define EFM32_V2_DI_AUXHFRCOCAL6 (EFM32_V2_DI+0x0F8) +#define EFM32_V2_DI_AUXHFRCOCAL7 (EFM32_V2_DI+0x0FC) +#define EFM32_V2_DI_AUXHFRCOCAL8 (EFM32_V2_DI+0x100) +#define EFM32_V2_DI_AUXHFRCOCAL10 (EFM32_V2_DI+0x108) +#define EFM32_V2_DI_AUXHFRCOCAL11 (EFM32_V2_DI+0x10C) +#define EFM32_V2_DI_AUXHFRCOCAL12 (EFM32_V2_DI+0x110) +#define EFM32_V2_DI_VMONCAL0 (EFM32_V2_DI+0x140) +#define EFM32_V2_DI_VMONCAL1 (EFM32_V2_DI+0x144) /* VMON Calibration Register 1 */ +#define EFM32_V2_DI_VMONCAL2 (EFM32_V2_DI+0x148) /* VMON Calibration Register 2 */ +#define EFM32_V2_DI_IDAC0CAL0 (EFM32_V2_DI+0x158) /* IDAC0 Calibration Register 0 */ +#define EFM32_V2_DI_IDAC0CAL1 (EFM32_V2_DI+0x15C) /* IDAC0 Calibration Register 1 */ +#define EFM32_V2_DI_DCDCLNVCTRL0 (EFM32_V2_DI+0x168) /* DCDC Low-noise VREF Trim Register 0 */ +#define EFM32_V2_DI_DCDCLPVCTRL0 (EFM32_V2_DI+0x16C) /* DCDC Low-power VREF Trim Register 0 */ +#define EFM32_V2_DI_DCDCLPVCTRL1 (EFM32_V2_DI+0x170) /* DCDC Low-power VREF Trim Register 1 */ +#define EFM32_V2_DI_DCDCLPVCTRL2 (EFM32_V2_DI+0x174) /* DCDC Low-power VREF Trim Register 2 */ +#define EFM32_V2_DI_DCDCLPVCTRL3 (EFM32_V2_DI+0x178) /* DCDC Low-power VREF Trim Register 3 */ +#define EFM32_V2_DI_DCDCLPCMPHYSSEL0 (EFM32_V2_DI+0x17C) /* DCDC LPCMPHYSSEL Trim Register 0 */ +#define EFM32_V2_DI_DCDCLPCMPHYSSEL1 (EFM32_V2_DI+0x180) /* DCDC LPCMPHYSSEL Trim Register 1 */ +#define EFM32_V2_DI_VDAC0MAINCAL (EFM32_V2_DI+0x184) /* VDAC0 Cals for Main Path */ +#define EFM32_V2_DI_VDAC0ALTCAL (EFM32_V2_DI+0x188) /* VDAC0 Cals for Alternate Path */ +#define EFM32_V2_DI_VDAC0CH1CAL (EFM32_V2_DI+0x18C) /* VDAC0 CH1 Error Cal */ +#define EFM32_V2_DI_OPA0CAL0 (EFM32_V2_DI+0x190) /* OPA0 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ +#define EFM32_V2_DI_OPA0CAL1 (EFM32_V2_DI+0x194) /* OPA0 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ +#define EFM32_V2_DI_OPA0CAL2 (EFM32_V2_DI+0x198) /* OPA0 Calibration Register for DRIVESTRENGTH 2, INCBW=1 */ +#define EFM32_V2_DI_OPA0CAL3 (EFM32_V2_DI+0x19C) /* OPA0 Calibration Register for DRIVESTRENGTH 3, INCBW=1 */ +#define EFM32_V2_DI_OPA1CAL0 (EFM32_V2_DI+0x1A0) /* OPA1 Calibration Register for DRIVESTRENGTH 0, INCBW=1 */ +#define EFM32_V2_DI_OPA1CAL1 (EFM32_V2_DI+0x1A4) /* OPA1 Calibration Register for DRIVESTRENGTH 1, INCBW=1 */ +#define EFM32_V2_DI_OPA1CAL2 (EFM32_V2_DI+0x1A8) +#define EFM32_V2_DI_OPA1CAL3 (EFM32_V2_DI+0x1AC) +#define EFM32_V2_DI_OPA2CAL0 (EFM32_V2_DI+0x1B0) +#define EFM32_V2_DI_OPA2CAL1 (EFM32_V2_DI+0x1B4) +#define EFM32_V2_DI_OPA2CAL2 (EFM32_V2_DI+0x1B8) +#define EFM32_V2_DI_OPA2CAL3 (EFM32_V2_DI+0x1BC) +#define EFM32_V2_DI_CSENGAINCAL (EFM32_V2_DI+0x1C0) +#define EFM32_V2_DI_OPA0CAL4 (EFM32_V2_DI+0x1D0) +#define EFM32_V2_DI_OPA0CAL5 (EFM32_V2_DI+0x1D4) +#define EFM32_V2_DI_OPA0CAL6 (EFM32_V2_DI+0x1D8) +#define EFM32_V2_DI_OPA0CAL7 (EFM32_V2_DI+0x1DC) +#define EFM32_V2_DI_OPA1CAL4 (EFM32_V2_DI+0x1E0) +#define EFM32_V2_DI_OPA1CAL5 (EFM32_V2_DI+0x1E4) +#define EFM32_V2_DI_OPA1CAL6 (EFM32_V2_DI+0x1E8) +#define EFM32_V2_DI_OPA1CAL7 (EFM32_V2_DI+0x1EC) +#define EFM32_V2_DI_OPA2CAL4 (EFM32_V2_DI+0x1F0) +#define EFM32_V2_DI_OPA2CAL5 (EFM32_V2_DI+0x1F4) +#define EFM32_V2_DI_OPA2CAL6 (EFM32_V2_DI+0x1F8) /* OPA2 Calibration Register for DRIVESTRENGTH 2, INCBW=0 */ +#define EFM32_V2_DI_OPA2CAL7 (EFM32_V2_DI+0x1FC) /* OPA2 Calibration Register for DRIVESTRENGTH 3, INCBW=0 */ + +/* top 24 bits of eui */ +#define EFM32_V2_DI_EUI_ENERGYMICRO 0xd0cf5e + +/* -------------------------------------------------------------------------- */ +/* Constants */ +/* -------------------------------------------------------------------------- */ + +typedef struct efm32_device_t { + uint16_t family_id; /* Family for device matching */ + char* name; /* Friendly device family name */ + uint32_t flash_page_size; /* Flash page size */ + uint32_t msc_addr; /* MSC Address */ + bool has_radio; /* Indicates a device has attached radio */ + char* description; /* Human-readable description */ +} efm32_device_t; + +efm32_device_t const efm32_devices[] = { + /* First gen micros */ + {71, "EFM32G", 512, 0x400c0000, false, "Gecko"}, + {72, "EFM32GG", 2048, 0x400c0000, false, "Giant Gecko"}, + {73, "EFM32TG", 512, 0x400c0000, false, "Tiny Gecko"}, + {74, "EFM32LG", 2048, 0x400c0000, false, "Leopard Gecko"}, + {75, "EFM32WG", 2048, 0x400c0000, false, "Wonder Gecko"}, + {76, "EFM32ZG", 1024, 0x400c0000, false, "Zero Gecko"}, + {77, "EFM32HG", 1024, 0x400c0000, false, "Happy Gecko"}, + /* First (1.5) gen micro + radio */ + {120, "EZR32WG", 2048, 0x400c0000, true, "EZR Wonder Gecko"}, + {121, "EZR32LG", 2048, 0x400c0000, true, "EZR Leopard Gecko"}, + {122, "EZR32HG", 2048, 0x400c0000, true, "EZR Happy Gecko"}, + /* Second gen micros */ + {81, "EFM32PG1B", 2048, 0x400e0000, false, "Pearl Gecko"}, + {83, "EFM32JG1B", 2048, 0x400e0000, false, "Jade Gecko"}, + /* Second gen devices micro + radio */ + {16, "EFR32MG1P", 2048, 0x400e0000, true, "Mighty Gecko"}, + {17, "EFR32MG1B", 2048, 0x400e0000, true, "Mighty Gecko"}, + {18, "EFR32MG1V", 2048, 0x400e0000, true, "Mighty Gecko"}, + {19, "EFR32BG1P", 2048, 0x400e0000, true, "Blue Gecko"}, + {20, "EFR32BG1B", 2048, 0x400e0000, true, "Blue Gecko"}, + {21, "EFR32BG1V", 2048, 0x400e0000, true, "Blue Gecko"}, + {25, "EFR32FG1P", 2048, 0x400e0000, true, "Flex Gecko"}, + {26, "EFR32FG1B", 2048, 0x400e0000, true, "Flex Gecko"}, + {27, "EFR32FG1V", 2048, 0x400e0000, true, "Flex Gecko"}, + {28, "EFR32MG12P", 2048, 0x400e0000, true, "Mighty Gecko"}, + {29, "EFR32MG12B", 2048, 0x400e0000, true, "Mighty Gecko"}, + {30, "EFR32MG12V", 2048, 0x400e0000, true, "Mighty Gecko"}, + {31, "EFR32BG12P", 2048, 0x400e0000, true, "Blue Gecko"}, + {32, "EFR32BG12B", 2048, 0x400e0000, true, "Blue Gecko"}, + {33, "EFR32BG12V", 2048, 0x400e0000, true, "Blue Gecko"}, + {37, "EFR32FG12P", 2048, 0x400e0000, true, "Flex Gecko"}, + {38, "EFR32FG12B", 2048, 0x400e0000, true, "Flex Gecko"}, + {39, "EFR32FG12V", 2048, 0x400e0000, true, "Flex Gecko"}, + {40, "EFR32MG13P", 2048, 0x400e0000, true, "Mighty Gecko"}, + {41, "EFR32MG13B", 2048, 0x400e0000, true, "Mighty Gecko"}, + {42, "EFR32MG13V", 2048, 0x400e0000, true, "Mighty Gecko"}, + {43, "EFR32BG13P", 2048, 0x400e0000, true, "Blue Gecko"}, + {44, "EFR32BG13B", 2048, 0x400e0000, true, "Blue Gecko"}, + {45, "EFR32BG13V", 2048, 0x400e0000, true, "Blue Gecko"}, + {49, "EFR32FG13P", 2048, 0x400e0000, true, "Flex Gecko"}, + {50, "EFR32FG13B", 2048, 0x400e0000, true, "Flex Gecko"}, + {51, "EFR32FG13V", 2048, 0x400e0000, true, "Flex Gecko"}, + {52, "EFR32MG14P", 2048, 0x400e0000, true, "Mighty Gecko"}, + {53, "EFR32MG14B", 2048, 0x400e0000, true, "Mighty Gecko"}, + {54, "EFR32MG14V", 2048, 0x400e0000, true, "Mighty Gecko"}, + {55, "EFR32BG14P", 2048, 0x400e0000, true, "Blue Gecko"}, + {56, "EFR32BG14B", 2048, 0x400e0000, true, "Blue Gecko"}, + {57, "EFR32BG14V", 2048, 0x400e0000, true, "Blue Gecko"}, + {61, "EFR32FG14P", 2048, 0x400e0000, true, "Flex Gecko"}, + {62, "EFR32FG14B", 2048, 0x400e0000, true, "Flex Gecko"}, + {63, "EFR32FG14V", 2048, 0x400e0000, true, "Flex Gecko"}, +}; + + +/* miscchip */ +typedef struct efm32_v2_di_miscchip_t { + uint8_t pincount; + uint8_t pkgtype; + uint8_t tempgrade; +} efm32_v2_di_miscchip_t; + +/* pkgtype */ +typedef struct efm32_v2_di_pkgtype_t { + uint8_t pkgtype; + char* name; +} efm32_v2_di_pkgtype_t; + +efm32_v2_di_pkgtype_t const efm32_v2_di_pkgtypes[] = { + {74, "WLCSP"}, /* WLCSP package */ + {76, "BGA"}, /* BGA package */ + {77, "QFN"}, /* QFN package */ + {81, "QFxP"}, /* QFP package */ +}; + +/* tempgrade */ +typedef struct efm32_v2_di_tempgrade_t { + uint8_t tempgrade; + char* name; +} efm32_v2_di_tempgrade_t; + +efm32_v2_di_tempgrade_t const efm32_v2_di_tempgrades[] = { + {0, "-40 to 85degC"}, + {1, "-40 to 125degC"}, + {2, "-40 to 105degC"}, + {3, "0 to 70degC"} +}; + +/* -------------------------------------------------------------------------- */ +/* Helper functions - Version 1 V1 */ /* -------------------------------------------------------------------------- */ /** - * Reads the EFM32 Extended Unique Identifier + * Reads the EFM32 Extended Unique Identifier EUI64 (V1) */ - uint64_t efm32_read_eui(target *t) - { - uint64_t eui; +uint64_t efm32_v1_read_eui64(target *t) +{ + uint64_t eui; - eui = (uint64_t)target_mem_read32(t, EFM32_DI_EUI64_1) << 32; - eui |= (uint64_t)target_mem_read32(t, EFM32_DI_EUI64_0) << 0; + eui = (uint64_t)target_mem_read32(t, EFM32_V1_DI_EUI64_1) << 32; + eui |= (uint64_t)target_mem_read32(t, EFM32_V1_DI_EUI64_0) << 0; - return eui; + return eui; +} +/** + * Reads the EFM32 Extended Unique Identifier EUI48 (V2) + */ +uint64_t efm32_v2_read_eui48(target *t) +{ + uint64_t eui; + + eui = (uint64_t)target_mem_read32(t, EFM32_V2_DI_EUI48H) << 32; + eui |= (uint64_t)target_mem_read32(t, EFM32_V2_DI_EUI48L) << 0; + + return eui; +} +/** + * Reads the Unique Number (DI V2 only) + */ +uint64_t efm32_v2_read_unique(target *t, uint8_t di_version) +{ + uint64_t unique; + switch (di_version) { + case 2: + unique = (uint64_t)target_mem_read32(t, EFM32_V2_DI_UNIQUEH) << 32; + unique |= (uint64_t)target_mem_read32(t, EFM32_V2_DI_UNIQUEL) << 0; + return unique; + default: + return 0; } +} + /** * Reads the EFM32 flash size in kiB */ -uint16_t efm32_read_flash_size(target *t) +uint16_t efm32_read_flash_size(target *t, uint8_t di_version) { - return target_mem_read16(t, EFM32_DI_MEM_INFO_FLASH); + switch (di_version) { + case 1: + return target_mem_read16(t, EFM32_V1_DI_MEM_INFO_FLASH); + case 2: + return (target_mem_read32(t, EFM32_V2_DI_MSIZE) >> 0) & 0xFFFF; + default: + return 0; + } } /** * Reads the EFM32 RAM size in kiB */ -uint16_t efm32_read_ram_size(target *t) +uint16_t efm32_read_ram_size(target *t, uint8_t di_version) { - return target_mem_read16(t, EFM32_DI_MEM_INFO_RAM); + switch (di_version) { + case 1: + return target_mem_read16(t, EFM32_V1_DI_MEM_INFO_RAM); + case 2: + return (target_mem_read32(t, EFM32_V2_DI_MSIZE) >> 16) & 0xFFFF; + default: + return 0; + } } +/** + * Reads the EFM32 reported flash page size in bytes. Note: This + * driver ignores this value, and uses a conservative hard-coded + * value. There are errata on the value reported by the EFM32 + * eg. DI_101 + */ +uint32_t efm32_flash_page_size(target *t, uint8_t di_version) +{ + uint8_t mem_info_page_size; + + switch (di_version) { + case 1: + mem_info_page_size = target_mem_read8(t, EFM32_V1_DI_MEM_INFO_PAGE_SIZE); + break; + case 2: + mem_info_page_size = (target_mem_read32(t, EFM32_V2_DI_MEMINFO) >> 24) & 0xFF; + break; + default: + return 0; + } + + return (1 << (mem_info_page_size + 10)); /* uint8_t ovf here */ +} + + /** * Reads the EFM32 Part Number */ -uint16_t efm32_read_part_number(target *t) +uint16_t efm32_read_part_number(target *t, uint8_t di_version) { - return target_mem_read16(t, EFM32_DI_PART_NUMBER); + switch (di_version) { + case 1: + return target_mem_read8(t, EFM32_V1_DI_PART_NUMBER); + case 2: + return target_mem_read32(t, EFM32_V2_DI_PART) & 0xFFFF; + default: + return 0; + } } /** * Reads the EFM32 Part Family */ -uint8_t efm32_read_part_family(target *t) +uint8_t efm32_read_part_family(target *t, uint8_t di_version) { - return target_mem_read8(t, EFM32_DI_PART_FAMILY); + switch (di_version) { + case 1: + return target_mem_read8(t, EFM32_V1_DI_PART_FAMILY); + case 2: + return (target_mem_read32(t, EFM32_V2_DI_PART) >> 16) & 0xFF; + default: + return 0; + } } /** - * Reads the EFM32 Radio part number (EZR parts only) + * Reads the EFM32 Radio part number (EZR parts with V1 DI only) */ -uint16_t efm32_read_radio_part_number(target *t) +uint16_t efm32_read_radio_part_number(target *t, uint8_t di_version) { - return target_mem_read16(t, EFM32_DI_RADIO_OPN); + switch (di_version) { + case 1: + return target_mem_read16(t, EFM32_V1_DI_RADIO_OPN); + default: + return 0; + } } +/** + * Reads the EFM32 Misc. Chip definitions + */ +efm32_v2_di_miscchip_t efm32_v2_read_miscchip(target *t, uint8_t di_version) +{ + uint32_t meminfo; + efm32_v2_di_miscchip_t miscchip; + memset(&miscchip, 0, sizeof(efm32_v2_di_miscchip_t) / sizeof(char)); + switch (di_version) { + case 2: + meminfo = target_mem_read32(t, EFM32_V2_DI_MEMINFO); + miscchip.pincount = (meminfo >> 16) & 0xFF; + miscchip.pkgtype = (meminfo >> 8) & 0xFF; + miscchip.tempgrade = (meminfo >> 0) & 0xFF; + } + + return miscchip; +} + +/* -------------------------------------------------------------------------- */ +/* Shared Functions */ +/* -------------------------------------------------------------------------- */ static void efm32_add_flash(target *t, target_addr addr, size_t length, @@ -244,9 +525,38 @@ static void efm32_add_flash(target *t, target_addr addr, size_t length, target_add_flash(t, f); } -char variant_string[40]; +/** + * Lookup device + */ +size_t efm32_lookup_device_index(target *t, uint8_t di_version) +{ + uint8_t part_family = efm32_read_part_family(t, di_version); + + /* Search for family */ + for (size_t i = 0; i < (sizeof(efm32_devices) / sizeof(efm32_device_t)); i++) { + if (efm32_devices[i].family_id == part_family) { + return i; + } + } + /* Unknown family */ + return 9999; +} +efm32_device_t const * efm32_get_device(size_t index) +{ + if (index >= (sizeof(efm32_devices) / sizeof(efm32_device_t))) { + return NULL; + } + return &efm32_devices[index]; +} + +/** + * Probe + */ +char variant_string[60]; bool efm32_probe(target *t) { + uint8_t di_version = 1; + /* Read the IDCODE register from the SW-DP */ ADIv5_AP_t *ap = cortexm_ap(t); uint32_t ap_idcode = ap->dp->idcode; @@ -260,79 +570,43 @@ bool efm32_probe(target *t) return false; } + /* Check the EUI is silabs. Identify the Device Identification (DI) version */ + if (((efm32_v1_read_eui64(t) >> 40) & 0xFFFFFF) == EFM32_V1_DI_EUI_SILABS) { + /* Device Identification (DI) version 1 */ + di_version = 1; + } else if (((efm32_v2_read_eui48(t) >> 24) & 0xFFFFFF) == EFM32_V2_DI_EUI_ENERGYMICRO) { + /* Device Identification (DI) version 2 */ + di_version = 2; + } else { + /* unknown device */ + /* sprintf(variant_string, */ + /* "EFM32 DI Version ?? 0x%016llx 0x%016llx", */ + /* efm32_v1_read_eui64(t), efm32_v2_read_eui48(t)); */ + return false; + } + /* Read the part number and family */ - uint16_t part_number = efm32_read_part_number(t); - uint8_t part_family = efm32_read_part_family(t); - uint16_t radio_number, radio_number_short; /* optional, for ezr parts */ - uint32_t flash_page_size; uint16_t flash_kb; - - switch(part_family) { - case EFM32_DI_PART_FAMILY_GECKO: - sprintf(variant_string, - "EFM32 Gecko"); - flash_page_size = 512; - break; - case EFM32_DI_PART_FAMILY_GIANT_GECKO: - sprintf(variant_string, - "EFM32 Giant Gecko"); - flash_page_size = 2048; /* Could be 2048 or 4096, assume 2048 */ - break; - case EFM32_DI_PART_FAMILY_TINY_GECKO: - sprintf(variant_string, - "EFM32 Tiny Gecko"); - flash_page_size = 512; - break; - case EFM32_DI_PART_FAMILY_LEOPARD_GECKO: - sprintf(variant_string, - "EFM32 Leopard Gecko"); - flash_page_size = 2048; /* Could be 2048 or 4096, assume 2048 */ - break; - case EFM32_DI_PART_FAMILY_WONDER_GECKO: - sprintf(variant_string, - "EFM32 Wonder Gecko"); - flash_page_size = 2048; - break; - case EFM32_DI_PART_FAMILY_ZERO_GECKO: - sprintf(variant_string, - "EFM32 Zero Gecko"); - flash_page_size = 1024; - break; - case EFM32_DI_PART_FAMILY_HAPPY_GECKO: - sprintf(variant_string, - "EFM32 Happy Gecko"); - flash_page_size = 1024; - break; - case EFM32_DI_PART_FAMILY_EZR_WONDER_GECKO: - radio_number = efm32_read_radio_part_number(t); /* on-chip radio */ - radio_number_short = radio_number % 100; - flash_kb = efm32_read_flash_size(t); - - sprintf(variant_string, - "EZR32WG%dF%dR%d (radio si%d)", - part_number, flash_kb, - radio_number_short, radio_number); - - flash_page_size = 2048; - break; - case EFM32_DI_PART_FAMILY_EZR_LEOPARD_GECKO: - radio_number = efm32_read_radio_part_number(t); /* on-chip radio */ - radio_number_short = radio_number % 100; - flash_kb = efm32_read_flash_size(t); - - sprintf(variant_string, - "EZR32LG%dF%dR%d (radio si%d)", - part_number, flash_kb, - radio_number_short, radio_number); - - flash_page_size = 2048; - break; - default: /* Unknown family */ - return false; + uint16_t part_number = efm32_read_part_number(t, di_version); + size_t device_index = efm32_lookup_device_index(t, di_version); + if (device_index > (127-32)) { + /* too big to encode in printable ascii */ + return false; + } + efm32_device_t const* device = &efm32_devices[device_index]; + if (device == NULL) { + return false; } /* Read memory sizes, convert to bytes */ - uint32_t flash_size = efm32_read_flash_size(t) * 0x400; - uint32_t ram_size = efm32_read_ram_size(t) * 0x400; + uint16_t flash_kib = efm32_read_flash_size(t, di_version); + uint32_t flash_size = flash_kib * 0x400; + uint16_t ram_kib = efm32_read_ram_size(t, di_version); + uint32_t ram_size = ram_kib * 0x400; + uint32_t flash_page_size = device->flash_page_size; + + sprintf(variant_string, "%c\b%c\b%s %d F%d %s", + di_version + 48, device_index + 32, + device->name, part_number, flash_kib, device->description); /* Setup Target */ t->target_options |= CORTEXM_TOPT_INHIBIT_SRST; @@ -351,20 +625,28 @@ bool efm32_probe(target *t) static int efm32_flash_erase(struct target_flash *f, target_addr addr, size_t len) { target *t = f->t; + efm32_device_t const* device = efm32_get_device(t->driver[2] - 32); + if (device == NULL) { + return true; + } + uint32_t msc = device->msc_addr; + + /* Unlock */ + target_mem_write32(t, EFM32_MSC_LOCK(msc), EFM32_MSC_LOCK_LOCKKEY); /* Set WREN bit to enabel MSC write and erase functionality */ - target_mem_write32(t, EFM32_MSC_WRITECTRL, 1); + target_mem_write32(t, EFM32_MSC_WRITECTRL(msc), 1); while (len) { /* Write address of first word in row to erase it */ - target_mem_write32(t, EFM32_MSC_ADDRB, addr); - target_mem_write32(t, EFM32_MSC_WRITECMD, EFM32_MSC_WRITECMD_LADDRIM); + target_mem_write32(t, EFM32_MSC_ADDRB(msc), addr); + target_mem_write32(t, EFM32_MSC_WRITECMD(msc), EFM32_MSC_WRITECMD_LADDRIM); /* Issue the erase command */ - target_mem_write32(t, EFM32_MSC_WRITECMD, EFM32_MSC_WRITECMD_ERASEPAGE ); + target_mem_write32(t, EFM32_MSC_WRITECMD(msc), EFM32_MSC_WRITECMD_ERASEPAGE ); /* Poll MSC Busy */ - while ((target_mem_read32(t, EFM32_MSC_STATUS) & EFM32_MSC_STATUS_BUSY)) { + while ((target_mem_read32(t, EFM32_MSC_STATUS(msc)) & EFM32_MSC_STATUS_BUSY)) { if (target_check_error(t)) return -1; } @@ -384,6 +666,10 @@ static int efm32_flash_write(struct target_flash *f, { (void)len; target *t = f->t; + efm32_device_t const* device = efm32_get_device(t->driver[2] - 32); + if (device == NULL) { + return true; + } /* Write flashloader */ target_mem_write(t, SRAM_BASE, efm32_flash_write_stub, @@ -391,7 +677,7 @@ static int efm32_flash_write(struct target_flash *f, /* Write Buffer */ target_mem_write(t, STUB_BUFFER_BASE, src, len); /* Run flashloader */ - return cortexm_run_stub(t, SRAM_BASE, dest, STUB_BUFFER_BASE, len, 0); + return cortexm_run_stub(t, SRAM_BASE, dest, STUB_BUFFER_BASE, len, device->msc_addr); return 0; } @@ -401,23 +687,29 @@ static int efm32_flash_write(struct target_flash *f, */ static bool efm32_cmd_erase_all(target *t) { + efm32_device_t const* device = efm32_get_device(t->driver[2] - 32); + if (device == NULL) { + return true; + } + uint32_t msc = device->msc_addr; + /* Set WREN bit to enabel MSC write and erase functionality */ - target_mem_write32(t, EFM32_MSC_WRITECTRL, 1); + target_mem_write32(t, EFM32_MSC_WRITECTRL(msc), 1); /* Unlock mass erase */ - target_mem_write32(t, EFM32_MSC_MASSLOCK, EFM32_MSC_MASSLOCK_LOCKKEY); + target_mem_write32(t, EFM32_MSC_MASSLOCK(msc), EFM32_MSC_MASSLOCK_LOCKKEY); /* Erase operation */ - target_mem_write32(t, EFM32_MSC_WRITECMD, EFM32_MSC_WRITECMD_ERASEMAIN0); + target_mem_write32(t, EFM32_MSC_WRITECMD(msc), EFM32_MSC_WRITECMD_ERASEMAIN0); /* Poll MSC Busy */ - while ((target_mem_read32(t, EFM32_MSC_STATUS) & EFM32_MSC_STATUS_BUSY)) { + while ((target_mem_read32(t, EFM32_MSC_STATUS(msc)) & EFM32_MSC_STATUS_BUSY)) { if (target_check_error(t)) return false; } /* Relock mass erase */ - target_mem_write32(t, EFM32_MSC_MASSLOCK, 0); + target_mem_write32(t, EFM32_MSC_MASSLOCK(msc), 0); tc_printf(t, "Erase successful!\n"); @@ -429,11 +721,94 @@ static bool efm32_cmd_erase_all(target *t) */ static bool efm32_cmd_serial(target *t) { - /* Read the extended unique identifier */ - uint64_t eui = efm32_read_eui(t); + uint64_t unique = 0; + uint8_t di_version = t->driver[0] - 48; /* di version hidden in driver str */ - /* 64 bits of unique number */ - tc_printf(t, "Unique Number: 0x%016llx\n", eui); + switch (di_version) { + case 1: + /* Read the eui */ + unique = efm32_v1_read_eui64(t); + break; + case 2: + /* Read unique number */ + unique = efm32_v2_read_unique(t, di_version); + break; + } + + tc_printf(t, "Unique Number: 0x%016llx\n", unique); + + return true; +} +/** + * Prints various information we know about the device + */ +static bool efm32_cmd_efm_info(target *t) +{ + uint8_t di_version = t->driver[0] - 48; /* hidden in driver str */ + + switch (di_version) { + case 1: + tc_printf(t, "DI version 1 (silabs remix?) base 0x%08x\n\n", EFM32_V1_DI); + break; + case 2: + tc_printf(t, "DI version 2 (energy micro remix?) base 0x%08x\n\n", EFM32_V2_DI); + break; + default: + tc_printf(t, "Bad DI version %d! This driver doesn't know about this DI version\n", di_version); + return true; /* finish */ + } + + /* lookup device and part number */ + efm32_device_t const* device = efm32_get_device(t->driver[2] - 32); + if (device == NULL) { + return true; + } + uint16_t part_number = efm32_read_part_number(t, di_version); + + /* Read memory sizes, convert to bytes */ + uint16_t flash_kib = efm32_read_flash_size(t, di_version); + uint16_t ram_kib = efm32_read_ram_size(t, di_version); + uint32_t flash_page_size_reported = efm32_flash_page_size(t, di_version); + uint32_t flash_page_size = device->flash_page_size; + + tc_printf(t, "%s %d F%d = %s %dkiB flash, %dkiB ram\n", + device->name, part_number, flash_kib, + device->description, flash_kib, ram_kib); + tc_printf(t, "Device says flash page size is %d bytes, we're using %d bytes\n", + flash_page_size_reported, flash_page_size); + if (flash_page_size_reported < flash_page_size) { + tc_printf(t, "This is bad, flash writes may be corrupted\n"); + } + tc_printf(t, "\n"); + + if (di_version == 2) { + efm32_v2_di_miscchip_t miscchip = efm32_v2_read_miscchip(t, di_version); + efm32_v2_di_pkgtype_t const* pkgtype; + efm32_v2_di_tempgrade_t const* tempgrade; + + for (size_t i = 0; i < (sizeof(efm32_v2_di_pkgtypes) / + sizeof(efm32_v2_di_pkgtype_t)); i++) { + if (efm32_v2_di_pkgtypes[i].pkgtype == miscchip.pkgtype) { + pkgtype = &efm32_v2_di_pkgtypes[i]; + } + } + for (size_t i = 0; i < (sizeof(efm32_v2_di_tempgrades) / + sizeof(efm32_v2_di_tempgrade_t)); i++) { + if (efm32_v2_di_tempgrades[i].tempgrade == miscchip.tempgrade) { + tempgrade = &efm32_v2_di_tempgrades[i]; + } + } + + tc_printf(t, "Package %s %d pins\n", pkgtype->name, miscchip.pincount); + tc_printf(t, "Temperature grade %s\n", tempgrade->name); + tc_printf(t, "\n"); + } + + if (di_version == 1 && device->has_radio) { + uint16_t radio_number = efm32_read_radio_part_number(t, di_version); /* on-chip radio */ + tc_printf(t, "Radio si%d\n", radio_number); + tc_printf(t, "\n"); + } return true; } diff --git a/src/target/flashstub/efm32.c b/src/target/flashstub/efm32.c index 26f19a3..b38aded 100644 --- a/src/target/flashstub/efm32.c +++ b/src/target/flashstub/efm32.c @@ -19,13 +19,13 @@ #include #include "stub.h" -#define EFM32_MSC ((volatile uint32_t *)0x400c0000) -#define EFM32_MSC_WRITECTRL EFM32_MSC[2] -#define EFM32_MSC_WRITECMD EFM32_MSC[3] -#define EFM32_MSC_ADDRB EFM32_MSC[4] -#define EFM32_MSC_WDATA EFM32_MSC[6] -#define EFM32_MSC_STATUS EFM32_MSC[7] -#define EFM32_MSC_LOCK EFM32_MSC[15] +#define EFM32_MSC_WRITECTRL(msc) *((volatile uint32_t *)(msc+0x008)) +#define EFM32_MSC_WRITECMD(msc) *((volatile uint32_t *)(msc+0x00c)) +#define EFM32_MSC_ADDRB(msc) *((volatile uint32_t *)(msc+0x010)) +#define EFM32_MSC_WDATA(msc) *((volatile uint32_t *)(msc+0x018)) +#define EFM32_MSC_STATUS(msc) *((volatile uint32_t *)(msc+0x01c)) +#define EFM32_MSC_LOCK(msc) *((volatile uint32_t *)(msc+(msc == 0x400e0000?0x40:0x3c))) +#define EFM32_MSC_MASSLOCK(msc) *((volatile uint32_t *)(msc+0x054)) #define EFM32_MSC_LOCK_LOCKKEY 0x1b71 @@ -43,25 +43,25 @@ #define EFM32_MSC_STATUS_WORDTIMEOUT (1<<4) void __attribute__((naked)) -efm32_flash_write_stub(uint32_t *dest, uint32_t *src, uint32_t size) +efm32_flash_write_stub(uint32_t *dest, uint32_t *src, uint32_t size, uint32_t msc) { uint32_t i; - EFM32_MSC_LOCK = EFM32_MSC_LOCK_LOCKKEY; - EFM32_MSC_WRITECTRL = 1; + EFM32_MSC_LOCK(msc) = EFM32_MSC_LOCK_LOCKKEY; + EFM32_MSC_WRITECTRL(msc) = 1; for (i = 0; i < size/4; i++) { - EFM32_MSC_ADDRB = (uint32_t)&dest[i];; - EFM32_MSC_WRITECMD = EFM32_MSC_WRITECMD_LADDRIM; + EFM32_MSC_ADDRB(msc) = (uint32_t)&dest[i]; + EFM32_MSC_WRITECMD(msc) = EFM32_MSC_WRITECMD_LADDRIM; /* Wait for WDATAREADY */ - while ((EFM32_MSC_STATUS & EFM32_MSC_STATUS_WDATAREADY) == 0); + while ((EFM32_MSC_STATUS(msc) & EFM32_MSC_STATUS_WDATAREADY) == 0); - EFM32_MSC_WDATA = src[i]; - EFM32_MSC_WRITECMD = EFM32_MSC_WRITECMD_WRITEONCE; + EFM32_MSC_WDATA(msc) = src[i]; + EFM32_MSC_WRITECMD(msc) = EFM32_MSC_WRITECMD_WRITEONCE; /* Wait for BUSY */ - while ((EFM32_MSC_STATUS & EFM32_MSC_STATUS_BUSY)); + while ((EFM32_MSC_STATUS(msc) & EFM32_MSC_STATUS_BUSY)); } stub_exit(0); diff --git a/src/target/flashstub/efm32.stub b/src/target/flashstub/efm32.stub index 01fe5db..80418f1 100644 --- a/src/target/flashstub/efm32.stub +++ b/src/target/flashstub/efm32.stub @@ -1,41 +1 @@ - [0x0/2] = 0x4c10, - [0x2/2] = 0x4b11, - [0x4/2] = 0x0892, - [0x6/2] = 0x601c, - [0x8/2] = 0x2401, - [0xa/2] = 0x4b10, - [0xc/2] = 0x0092, - [0xe/2] = 0x601c, - [0x10/2] = 0x2400, - [0x12/2] = 0x4294, - [0x14/2] = 0xd015, - [0x16/2] = 0x4d0e, - [0x18/2] = 0x1903, - [0x1a/2] = 0x602b, - [0x1c/2] = 0x2501, - [0x1e/2] = 0x4b0d, - [0x20/2] = 0x601d, - [0x22/2] = 0x2608, - [0x24/2] = 0x4d0c, - [0x26/2] = 0x682f, - [0x28/2] = 0x46ac, - [0x2a/2] = 0x4237, - [0x2c/2] = 0xd0f9, - [0x2e/2] = 0x590d, - [0x30/2] = 0x4f0a, - [0x32/2] = 0x603d, - [0x34/2] = 0x601e, - [0x36/2] = 0x4663, - [0x38/2] = 0x681b, - [0x3a/2] = 0x07db, - [0x3c/2] = 0xd4fb, - [0x3e/2] = 0x3404, - [0x40/2] = 0xe7e7, - [0x42/2] = 0xbe00, - [0x44/2] = 0x1b71, 0x0000, - [0x48/2] = 0x003c, 0x400c, - [0x4c/2] = 0x0008, 0x400c, - [0x50/2] = 0x0010, 0x400c, - [0x54/2] = 0x000c, 0x400c, - [0x58/2] = 0x001c, 0x400c, - [0x5c/2] = 0x0018, 0x400c, +0x4D10, 0x2440, 0x42AB, 0xD000, 0x3C04, 0x4D0F, 0x18E4, 0x6025, 0x2401, 0x609C, 0x2400, 0x0892, 0x0092, 0x4294, 0xD011, 0x1905, 0x611D, 0x2501, 0x60DD, 0x1C1E, 0x2508, 0x69DF, 0x361C, 0x422F, 0xD0F9, 0x590F, 0x619F, 0x60DD, 0x6835, 0x07ED, 0xD4FC, 0x3404, 0xE7EB, 0xBE00, 0x0000, 0x400E, 0x1B71, 0x0000, \ No newline at end of file