From a3703186beb0da992a157aabdfe248800ed1b6d3 Mon Sep 17 00:00:00 2001 From: dragonmux Date: Fri, 19 Aug 2022 17:31:37 +0100 Subject: [PATCH] usbuart: Moved aux_serial_init() into aux_serial.c --- src/platforms/common/aux_serial.c | 142 ++++++++++++++++++++++++++++++ src/platforms/stm32/usbuart.c | 98 --------------------- src/platforms/tm4c/usbuart.c | 37 -------- 3 files changed, 142 insertions(+), 135 deletions(-) diff --git a/src/platforms/common/aux_serial.c b/src/platforms/common/aux_serial.c index 85d6c77..70d7286 100644 --- a/src/platforms/common/aux_serial.c +++ b/src/platforms/common/aux_serial.c @@ -19,6 +19,7 @@ */ #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32F4) +#include #include #include #elif defined(LM4F) @@ -26,6 +27,7 @@ #else #error "Unknown processor target" #endif +#include #include #include @@ -38,8 +40,148 @@ static char aux_serial_transmit_buffer[2U][TX_BUF_SIZE]; static uint8_t aux_serial_transmit_buffer_index; static uint8_t aux_serial_transmit_buffer_consumed; + +#ifdef DMA_STREAM0 +#define dma_channel_reset(dma, channel) dma_stream_reset(dma, channel) +#define dma_enable_channel(dma, channel) dma_enable_stream(dma, channel) +#define dma_disable_channel(dma, channel) dma_disable_stream(dma, channel) + +#define DMA_PSIZE_8BIT DMA_SxCR_PSIZE_8BIT +#define DMA_MSIZE_8BIT DMA_SxCR_MSIZE_8BIT +#define DMA_PL_HIGH DMA_SxCR_PL_HIGH +#define DMA_CGIF DMA_ISR_FLAGS +#else +#define DMA_PSIZE_8BIT DMA_CCR_PSIZE_8BIT +#define DMA_MSIZE_8BIT DMA_CCR_MSIZE_8BIT +#define DMA_PL_HIGH DMA_CCR_PL_HIGH +#define DMA_CGIF DMA_IFCR_CGIF_BIT +#endif + +void aux_serial_init(void) +{ + /* Enable clocks */ + rcc_periph_clock_enable(USBUSART_CLK); + rcc_periph_clock_enable(USBUSART_DMA_CLK); + + /* Setup UART parameters */ + UART_PIN_SETUP(); + usart_set_baudrate(USBUSART, 38400); + usart_set_databits(USBUSART, 8); + usart_set_stopbits(USBUSART, USART_STOPBITS_1); + usart_set_mode(USBUSART, USART_MODE_TX_RX); + usart_set_parity(USBUSART, USART_PARITY_NONE); + usart_set_flow_control(USBUSART, USART_FLOWCONTROL_NONE); + USART_CR1(USBUSART) |= USART_CR1_IDLEIE; + + /* Setup USART TX DMA */ +#if !defined(USBUSART_TDR) && defined(USBUSART_DR) +# define USBUSART_TDR USBUSART_DR +#elif !defined(USBUSART_TDR) +# define USBUSART_TDR USART_DR(USBUSART) +#endif +#if !defined(USBUSART_RDR) && defined(USBUSART_DR) +# define USBUSART_RDR USBUSART_DR +#elif !defined(USBUSART_RDR) +# define USBUSART_RDR USART_DR(USBUSART) +#endif + dma_channel_reset(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN); + dma_set_peripheral_address(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN, (uint32_t)&USBUSART_TDR); + dma_enable_memory_increment_mode(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN); + dma_set_peripheral_size(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN, DMA_PSIZE_8BIT); + dma_set_memory_size(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN, DMA_MSIZE_8BIT); + dma_set_priority(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN, DMA_PL_HIGH); + dma_enable_transfer_complete_interrupt(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN); +#ifdef DMA_STREAM0 + dma_set_transfer_mode(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN, DMA_SxCR_DIR_MEM_TO_PERIPHERAL); + dma_channel_select(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN, USBUSART_DMA_TRG); + dma_set_dma_flow_control(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN); + dma_enable_direct_mode(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN); +#else + dma_set_read_from_memory(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN); +#endif + + /* Setup USART RX DMA */ + dma_channel_reset(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); + dma_set_peripheral_address(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, (uint32_t)&USBUSART_RDR); + dma_set_memory_address(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, (uint32_t)buf_rx); + dma_set_number_of_data(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, RX_FIFO_SIZE); + dma_enable_memory_increment_mode(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); + dma_enable_circular_mode(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); + dma_set_peripheral_size(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, DMA_PSIZE_8BIT); + dma_set_memory_size(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, DMA_MSIZE_8BIT); + dma_set_priority(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, DMA_PL_HIGH); + dma_enable_half_transfer_interrupt(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); + dma_enable_transfer_complete_interrupt(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); +#ifdef DMA_STREAM0 + dma_set_transfer_mode(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, DMA_SxCR_DIR_PERIPHERAL_TO_MEM); + dma_channel_select(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, USBUSART_DMA_TRG); + dma_set_dma_flow_control(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); + dma_enable_direct_mode(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); +#else + dma_set_read_from_peripheral(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); +#endif + dma_enable_channel(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); + + /* Enable interrupts */ + nvic_set_priority(USBUSART_IRQ, IRQ_PRI_USBUSART); +#if defined(USBUSART_DMA_RXTX_IRQ) + nvic_set_priority(USBUSART_DMA_RXTX_IRQ, IRQ_PRI_USBUSART_DMA); +#else + nvic_set_priority(USBUSART_DMA_TX_IRQ, IRQ_PRI_USBUSART_DMA); + nvic_set_priority(USBUSART_DMA_RX_IRQ, IRQ_PRI_USBUSART_DMA); +#endif + nvic_enable_irq(USBUSART_IRQ); +#if defined(USBUSART_DMA_RXTX_IRQ) + nvic_enable_irq(USBUSART_DMA_RXTX_IRQ); +#else + nvic_enable_irq(USBUSART_DMA_TX_IRQ); + nvic_enable_irq(USBUSART_DMA_RX_IRQ); +#endif + + /* Finally enable the USART */ + usart_enable(USBUSART); + usart_enable_tx_dma(USBUSART); + usart_enable_rx_dma(USBUSART); +} #elif defined(LM4F) static char aux_serial_transmit_buffer[FIFO_SIZE]; + +void aux_serial_init(void) +{ + UART_PIN_SETUP(); + + periph_clock_enable(USBUART_CLK); + __asm__("nop"); + __asm__("nop"); + __asm__("nop"); + + uart_disable(USBUART); + + /* Setup UART parameters. */ + uart_clock_from_sysclk(USBUART); + uart_set_baudrate(USBUART, 38400); + uart_set_databits(USBUART, 8); + uart_set_stopbits(USBUART, 1); + uart_set_parity(USBUART, UART_PARITY_NONE); + + // Enable FIFO + uart_enable_fifo(USBUART); + + // Set FIFO interrupt trigger levels to 1/8 full for RX buffer and + // 7/8 empty (1/8 full) for TX buffer + uart_set_fifo_trigger_levels(USBUART, UART_FIFO_RX_TRIG_1_8, UART_FIFO_TX_TRIG_7_8); + + uart_clear_interrupt_flag(USBUART, UART_INT_RX | UART_INT_RT); + + /* Enable interrupts */ + uart_enable_interrupts(UART0, UART_INT_RX| UART_INT_RT); + + /* Finally enable the USART. */ + uart_enable(USBUART); + + //nvic_set_priority(USBUSART_IRQ, IRQ_PRI_USBUSART); + nvic_enable_irq(USBUART_IRQ); +} #endif void aux_serial_set_encoding(struct usb_cdc_line_coding *coding) diff --git a/src/platforms/stm32/usbuart.c b/src/platforms/stm32/usbuart.c index 728a19c..466f5dd 100644 --- a/src/platforms/stm32/usbuart.c +++ b/src/platforms/stm32/usbuart.c @@ -18,7 +18,6 @@ * along with this program. If not, see . */ -#include #include #include #include @@ -34,18 +33,8 @@ #include "aux_serial.h" #ifdef DMA_STREAM0 -#define dma_channel_reset(dma, channel) dma_stream_reset(dma, channel) -#define dma_enable_channel(dma, channel) dma_enable_stream(dma, channel) -#define dma_disable_channel(dma, channel) dma_disable_stream(dma, channel) - -#define DMA_PSIZE_8BIT DMA_SxCR_PSIZE_8BIT -#define DMA_MSIZE_8BIT DMA_SxCR_MSIZE_8BIT -#define DMA_PL_HIGH DMA_SxCR_PL_HIGH #define DMA_CGIF DMA_ISR_FLAGS #else -#define DMA_PSIZE_8BIT DMA_CCR_PSIZE_8BIT -#define DMA_MSIZE_8BIT DMA_CCR_MSIZE_8BIT -#define DMA_PL_HIGH DMA_CCR_PL_HIGH #define DMA_CGIF DMA_IFCR_CGIF_BIT #endif @@ -89,93 +78,6 @@ void usbuart_set_led_state(uint8_t ledn, bool state) } } -void aux_serial_init(void) -{ - /* Enable clocks */ - rcc_periph_clock_enable(USBUSART_CLK); - rcc_periph_clock_enable(USBUSART_DMA_CLK); - - /* Setup UART parameters */ - UART_PIN_SETUP(); - usart_set_baudrate(USBUSART, 38400); - usart_set_databits(USBUSART, 8); - usart_set_stopbits(USBUSART, USART_STOPBITS_1); - usart_set_mode(USBUSART, USART_MODE_TX_RX); - usart_set_parity(USBUSART, USART_PARITY_NONE); - usart_set_flow_control(USBUSART, USART_FLOWCONTROL_NONE); - USART_CR1(USBUSART) |= USART_CR1_IDLEIE; - - /* Setup USART TX DMA */ -#if !defined(USBUSART_TDR) && defined(USBUSART_DR) -# define USBUSART_TDR USBUSART_DR -#elif !defined(USBUSART_TDR) -# define USBUSART_TDR USART_DR(USBUSART) -#endif -#if !defined(USBUSART_RDR) && defined(USBUSART_DR) -# define USBUSART_RDR USBUSART_DR -#elif !defined(USBUSART_RDR) -# define USBUSART_RDR USART_DR(USBUSART) -#endif - dma_channel_reset(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN); - dma_set_peripheral_address(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN, (uint32_t)&USBUSART_TDR); - dma_enable_memory_increment_mode(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN); - dma_set_peripheral_size(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN, DMA_PSIZE_8BIT); - dma_set_memory_size(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN, DMA_MSIZE_8BIT); - dma_set_priority(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN, DMA_PL_HIGH); - dma_enable_transfer_complete_interrupt(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN); -#ifdef DMA_STREAM0 - dma_set_transfer_mode(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN, DMA_SxCR_DIR_MEM_TO_PERIPHERAL); - dma_channel_select(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN, USBUSART_DMA_TRG); - dma_set_dma_flow_control(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN); - dma_enable_direct_mode(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN); -#else - dma_set_read_from_memory(USBUSART_DMA_BUS, USBUSART_DMA_TX_CHAN); -#endif - - /* Setup USART RX DMA */ - dma_channel_reset(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); - dma_set_peripheral_address(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, (uint32_t)&USBUSART_RDR); - dma_set_memory_address(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, (uint32_t)buf_rx); - dma_set_number_of_data(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, RX_FIFO_SIZE); - dma_enable_memory_increment_mode(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); - dma_enable_circular_mode(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); - dma_set_peripheral_size(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, DMA_PSIZE_8BIT); - dma_set_memory_size(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, DMA_MSIZE_8BIT); - dma_set_priority(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, DMA_PL_HIGH); - dma_enable_half_transfer_interrupt(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); - dma_enable_transfer_complete_interrupt(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); -#ifdef DMA_STREAM0 - dma_set_transfer_mode(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, DMA_SxCR_DIR_PERIPHERAL_TO_MEM); - dma_channel_select(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN, USBUSART_DMA_TRG); - dma_set_dma_flow_control(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); - dma_enable_direct_mode(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); -#else - dma_set_read_from_peripheral(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); -#endif - dma_enable_channel(USBUSART_DMA_BUS, USBUSART_DMA_RX_CHAN); - - /* Enable interrupts */ - nvic_set_priority(USBUSART_IRQ, IRQ_PRI_USBUSART); -#if defined(USBUSART_DMA_RXTX_IRQ) - nvic_set_priority(USBUSART_DMA_RXTX_IRQ, IRQ_PRI_USBUSART_DMA); -#else - nvic_set_priority(USBUSART_DMA_TX_IRQ, IRQ_PRI_USBUSART_DMA); - nvic_set_priority(USBUSART_DMA_RX_IRQ, IRQ_PRI_USBUSART_DMA); -#endif - nvic_enable_irq(USBUSART_IRQ); -#if defined(USBUSART_DMA_RXTX_IRQ) - nvic_enable_irq(USBUSART_DMA_RXTX_IRQ); -#else - nvic_enable_irq(USBUSART_DMA_TX_IRQ); - nvic_enable_irq(USBUSART_DMA_RX_IRQ); -#endif - - /* Finally enable the USART */ - usart_enable(USBUSART); - usart_enable_tx_dma(USBUSART); - usart_enable_rx_dma(USBUSART); -} - #if defined(USART_ICR) #define USBUSART_ISR_TEMPLATE(USART, DMA_IRQ) do { \ nvic_disable_irq(DMA_IRQ); \ diff --git a/src/platforms/tm4c/usbuart.c b/src/platforms/tm4c/usbuart.c index 94e5a0c..31b5461 100644 --- a/src/platforms/tm4c/usbuart.c +++ b/src/platforms/tm4c/usbuart.c @@ -39,43 +39,6 @@ uint8_t buf_rx_in; /* Fifo out pointer, writes assumed to be atomic, should be only incremented outside RX ISR */ uint8_t buf_rx_out; -void aux_serial_init(void) -{ - UART_PIN_SETUP(); - - periph_clock_enable(USBUART_CLK); - __asm__("nop"); - __asm__("nop"); - __asm__("nop"); - - uart_disable(USBUART); - - /* Setup UART parameters. */ - uart_clock_from_sysclk(USBUART); - uart_set_baudrate(USBUART, 38400); - uart_set_databits(USBUART, 8); - uart_set_stopbits(USBUART, 1); - uart_set_parity(USBUART, UART_PARITY_NONE); - - // Enable FIFO - uart_enable_fifo(USBUART); - - // Set FIFO interrupt trigger levels to 1/8 full for RX buffer and - // 7/8 empty (1/8 full) for TX buffer - uart_set_fifo_trigger_levels(USBUART, UART_FIFO_RX_TRIG_1_8, UART_FIFO_TX_TRIG_7_8); - - uart_clear_interrupt_flag(USBUART, UART_INT_RX | UART_INT_RT); - - /* Enable interrupts */ - uart_enable_interrupts(UART0, UART_INT_RX| UART_INT_RT); - - /* Finally enable the USART. */ - uart_enable(USBUART); - - //nvic_set_priority(USBUSART_IRQ, IRQ_PRI_USBUSART); - nvic_enable_irq(USBUART_IRQ); -} - /* * Read a character from the UART RX and stuff it in a software FIFO. * Allowed to read from FIFO out pointer, but not write to it.