From a3ab9b24d1c3b4dd6678fc88289f0cf397e52c6c Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Sun, 18 Jan 2015 12:16:17 +1300 Subject: [PATCH] Avoid repetition of cortexm code in stmd20 driver. --- src/cortexm.c | 134 ++---------------------------------------- src/include/cortexm.h | 130 ++++++++++++++++++++++++++++++++++++++++ src/samd20.c | 133 +---------------------------------------- 3 files changed, 138 insertions(+), 259 deletions(-) create mode 100644 src/include/cortexm.h diff --git a/src/cortexm.c b/src/cortexm.c index 731632e..b7f71eb 100644 --- a/src/cortexm.c +++ b/src/cortexm.c @@ -40,6 +40,7 @@ #include "target.h" #include "command.h" #include "gdb_packet.h" +#include "cortexm.h" static char cortexm_driver_str[] = "ARM Cortex-M"; @@ -54,142 +55,18 @@ const struct command_s cortexm_cmd_list[] = { #define TOPT_FLAVOUR_V6M (1<<0) /* if not set, target is assumed to be v7m */ #define TOPT_FLAVOUR_V7MF (1<<1) /* if set, floating-point enabled. */ -/* Private peripheral bus base address */ -#define CORTEXM_PPB_BASE 0xE0000000 - -#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xE000) - -#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xD0C) -#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xD28) -#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xD2C) -#define CORTEXM_DFSR (CORTEXM_SCS_BASE + 0xD30) -#define CORTEXM_CPACR (CORTEXM_SCS_BASE + 0xD88) -#define CORTEXM_DHCSR (CORTEXM_SCS_BASE + 0xDF0) -#define CORTEXM_DCRSR (CORTEXM_SCS_BASE + 0xDF4) -#define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xDF8) -#define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xDFC) - -#define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000) - -/* ARM Literature uses FP_*, we use CORTEXM_FPB_* consistently */ -#define CORTEXM_FPB_CTRL (CORTEXM_FPB_BASE + 0x000) -#define CORTEXM_FPB_REMAP (CORTEXM_FPB_BASE + 0x004) -#define CORTEXM_FPB_COMP(i) (CORTEXM_FPB_BASE + 0x008 + (4*(i))) - -#define CORTEXM_DWT_BASE (CORTEXM_PPB_BASE + 0x1000) - -#define CORTEXM_DWT_CTRL (CORTEXM_DWT_BASE + 0x000) -#define CORTEXM_DWT_COMP(i) (CORTEXM_DWT_BASE + 0x020 + (0x10*(i))) -#define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024 + (0x10*(i))) -#define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028 + (0x10*(i))) - -/* Application Interrupt and Reset Control Register (AIRCR) */ -#define CORTEXM_AIRCR_VECTKEY (0x05FA << 16) -/* Bits 31:16 - Read as VECTKETSTAT, 0xFA05 */ -#define CORTEXM_AIRCR_ENDIANESS (1 << 15) -/* Bits 15:11 - Unused, reserved */ -#define CORTEXM_AIRCR_PRIGROUP (7 << 8) -/* Bits 7:3 - Unused, reserved */ -#define CORTEXM_AIRCR_SYSRESETREQ (1 << 2) -#define CORTEXM_AIRCR_VECTCLRACTIVE (1 << 1) -#define CORTEXM_AIRCR_VECTRESET (1 << 0) - -/* HardFault Status Register (HFSR) */ -#define CORTEXM_HFSR_DEBUGEVT (1 << 31) -#define CORTEXM_HFSR_FORCED (1 << 30) -/* Bits 29:2 - Not specified */ -#define CORTEXM_HFSR_VECTTBL (1 << 1) -/* Bits 0 - Reserved */ - -/* Debug Fault Status Register (DFSR) */ -/* Bits 31:5 - Reserved */ -#define CORTEXM_DFSR_RESETALL 0x1F -#define CORTEXM_DFSR_EXTERNAL (1 << 4) -#define CORTEXM_DFSR_VCATCH (1 << 3) -#define CORTEXM_DFSR_DWTTRAP (1 << 2) -#define CORTEXM_DFSR_BKPT (1 << 1) -#define CORTEXM_DFSR_HALTED (1 << 0) - -/* Debug Halting Control and Status Register (DHCSR) */ -/* This key must be written to bits 31:16 for write to take effect */ -#define CORTEXM_DHCSR_DBGKEY 0xA05F0000 -/* Bits 31:26 - Reserved */ -#define CORTEXM_DHCSR_S_RESET_ST (1 << 25) -#define CORTEXM_DHCSR_S_RETIRE_ST (1 << 24) -/* Bits 23:20 - Reserved */ -#define CORTEXM_DHCSR_S_LOCKUP (1 << 19) -#define CORTEXM_DHCSR_S_SLEEP (1 << 18) -#define CORTEXM_DHCSR_S_HALT (1 << 17) -#define CORTEXM_DHCSR_S_REGRDY (1 << 16) -/* Bits 15:6 - Reserved */ -#define CORTEXM_DHCSR_C_SNAPSTALL (1 << 5) /* v7m only */ -/* Bit 4 - Reserved */ -#define CORTEXM_DHCSR_C_MASKINTS (1 << 3) -#define CORTEXM_DHCSR_C_STEP (1 << 2) -#define CORTEXM_DHCSR_C_HALT (1 << 1) -#define CORTEXM_DHCSR_C_DEBUGEN (1 << 0) - -/* Debug Core Register Selector Register (DCRSR) */ -#define CORTEXM_DCRSR_REGWnR 0x00010000 -#define CORTEXM_DCRSR_REGSEL_MASK 0x0000001F -#define CORTEXM_DCRSR_REGSEL_XPSR 0x00000010 -#define CORTEXM_DCRSR_REGSEL_MSP 0x00000011 -#define CORTEXM_DCRSR_REGSEL_PSP 0x00000012 - -/* Debug Exception and Monitor Control Register (DEMCR) */ -/* Bits 31:25 - Reserved */ -#define CORTEXM_DEMCR_TRCENA (1 << 24) -/* Bits 23:20 - Reserved */ -#define CORTEXM_DEMCR_MON_REQ (1 << 19) /* v7m only */ -#define CORTEXM_DEMCR_MON_STEP (1 << 18) /* v7m only */ -#define CORTEXM_DEMCR_VC_MON_PEND (1 << 17) /* v7m only */ -#define CORTEXM_DEMCR_VC_MON_EN (1 << 16) /* v7m only */ -/* Bits 15:11 - Reserved */ -#define CORTEXM_DEMCR_VC_HARDERR (1 << 10) -#define CORTEXM_DEMCR_VC_INTERR (1 << 9) /* v7m only */ -#define CORTEXM_DEMCR_VC_BUSERR (1 << 8) /* v7m only */ -#define CORTEXM_DEMCR_VC_STATERR (1 << 7) /* v7m only */ -#define CORTEXM_DEMCR_VC_CHKERR (1 << 6) /* v7m only */ -#define CORTEXM_DEMCR_VC_NOCPERR (1 << 5) /* v7m only */ -#define CORTEXM_DEMCR_VC_MMERR (1 << 4) /* v7m only */ -/* Bits 3:1 - Reserved */ -#define CORTEXM_DEMCR_VC_CORERESET (1 << 0) - -/* Flash Patch and Breakpoint Control Register (FP_CTRL) */ -/* Bits 32:15 - Reserved */ -/* Bits 14:12 - NUM_CODE2 */ /* v7m only */ -/* Bits 11:8 - NUM_LIT */ /* v7m only */ -/* Bits 7:4 - NUM_CODE1 */ -/* Bits 3:2 - Unspecified */ -#define CORTEXM_FPB_CTRL_KEY (1 << 1) -#define CORTEXM_FPB_CTRL_ENABLE (1 << 0) - -/* Data Watchpoint and Trace Mask Register (DWT_MASKx) */ -#define CORTEXM_DWT_MASK_BYTE (0 << 0) -#define CORTEXM_DWT_MASK_HALFWORD (1 << 0) -#define CORTEXM_DWT_MASK_WORD (3 << 0) - -/* Data Watchpoint and Trace Function Register (DWT_FUNCTIONx) */ -#define CORTEXM_DWT_FUNC_MATCHED (1 << 24) -#define CORTEXM_DWT_FUNC_DATAVSIZE_WORD (2 << 10) /* v7m only */ -#define CORTEXM_DWT_FUNC_FUNC_READ (5 << 0) -#define CORTEXM_DWT_FUNC_FUNC_WRITE (6 << 0) -#define CORTEXM_DWT_FUNC_FUNC_ACCESS (7 << 0) - /* Signals returned by cortexm_halt_wait() */ #define SIGINT 2 #define SIGTRAP 5 #define SIGSEGV 11 static bool cortexm_attach(struct target_s *target); -static void cortexm_detach(struct target_s *target); static int cortexm_regs_read(struct target_s *target, void *data); static int cortexm_regs_write(struct target_s *target, const void *data); static int cortexm_pc_write(struct target_s *target, const uint32_t val); static void cortexm_reset(struct target_s *target); -static void cortexm_halt_resume(struct target_s *target, bool step); static int cortexm_halt_wait(struct target_s *target); static void cortexm_halt_request(struct target_s *target); static int cortexm_fault_unwind(struct target_s *target); @@ -456,8 +333,7 @@ cortexm_attach(struct target_s *target) return true; } -static void -cortexm_detach(struct target_s *target) +void cortexm_detach(struct target_s *target) { ADIv5_AP_t *ap = adiv5_target_ap(target); struct cortexm_priv *priv = ap->priv; @@ -646,14 +522,14 @@ cortexm_halt_wait(struct target_s *target) } -static void -cortexm_halt_resume(struct target_s *target, bool step) +void cortexm_halt_resume(struct target_s *target, bool step) { ADIv5_AP_t *ap = adiv5_target_ap(target); struct cortexm_priv *priv = ap->priv; uint32_t dhcsr = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN; - if(step) dhcsr |= CORTEXM_DHCSR_C_STEP | CORTEXM_DHCSR_C_MASKINTS; + if (step) + dhcsr |= CORTEXM_DHCSR_C_STEP | CORTEXM_DHCSR_C_MASKINTS; /* Disable interrupts while single stepping... */ if(step != priv->stepping) { diff --git a/src/include/cortexm.h b/src/include/cortexm.h new file mode 100644 index 0000000..f6170b0 --- /dev/null +++ b/src/include/cortexm.h @@ -0,0 +1,130 @@ +#ifndef __CORTEXM_H +#define __CORTEXM_H + +/* Private peripheral bus base address */ +#define CORTEXM_PPB_BASE 0xE0000000 + +#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xE000) + +#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xD0C) +#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xD28) +#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xD2C) +#define CORTEXM_DFSR (CORTEXM_SCS_BASE + 0xD30) +#define CORTEXM_CPACR (CORTEXM_SCS_BASE + 0xD88) +#define CORTEXM_DHCSR (CORTEXM_SCS_BASE + 0xDF0) +#define CORTEXM_DCRSR (CORTEXM_SCS_BASE + 0xDF4) +#define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xDF8) +#define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xDFC) + +#define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000) + +/* ARM Literature uses FP_*, we use CORTEXM_FPB_* consistently */ +#define CORTEXM_FPB_CTRL (CORTEXM_FPB_BASE + 0x000) +#define CORTEXM_FPB_REMAP (CORTEXM_FPB_BASE + 0x004) +#define CORTEXM_FPB_COMP(i) (CORTEXM_FPB_BASE + 0x008 + (4*(i))) + +#define CORTEXM_DWT_BASE (CORTEXM_PPB_BASE + 0x1000) + +#define CORTEXM_DWT_CTRL (CORTEXM_DWT_BASE + 0x000) +#define CORTEXM_DWT_COMP(i) (CORTEXM_DWT_BASE + 0x020 + (0x10*(i))) +#define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024 + (0x10*(i))) +#define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028 + (0x10*(i))) + +/* Application Interrupt and Reset Control Register (AIRCR) */ +#define CORTEXM_AIRCR_VECTKEY (0x05FA << 16) +/* Bits 31:16 - Read as VECTKETSTAT, 0xFA05 */ +#define CORTEXM_AIRCR_ENDIANESS (1 << 15) +/* Bits 15:11 - Unused, reserved */ +#define CORTEXM_AIRCR_PRIGROUP (7 << 8) +/* Bits 7:3 - Unused, reserved */ +#define CORTEXM_AIRCR_SYSRESETREQ (1 << 2) +#define CORTEXM_AIRCR_VECTCLRACTIVE (1 << 1) +#define CORTEXM_AIRCR_VECTRESET (1 << 0) + +/* HardFault Status Register (HFSR) */ +#define CORTEXM_HFSR_DEBUGEVT (1 << 31) +#define CORTEXM_HFSR_FORCED (1 << 30) +/* Bits 29:2 - Not specified */ +#define CORTEXM_HFSR_VECTTBL (1 << 1) +/* Bits 0 - Reserved */ + +/* Debug Fault Status Register (DFSR) */ +/* Bits 31:5 - Reserved */ +#define CORTEXM_DFSR_RESETALL 0x1F +#define CORTEXM_DFSR_EXTERNAL (1 << 4) +#define CORTEXM_DFSR_VCATCH (1 << 3) +#define CORTEXM_DFSR_DWTTRAP (1 << 2) +#define CORTEXM_DFSR_BKPT (1 << 1) +#define CORTEXM_DFSR_HALTED (1 << 0) + +/* Debug Halting Control and Status Register (DHCSR) */ +/* This key must be written to bits 31:16 for write to take effect */ +#define CORTEXM_DHCSR_DBGKEY 0xA05F0000 +/* Bits 31:26 - Reserved */ +#define CORTEXM_DHCSR_S_RESET_ST (1 << 25) +#define CORTEXM_DHCSR_S_RETIRE_ST (1 << 24) +/* Bits 23:20 - Reserved */ +#define CORTEXM_DHCSR_S_LOCKUP (1 << 19) +#define CORTEXM_DHCSR_S_SLEEP (1 << 18) +#define CORTEXM_DHCSR_S_HALT (1 << 17) +#define CORTEXM_DHCSR_S_REGRDY (1 << 16) +/* Bits 15:6 - Reserved */ +#define CORTEXM_DHCSR_C_SNAPSTALL (1 << 5) /* v7m only */ +/* Bit 4 - Reserved */ +#define CORTEXM_DHCSR_C_MASKINTS (1 << 3) +#define CORTEXM_DHCSR_C_STEP (1 << 2) +#define CORTEXM_DHCSR_C_HALT (1 << 1) +#define CORTEXM_DHCSR_C_DEBUGEN (1 << 0) + +/* Debug Core Register Selector Register (DCRSR) */ +#define CORTEXM_DCRSR_REGWnR 0x00010000 +#define CORTEXM_DCRSR_REGSEL_MASK 0x0000001F +#define CORTEXM_DCRSR_REGSEL_XPSR 0x00000010 +#define CORTEXM_DCRSR_REGSEL_MSP 0x00000011 +#define CORTEXM_DCRSR_REGSEL_PSP 0x00000012 + +/* Debug Exception and Monitor Control Register (DEMCR) */ +/* Bits 31:25 - Reserved */ +#define CORTEXM_DEMCR_TRCENA (1 << 24) +/* Bits 23:20 - Reserved */ +#define CORTEXM_DEMCR_MON_REQ (1 << 19) /* v7m only */ +#define CORTEXM_DEMCR_MON_STEP (1 << 18) /* v7m only */ +#define CORTEXM_DEMCR_VC_MON_PEND (1 << 17) /* v7m only */ +#define CORTEXM_DEMCR_VC_MON_EN (1 << 16) /* v7m only */ +/* Bits 15:11 - Reserved */ +#define CORTEXM_DEMCR_VC_HARDERR (1 << 10) +#define CORTEXM_DEMCR_VC_INTERR (1 << 9) /* v7m only */ +#define CORTEXM_DEMCR_VC_BUSERR (1 << 8) /* v7m only */ +#define CORTEXM_DEMCR_VC_STATERR (1 << 7) /* v7m only */ +#define CORTEXM_DEMCR_VC_CHKERR (1 << 6) /* v7m only */ +#define CORTEXM_DEMCR_VC_NOCPERR (1 << 5) /* v7m only */ +#define CORTEXM_DEMCR_VC_MMERR (1 << 4) /* v7m only */ +/* Bits 3:1 - Reserved */ +#define CORTEXM_DEMCR_VC_CORERESET (1 << 0) + +/* Flash Patch and Breakpoint Control Register (FP_CTRL) */ +/* Bits 32:15 - Reserved */ +/* Bits 14:12 - NUM_CODE2 */ /* v7m only */ +/* Bits 11:8 - NUM_LIT */ /* v7m only */ +/* Bits 7:4 - NUM_CODE1 */ +/* Bits 3:2 - Unspecified */ +#define CORTEXM_FPB_CTRL_KEY (1 << 1) +#define CORTEXM_FPB_CTRL_ENABLE (1 << 0) + +/* Data Watchpoint and Trace Mask Register (DWT_MASKx) */ +#define CORTEXM_DWT_MASK_BYTE (0 << 0) +#define CORTEXM_DWT_MASK_HALFWORD (1 << 0) +#define CORTEXM_DWT_MASK_WORD (3 << 0) + +/* Data Watchpoint and Trace Function Register (DWT_FUNCTIONx) */ +#define CORTEXM_DWT_FUNC_MATCHED (1 << 24) +#define CORTEXM_DWT_FUNC_DATAVSIZE_WORD (2 << 10) /* v7m only */ +#define CORTEXM_DWT_FUNC_FUNC_READ (5 << 0) +#define CORTEXM_DWT_FUNC_FUNC_WRITE (6 << 0) +#define CORTEXM_DWT_FUNC_FUNC_ACCESS (7 << 0) + +void cortexm_detach(struct target_s *target); +void cortexm_halt_resume(struct target_s *target, bool step); + +#endif + diff --git a/src/samd20.c b/src/samd20.c index 8b79049..b252524 100644 --- a/src/samd20.c +++ b/src/samd20.c @@ -39,6 +39,7 @@ #include "target.h" #include "command.h" #include "gdb_packet.h" +#include "cortexm.h" static int samd20_flash_erase(struct target_s *target, uint32_t addr, int len); static int samd20_flash_write(struct target_s *target, uint32_t dest, @@ -145,104 +146,6 @@ static const char samd20_xml_memory_map[] = "" /* Component ID */ #define SAMD20_CID_VALUE 0xB105100D -#define CORTEXM_PPB_BASE 0xE0000000 - -#define CORTEXM_SCS_BASE (CORTEXM_PPB_BASE + 0xE000) - -#define CORTEXM_AIRCR (CORTEXM_SCS_BASE + 0xD0C) -#define CORTEXM_CFSR (CORTEXM_SCS_BASE + 0xD28) -#define CORTEXM_HFSR (CORTEXM_SCS_BASE + 0xD2C) -#define CORTEXM_DFSR (CORTEXM_SCS_BASE + 0xD30) -#define CORTEXM_CPACR (CORTEXM_SCS_BASE + 0xD88) -#define CORTEXM_DHCSR (CORTEXM_SCS_BASE + 0xDF0) -#define CORTEXM_DCRSR (CORTEXM_SCS_BASE + 0xDF4) -#define CORTEXM_DCRDR (CORTEXM_SCS_BASE + 0xDF8) -#define CORTEXM_DEMCR (CORTEXM_SCS_BASE + 0xDFC) - -/* Application Interrupt and Reset Control Register (AIRCR) */ -#define CORTEXM_AIRCR_VECTKEY (0x05FA << 16) -/* Bits 31:16 - Read as VECTKETSTAT, 0xFA05 */ -#define CORTEXM_AIRCR_ENDIANESS (1 << 15) -/* Bits 15:11 - Unused, reserved */ -#define CORTEXM_AIRCR_PRIGROUP (7 << 8) -/* Bits 7:3 - Unused, reserved */ -#define CORTEXM_AIRCR_SYSRESETREQ (1 << 2) -#define CORTEXM_AIRCR_VECTCLRACTIVE (1 << 1) -#define CORTEXM_AIRCR_VECTRESET (1 << 0) - -/* Debug Fault Status Register (DFSR) */ -/* Bits 31:5 - Reserved */ -#define CORTEXM_DFSR_RESETALL 0x1F -#define CORTEXM_DFSR_EXTERNAL (1 << 4) -#define CORTEXM_DFSR_VCATCH (1 << 3) -#define CORTEXM_DFSR_DWTTRAP (1 << 2) -#define CORTEXM_DFSR_BKPT (1 << 1) -#define CORTEXM_DFSR_HALTED (1 << 0) - -/* Debug Halting Control and Status Register (DHCSR) */ -/* This key must be written to bits 31:16 for write to take effect */ -#define CORTEXM_DHCSR_DBGKEY 0xA05F0000 -/* Bits 31:26 - Reserved */ -#define CORTEXM_DHCSR_S_RESET_ST (1 << 25) -#define CORTEXM_DHCSR_S_RETIRE_ST (1 << 24) -/* Bits 23:20 - Reserved */ -#define CORTEXM_DHCSR_S_LOCKUP (1 << 19) -#define CORTEXM_DHCSR_S_SLEEP (1 << 18) -#define CORTEXM_DHCSR_S_HALT (1 << 17) -#define CORTEXM_DHCSR_S_REGRDY (1 << 16) -/* Bits 15:6 - Reserved */ -#define CORTEXM_DHCSR_C_SNAPSTALL (1 << 5) /* v7m only */ -/* Bit 4 - Reserved */ -#define CORTEXM_DHCSR_C_MASKINTS (1 << 3) -#define CORTEXM_DHCSR_C_STEP (1 << 2) -#define CORTEXM_DHCSR_C_HALT (1 << 1) -#define CORTEXM_DHCSR_C_DEBUGEN (1 << 0) - - -/* -------------------------------------------------------------------------- */ -/* Cortex-M definitions for SAM D20 revision B fix */ -/* -------------------------------------------------------------------------- */ - -#define CORTEXM_FPB_BASE (CORTEXM_PPB_BASE + 0x2000) - -/* ARM Literature uses FP_*, we use CORTEXM_FPB_* consistently */ -#define CORTEXM_FPB_CTRL (CORTEXM_FPB_BASE + 0x000) -#define CORTEXM_FPB_REMAP (CORTEXM_FPB_BASE + 0x004) -#define CORTEXM_FPB_COMP(i) (CORTEXM_FPB_BASE + 0x008 + (4*(i))) - -#define CORTEXM_DWT_BASE (CORTEXM_PPB_BASE + 0x1000) - -#define CORTEXM_DWT_CTRL (CORTEXM_DWT_BASE + 0x000) -#define CORTEXM_DWT_COMP(i) (CORTEXM_DWT_BASE + 0x020 + (0x10*(i))) -#define CORTEXM_DWT_MASK(i) (CORTEXM_DWT_BASE + 0x024 + (0x10*(i))) -#define CORTEXM_DWT_FUNC(i) (CORTEXM_DWT_BASE + 0x028 + (0x10*(i))) - -#define CORTEXM_MAX_WATCHPOINTS 4 /* architecture says up to 15, no implementation has > 4 */ -#define CORTEXM_MAX_BREAKPOINTS 6 /* architecture says up to 127, no implementation has > 6 */ - -struct cortexm_priv { - bool stepping; - bool on_bkpt; - /* Watchpoint unit status */ - struct wp_unit_s { - uint32_t addr; - uint8_t type; - uint8_t size; - } hw_watchpoint[CORTEXM_MAX_WATCHPOINTS]; - unsigned hw_watchpoint_max; - /* Breakpoint unit status */ - uint32_t hw_breakpoint[CORTEXM_MAX_BREAKPOINTS]; - unsigned hw_breakpoint_max; - /* Copy of DEMCR for vector-catch */ - uint32_t demcr; - /* Semihosting state */ - uint32_t syscall; - uint32_t errno; - uint32_t byte_count; -}; - - - /* Utility */ #define MINIMUM(a,b) ((a < b) ? a : b) @@ -340,19 +243,7 @@ static void samd20_revB_detach(struct target_s *target) { ADIv5_AP_t *ap = adiv5_target_ap(target); - struct cortexm_priv *priv = ap->priv; - unsigned i; - - /* Clear any stale breakpoints */ - for(i = 0; i < priv->hw_breakpoint_max; i++) - adiv5_ap_mem_write(ap, CORTEXM_FPB_COMP(i), 0); - - /* Clear any stale watchpoints */ - for(i = 0; i < priv->hw_watchpoint_max; i++) - adiv5_ap_mem_write(ap, CORTEXM_DWT_FUNC(i), 0); - - /* Disable debug */ - adiv5_ap_mem_write(ap, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY); + cortexm_detach(target); /* ---- Additional ---- */ /* Exit extended reset */ @@ -374,25 +265,7 @@ static void samd20_revB_halt_resume(struct target_s *target, bool step) { ADIv5_AP_t *ap = adiv5_target_ap(target); - struct cortexm_priv *priv = ap->priv; - uint32_t dhcsr = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN; - - if(step) dhcsr |= CORTEXM_DHCSR_C_STEP | CORTEXM_DHCSR_C_MASKINTS; - - /* Disable interrupts while single stepping... */ - if(step != priv->stepping) { - adiv5_ap_mem_write(ap, CORTEXM_DHCSR, dhcsr | CORTEXM_DHCSR_C_HALT); - priv->stepping = step; - } - - if (priv->on_bkpt) { - uint32_t pc = target->pc_read(target); - if ((adiv5_ap_mem_read_halfword(ap, pc) & 0xFF00) == 0xBE00) - target->pc_write(target, pc + 2); - } - - adiv5_ap_mem_write(ap, CORTEXM_DHCSR, dhcsr); - ap->dp->allow_timeout = true; + cortexm_halt_resume(target, step); /* ---- Additional ---- */ /* Exit extended reset */