From aeaca988c3504bf2165b0a5ae1f9b0856c157e91 Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Mon, 4 Jul 2016 10:31:32 +1200 Subject: [PATCH] target: Use new target_addr type consistently in external interface. Flash routines still use uint32_t internally. --- src/gdb_main.c | 2 +- src/include/target.h | 18 +++++++++--------- src/target/cortexa.c | 18 +++++++++--------- src/target/cortexm.c | 24 ++++++++++++------------ src/target/target.c | 18 +++++++++--------- src/target/target_internal.h | 14 +++++++------- 6 files changed, 47 insertions(+), 47 deletions(-) diff --git a/src/gdb_main.c b/src/gdb_main.c index f92589a..c92a3e7 100644 --- a/src/gdb_main.c +++ b/src/gdb_main.c @@ -156,7 +156,7 @@ int gdb_main_loop(struct target_controller *tc, bool in_syscall) case '?': { /* '?': Request reason for target halt */ /* This packet isn't documented as being mandatory, * but GDB doesn't work without it. */ - uint32_t watch_addr; + target_addr watch_addr; int sig; if(!cur_target) { diff --git a/src/include/target.h b/src/include/target.h index fc3968b..523f545 100644 --- a/src/include/target.h +++ b/src/include/target.h @@ -91,8 +91,8 @@ bool target_check_error(target *t); bool target_attached(target *t); /* Memory access functions */ -void target_mem_read(target *t, void *dest, uint32_t src, size_t len); -void target_mem_write(target *t, uint32_t dest, const void *src, size_t len); +void target_mem_read(target *t, void *dest, target_addr src, size_t len); +void target_mem_write(target *t, target_addr dest, const void *src, size_t len); /* Register access functions */ void target_regs_read(target *t, void *data); @@ -105,16 +105,16 @@ int target_halt_wait(target *t); void target_halt_resume(target *t, bool step); /* Break-/watchpoint functions */ -int target_set_hw_bp(target *t, uint32_t addr, uint8_t len); -int target_clear_hw_bp(target *t, uint32_t addr, uint8_t len); +int target_set_hw_bp(target *t, target_addr addr, uint8_t len); +int target_clear_hw_bp(target *t, target_addr addr, uint8_t len); -int target_set_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len); -int target_clear_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len); -int target_check_hw_wp(target *t, uint32_t *addr); +int target_set_hw_wp(target *t, uint8_t type, target_addr addr, uint8_t len); +int target_clear_hw_wp(target *t, uint8_t type, target_addr addr, uint8_t len); +int target_check_hw_wp(target *t, target_addr *addr); /* Flash memory access functions */ -int target_flash_erase(target *t, uint32_t addr, size_t len); -int target_flash_write(target *t, uint32_t dest, const void *src, size_t len); +int target_flash_erase(target *t, target_addr addr, size_t len); +int target_flash_write(target *t, target_addr dest, const void *src, size_t len); int target_flash_done(target *t); /* Accessor functions */ diff --git a/src/target/cortexa.c b/src/target/cortexa.c index 24a8c6c..c622197 100644 --- a/src/target/cortexa.c +++ b/src/target/cortexa.c @@ -54,8 +54,8 @@ static void cortexa_reset(target *t); static int cortexa_halt_wait(target *t); static void cortexa_halt_request(target *t); -static int cortexa_set_hw_bp(target *t, uint32_t addr, uint8_t len); -static int cortexa_clear_hw_bp(target *t, uint32_t addr, uint8_t len); +static int cortexa_set_hw_bp(target *t, target_addr addr, uint8_t len); +static int cortexa_clear_hw_bp(target *t, target_addr addr, uint8_t len); static uint32_t bp_bas(uint32_t addr, uint8_t len); static void apb_write(target *t, uint16_t reg, uint32_t val); @@ -221,7 +221,7 @@ static uint32_t va_to_pa(target *t, uint32_t va) return pa; } -static void cortexa_mem_read(target *t, void *dest, uint32_t src, size_t len) +static void cortexa_mem_read(target *t, void *dest, target_addr src, size_t len) { /* Clean cache before reading */ for (uint32_t cl = src & ~(CACHE_LINE_LENGTH-1); @@ -234,7 +234,7 @@ static void cortexa_mem_read(target *t, void *dest, uint32_t src, size_t len) adiv5_mem_read(ahb, dest, va_to_pa(t, src), len); } -static void cortexa_slow_mem_read(target *t, void *dest, uint32_t src, size_t len) +static void cortexa_slow_mem_read(target *t, void *dest, target_addr src, size_t len) { struct cortexa_priv *priv = t->priv; unsigned words = (len + (src & 3) + 3) / 4; @@ -273,7 +273,7 @@ static void cortexa_slow_mem_read(target *t, void *dest, uint32_t src, size_t le } } -static void cortexa_mem_write(target *t, uint32_t dest, const void *src, size_t len) +static void cortexa_mem_write(target *t, target_addr dest, const void *src, size_t len) { /* Clean and invalidate cache before writing */ for (uint32_t cl = dest & ~(CACHE_LINE_LENGTH-1); @@ -285,7 +285,7 @@ static void cortexa_mem_write(target *t, uint32_t dest, const void *src, size_t adiv5_mem_write(ahb, va_to_pa(t, dest), src, len); } -static void cortexa_slow_mem_write_bytes(target *t, uint32_t dest, const uint8_t *src, size_t len) +static void cortexa_slow_mem_write_bytes(target *t, target_addr dest, const uint8_t *src, size_t len) { struct cortexa_priv *priv = t->priv; @@ -304,7 +304,7 @@ static void cortexa_slow_mem_write_bytes(target *t, uint32_t dest, const uint8_t } } -static void cortexa_slow_mem_write(target *t, uint32_t dest, const void *src, size_t len) +static void cortexa_slow_mem_write(target *t, target_addr dest, const void *src, size_t len) { struct cortexa_priv *priv = t->priv; if (len == 0) @@ -677,7 +677,7 @@ static uint32_t bp_bas(uint32_t addr, uint8_t len) return DBGBCR_BAS_LOW_HW; } -static int cortexa_set_hw_bp(target *t, uint32_t addr, uint8_t len) +static int cortexa_set_hw_bp(target *t, target_addr addr, uint8_t len) { struct cortexa_priv *priv = t->priv; unsigned i; @@ -698,7 +698,7 @@ static int cortexa_set_hw_bp(target *t, uint32_t addr, uint8_t len) return 0; } -static int cortexa_clear_hw_bp(target *t, uint32_t addr, uint8_t len) +static int cortexa_clear_hw_bp(target *t, target_addr addr, uint8_t len) { struct cortexa_priv *priv = t->priv; unsigned i; diff --git a/src/target/cortexm.c b/src/target/cortexm.c index fe05d5d..2dd976e 100644 --- a/src/target/cortexm.c +++ b/src/target/cortexm.c @@ -62,13 +62,13 @@ static int cortexm_halt_wait(target *t); static void cortexm_halt_request(target *t); static int cortexm_fault_unwind(target *t); -static int cortexm_set_hw_bp(target *t, uint32_t addr, uint8_t len); -static int cortexm_clear_hw_bp(target *t, uint32_t addr, uint8_t len); +static int cortexm_set_hw_bp(target *t, target_addr addr, uint8_t len); +static int cortexm_clear_hw_bp(target *t, target_addr addr, uint8_t len); -static int cortexm_set_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len); -static int cortexm_clear_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len); +static int cortexm_set_hw_wp(target *t, uint8_t type, target_addr addr, uint8_t len); +static int cortexm_clear_hw_wp(target *t, uint8_t type, target_addr addr, uint8_t len); -static int cortexm_check_hw_wp(target *t, uint32_t *addr); +static int cortexm_check_hw_wp(target *t, target_addr *addr); #define CORTEXM_MAX_WATCHPOINTS 4 /* architecture says up to 15, no implementation has > 4 */ #define CORTEXM_MAX_BREAKPOINTS 6 /* architecture says up to 127, no implementation has > 6 */ @@ -193,12 +193,12 @@ ADIv5_AP_t *cortexm_ap(target *t) return ((struct cortexm_priv *)t->priv)->ap; } -static void cortexm_mem_read(target *t, void *dest, uint32_t src, size_t len) +static void cortexm_mem_read(target *t, void *dest, target_addr src, size_t len) { adiv5_mem_read(cortexm_ap(t), dest, src, len); } -static void cortexm_mem_write(target *t, uint32_t dest, const void *src, size_t len) +static void cortexm_mem_write(target *t, target_addr dest, const void *src, size_t len) { adiv5_mem_write(cortexm_ap(t), dest, src, len); } @@ -656,7 +656,7 @@ int cortexm_run_stub(target *t, uint32_t loadaddr, /* The following routines implement hardware breakpoints. * The Flash Patch and Breakpoint (FPB) system is used. */ -static int cortexm_set_hw_bp(target *t, uint32_t addr, uint8_t len) +static int cortexm_set_hw_bp(target *t, target_addr addr, uint8_t len) { (void)len; struct cortexm_priv *priv = t->priv; @@ -681,7 +681,7 @@ static int cortexm_set_hw_bp(target *t, uint32_t addr, uint8_t len) return 0; } -static int cortexm_clear_hw_bp(target *t, uint32_t addr, uint8_t len) +static int cortexm_clear_hw_bp(target *t, target_addr addr, uint8_t len) { (void)len; struct cortexm_priv *priv = t->priv; @@ -703,7 +703,7 @@ static int cortexm_clear_hw_bp(target *t, uint32_t addr, uint8_t len) * The Data Watch and Trace (DWT) system is used. */ static int -cortexm_set_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len) +cortexm_set_hw_wp(target *t, uint8_t type, target_addr addr, uint8_t len) { struct cortexm_priv *priv = t->priv; unsigned i; @@ -744,7 +744,7 @@ cortexm_set_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len) } static int -cortexm_clear_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len) +cortexm_clear_hw_wp(target *t, uint8_t type, target_addr addr, uint8_t len) { struct cortexm_priv *priv = t->priv; unsigned i; @@ -779,7 +779,7 @@ cortexm_clear_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len) return 0; } -static int cortexm_check_hw_wp(target *t, uint32_t *addr) +static int cortexm_check_hw_wp(target *t, target_addr *addr) { struct cortexm_priv *priv = t->priv; unsigned i; diff --git a/src/target/target.c b/src/target/target.c index 3ae0b96..4b20aff 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -183,7 +183,7 @@ static struct target_flash *flash_for_addr(target *t, uint32_t addr) return NULL; } -int target_flash_erase(target *t, uint32_t addr, size_t len) +int target_flash_erase(target *t, target_addr addr, size_t len) { int ret = 0; while (len) { @@ -197,7 +197,7 @@ int target_flash_erase(target *t, uint32_t addr, size_t len) } int target_flash_write(target *t, - uint32_t dest, const void *src, size_t len) + target_addr dest, const void *src, size_t len) { int ret = 0; while (len) { @@ -288,12 +288,12 @@ bool target_check_error(target *t) { return t->check_error(t); } bool target_attached(target *t) { return t->attached; } /* Memory access functions */ -void target_mem_read(target *t, void *dest, uint32_t src, size_t len) +void target_mem_read(target *t, void *dest, target_addr src, size_t len) { t->mem_read(t, dest, src, len); } -void target_mem_write(target *t, uint32_t dest, const void *src, size_t len) +void target_mem_write(target *t, target_addr dest, const void *src, size_t len) { t->mem_write(t, dest, src, len); } @@ -309,35 +309,35 @@ int target_halt_wait(target *t) { return t->halt_wait(t); } void target_halt_resume(target *t, bool step) { t->halt_resume(t, step); } /* Break-/watchpoint functions */ -int target_set_hw_bp(target *t, uint32_t addr, uint8_t len) +int target_set_hw_bp(target *t, target_addr addr, uint8_t len) { if (t->set_hw_bp == NULL) return 0; return t->set_hw_bp(t, addr, len); } -int target_clear_hw_bp(target *t, uint32_t addr, uint8_t len) +int target_clear_hw_bp(target *t, target_addr addr, uint8_t len) { if (t->clear_hw_bp == NULL) return 0; return t->clear_hw_bp(t, addr, len); } -int target_set_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len) +int target_set_hw_wp(target *t, uint8_t type, target_addr addr, uint8_t len) { if (t->set_hw_wp == NULL) return 0; return t->set_hw_wp(t, type, addr, len); } -int target_clear_hw_wp(target *t, uint8_t type, uint32_t addr, uint8_t len) +int target_clear_hw_wp(target *t, uint8_t type, target_addr addr, uint8_t len) { if (t->clear_hw_wp == NULL) return 0; return t->clear_hw_wp(t, type, addr, len); } -int target_check_hw_wp(target *t, uint32_t *addr) +int target_check_hw_wp(target *t, target_addr *addr) { if (t->check_hw_wp == NULL) return 0; diff --git a/src/target/target_internal.h b/src/target/target_internal.h index 6c7e13d..9e52e7e 100644 --- a/src/target/target_internal.h +++ b/src/target/target_internal.h @@ -78,9 +78,9 @@ struct target_s { bool (*check_error)(target *t); /* Memory access functions */ - void (*mem_read)(target *t, void *dest, uint32_t src, + void (*mem_read)(target *t, void *dest, target_addr src, size_t len); - void (*mem_write)(target *t, uint32_t dest, + void (*mem_write)(target *t, target_addr dest, const void *src, size_t len); /* Register access functions */ @@ -96,13 +96,13 @@ struct target_s { void (*halt_resume)(target *t, bool step); /* Break-/watchpoint functions */ - int (*set_hw_bp)(target *t, uint32_t addr, uint8_t len); - int (*clear_hw_bp)(target *t, uint32_t addr, uint8_t len); + int (*set_hw_bp)(target *t, target_addr addr, uint8_t len); + int (*clear_hw_bp)(target *t, target_addr addr, uint8_t len); - int (*set_hw_wp)(target *t, uint8_t type, uint32_t addr, uint8_t len); - int (*clear_hw_wp)(target *t, uint8_t type, uint32_t addr, uint8_t len); + int (*set_hw_wp)(target *t, uint8_t type, target_addr addr, uint8_t len); + int (*clear_hw_wp)(target *t, uint8_t type, target_addr addr, uint8_t len); - int (*check_hw_wp)(target *t, uint32_t *addr); + int (*check_hw_wp)(target *t, target_addr *addr); /* target-defined options */ unsigned target_options;