From b9249fe10490b38fa6c8e990add6b1d05537d939 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sun, 20 Oct 2019 15:55:21 +0200 Subject: [PATCH] adiv5: Activate DP reset sequence, guarded with timeouts. While not working on most STM32, it succeeds on STM32G474. Thanks to Dave Marples --- src/target/adiv5.c | 47 ++++++++++++++++++++++++---------------------- 1 file changed, 25 insertions(+), 22 deletions(-) diff --git a/src/target/adiv5.c b/src/target/adiv5.c index 230fc44..599aa78 100644 --- a/src/target/adiv5.c +++ b/src/target/adiv5.c @@ -30,10 +30,6 @@ #include "cortexm.h" #include "exception.h" -#ifndef DO_RESET_SEQ -#define DO_RESET_SEQ 0 -#endif - /* All this should probably be defined in a dedicated ADIV5 header, so that they * are consistently named and accessible when needed in the codebase. */ @@ -455,26 +451,33 @@ void adiv5_dp_init(ADIv5_DP_t *dp) (ADIV5_DP_CTRLSTAT_CSYSPWRUPACK | ADIV5_DP_CTRLSTAT_CDBGPWRUPACK)) != (ADIV5_DP_CTRLSTAT_CSYSPWRUPACK | ADIV5_DP_CTRLSTAT_CDBGPWRUPACK)); - if(DO_RESET_SEQ) { - /* This AP reset logic is described in ADIv5, but fails to work - * correctly on STM32. CDBGRSTACK is never asserted, and we - * just wait forever. - */ + /* This AP reset logic is described in ADIv5, but fails to work + * correctly on STM32. CDBGRSTACK is never asserted, and we + * just wait forever. This scenario is described in B2.4.1 + * so we have a timeout mechanism in addition to the sensing one. + */ - /* Write request for debug reset */ - adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT, - ctrlstat |= ADIV5_DP_CTRLSTAT_CDBGRSTREQ); - /* Wait for acknowledge */ - while(!((ctrlstat = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT)) & - ADIV5_DP_CTRLSTAT_CDBGRSTACK)); + /* Write request for debug reset */ + adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT, + ctrlstat |= ADIV5_DP_CTRLSTAT_CDBGRSTREQ); - /* Write request for debug reset release */ - adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT, - ctrlstat &= ~ADIV5_DP_CTRLSTAT_CDBGRSTREQ); - /* Wait for acknowledge */ - while(adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT) & - ADIV5_DP_CTRLSTAT_CDBGRSTACK); - } + platform_timeout timeout; + platform_timeout_set(&timeout,200); + /* Wait for acknowledge */ + while ((!platform_timeout_is_expired(&timeout)) && + (!((ctrlstat = adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT)) & ADIV5_DP_CTRLSTAT_CDBGRSTACK)) + ); + + /* Write request for debug reset release */ + adiv5_dp_write(dp, ADIV5_DP_CTRLSTAT, + ctrlstat &= ~ADIV5_DP_CTRLSTAT_CDBGRSTREQ); + + platform_timeout_set(&timeout,200); + /* Wait for acknowledge */ + while ((!platform_timeout_is_expired(&timeout)) && + (adiv5_dp_read(dp, ADIV5_DP_CTRLSTAT) & ADIV5_DP_CTRLSTAT_CDBGRSTACK) + ); + DEBUG("RESET_SEQ %s\n", (platform_timeout_is_expired(&timeout)) ? "failed": "succeeded"); dp->dp_idcode = adiv5_dp_read(dp, ADIV5_DP_IDCODE); if ((dp->dp_idcode & ADIV5_DP_VERSION_MASK) == ADIV5_DPv2) {