From bcf3caf20ed698500cfd151961c705d920213f2a Mon Sep 17 00:00:00 2001 From: Gareth McMullin Date: Wed, 26 Oct 2016 18:27:35 -0700 Subject: [PATCH] cortexa: Disable AHB memory access to avoid issues with L2 cache. --- src/target/cortexa.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/target/cortexa.c b/src/target/cortexa.c index 8dcf1b6..ba27375 100644 --- a/src/target/cortexa.c +++ b/src/target/cortexa.c @@ -359,7 +359,11 @@ bool cortexa_probe(ADIv5_AP_t *apb, uint32_t debug_base) * device specific. */ priv->ahb = adiv5_new_ap(apb->dp, 0); adiv5_ap_ref(priv->ahb); - if ((priv->ahb->idr & 0xfffe00f) == 0x4770001) { + if (false) { + /* FIXME: This used to be if ((priv->ahb->idr & 0xfffe00f) == 0x4770001) + * Accessing memory directly through the AHB is much faster, but can + * result in data inconsistencies if the L2 cache is enabled. + */ /* This is an AHB */ t->mem_read = cortexa_mem_read; t->mem_write = cortexa_mem_write;