From c161521c262d58c10cf42e3f2c80b84d65c4e039 Mon Sep 17 00:00:00 2001
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Sun, 18 Oct 2020 12:32:11 +0200
Subject: [PATCH] cortexm: Designer ARM must be in the default path when
 probing.

---
 src/target/adiv5.c   |  4 +++-
 src/target/cortexm.c | 29 +++++++++++++++++------------
 2 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/src/target/adiv5.c b/src/target/adiv5.c
index 71fef15..b6990c9 100644
--- a/src/target/adiv5.c
+++ b/src/target/adiv5.c
@@ -201,8 +201,10 @@ static const struct {
 	{0x471, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0  ROM",  "(Cortex-M0 ROM)")},
 	{0x490, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 GIC", "(Generic Interrupt Controller)")},
 	{0x4c0, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M0+ ROM",  "(Cortex-M0+ ROM)")},
+	{0x4c3, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 ROM",  "(Cortex-M3 ROM)")},
 	{0x4c4, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M4 ROM",  "(Cortex-M4 ROM)")},
-	{0x4c7, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 PPB",  "(Private Peripheral Bus ROM Table)")},
+	{0x4c7, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 PPB",  "(Cortex-M7 Private Peripheral Bus ROM Table)")},
+	{0x4c8, 0x00, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 ROM",  "(Cortex-M7 ROM)")},
 	{0x906, 0x14, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight CTI",  "(Cross Trigger)")},
 	{0x907, 0x21, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight ETB",  "(Trace Buffer)")},
 	{0x908, 0x12, 0,      aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight CSTF", "(Trace Funnel)")},
diff --git a/src/target/cortexm.c b/src/target/cortexm.c
index 274edf6..e523141 100644
--- a/src/target/cortexm.c
+++ b/src/target/cortexm.c
@@ -409,12 +409,6 @@ bool cortexm_probe(ADIv5_AP_t *ap)
 		PROBE(samd_probe);
 		PROBE(samx5x_probe);
 		break;
-	case AP_DESIGNER_ARM:
-		if (ap->ap_partno == 0x4c3)  /* Care for STM32F1 clones */
-			PROBE(stm32f1_probe);
-		PROBE(sam3x_probe);
-		PROBE(lpc11xx_probe); /* LPC24C11 */
-		break;
 	case AP_DESIGNER_ENERGY_MICRO:
 		PROBE(efm32_probe);
 		break;
@@ -425,16 +419,27 @@ bool cortexm_probe(ADIv5_AP_t *ap)
 		PROBE(lpc11xx_probe); /* LPC845 */
 		break;
 	default:
+		if (ap->ap_designer != AP_DESIGNER_ARM) {
+			/* Report unexpected designers */
 #if PC_HOSTED == 0
-        gdb_outf("Please report Designer %3x and Partno %3x and the probed "
-				 "device\n", ap->ap_designer, ap->ap_partno);
+				gdb_outf("Please report Designer %3x and Partno %3x and the "
+						 "probed device\n", ap->ap_designer, ap->ap_partno);
 #else
-		DEBUG_WARN("Please report Designer %3x and Partno %3x and the probed "
-				 "device\n", ap->ap_designer, ap->ap_partno);
+				DEBUG_WARN("Please report Designer %3x and Partno %3x and the "
+						   "probed device\n", ap->ap_designer, ap->ap_partno);
 #endif
-		PROBE(lpc11xx_probe); /* Let's get feedback if LPC11 is also Specular*/
+		}
+		if (ap->ap_partno == 0x4c3)  /* Cortex-M3 ROM */
+			PROBE(stm32f1_probe); /* Care for STM32F1 clones */
+		else if (ap->ap_partno == 0x471)  { /* Cortex-M0 ROM */
+			PROBE(lpc11xx_probe); /* LPC24C11 */
+			PROBE(lpc43xx_probe);
+		}
+		else if (ap->ap_partno == 0x4c4) /* Cortex-M4 ROM */
+			PROBE(lpc43xx_probe);
+		/* Info on PIDR of these parts wanted! */
+		PROBE(sam3x_probe);
 		PROBE(lpc15xx_probe);
-		PROBE(lpc43xx_probe);
 		PROBE(lmi_probe);
 		PROBE(ke04_probe);
 		PROBE(lpc17xx_probe);