From c456fc7f6122ec9d0fff891b5b79f4a0aded63f7 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 10 Mar 2020 16:04:25 +0100 Subject: [PATCH] adiv5: Store AP designer and partno in the AP structure. --- src/target/adiv5.c | 15 ++++++++++----- src/target/adiv5.h | 2 ++ 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/src/target/adiv5.c b/src/target/adiv5.c index ec5cead..6200e5a 100644 --- a/src/target/adiv5.c +++ b/src/target/adiv5.c @@ -433,8 +433,10 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion, /* ROM table */ if (cid_class == cidc_romtab) { + uint16_t designer = ((pidr >> 24) & 0xf00) | ((pidr >> 12) & 0x7f); + uint16_t partno = pidr & 0xfff; +#if defined(ENABLE_DEBUG) && defined(PLATFORM_HAS_DEBUG) /* Check SYSMEM bit */ -#if defined(ENABLE_DEBUG) uint32_t memtype = adiv5_mem_read32(ap, addr | ADIV5_ROM_MEMTYPE) & ADIV5_ROM_MEMTYPE_SYSMEM; @@ -442,11 +444,14 @@ static bool adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion, DEBUG_WARN("Fault reading ROM table entry\n"); } - DEBUG_INFO("ROM: Table BASE=0x%" PRIx32 " SYSMEM=0x%" PRIx32 - ", PIDR 0x%02" PRIx32 "%08" PRIx32 "\n", addr, - memtype, (uint32_t)(pidr >> 32), (uint32_t)pidr); + DEBUG_INFO("ROM: Table BASE=0x%" PRIx32 " SYSMEM=0x%" PRIx32 ", designer %3" + PRIx32 " Partno %3" PRIx32 "\n", addr, memtype, designer, + partno); #endif - + if (recursion == 0) { + ap->ap_designer = designer; + ap->ap_partno = partno; + } for (int i = 0; i < 960; i++) { adiv5_dp_error(ap->dp); uint32_t entry = adiv5_mem_read32(ap, addr + i*4); diff --git a/src/target/adiv5.h b/src/target/adiv5.h index 68e370b..8ba602f 100644 --- a/src/target/adiv5.h +++ b/src/target/adiv5.h @@ -183,6 +183,8 @@ struct ADIv5_AP_s { uint32_t csw; uint32_t ap_cortexm_demcr; /* Copy of demcr when starting */ uint32_t ap_storage; /* E.g to hold STM32F7 initial DBGMCU_CR value.*/ + uint16_t ap_designer; + uint16_t ap_partno; }; #if PC_HOSTED == 0