From cdd07544d5df183520d23ef41420ae02c78aac2e Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sat, 17 Oct 2020 16:24:19 +0200 Subject: [PATCH] Cortexm: Allow pure debug on devices not yet handled for flashing - Recognize STM32L552 and MIMXRT10XX - Fix another PIDR - Fix bad debug print string. --- src/platforms/hosted/dap.c | 2 +- src/target/adiv5.c | 2 +- src/target/cortexm.c | 10 ++++++++++ 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/platforms/hosted/dap.c b/src/platforms/hosted/dap.c index 03844d1..73bf3c0 100644 --- a/src/platforms/hosted/dap.c +++ b/src/platforms/hosted/dap.c @@ -397,7 +397,7 @@ unsigned int dap_read_block(ADIv5_AP_t *ap, void *dest, uint32_t src, dbg_dap_cmd(buf, 1023, 5 + 1); unsigned int transferred = buf[0] + (buf[1] << 8); if (buf[2] >= DAP_TRANSFER_FAULT) { - DEBUG_WARN("dap_read_block @ %08 "PRIx32 " fault -> line reset\n", src); + DEBUG_WARN("dap_read_block @ %08" PRIx32 " fault -> line reset\n", src); dap_line_reset(); } if (sz != transferred) { diff --git a/src/target/adiv5.c b/src/target/adiv5.c index 0577788..71fef15 100644 --- a/src/target/adiv5.c +++ b/src/target/adiv5.c @@ -218,7 +218,7 @@ static const struct { {0x924, 0x13, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M3 ETM", "(Embedded Trace)")}, {0x925, 0x13, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M4 ETM", "(Embedded Trace)")}, {0x930, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-R4 ETM", "(Embedded Trace)")}, - {0x932, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight MTB-M0+", "(Simple Execution Trace)")}, + {0x932, 0x31, 0x0a31, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight MTB-M0+", "(Simple Execution Trace)")}, {0x941, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight TPIU-Lite", "(Trace Port Interface Unit)")}, {0x950, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight Component", "(unidentified Cortex-A9 component)")}, {0x955, 0x00, 0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight Component", "(unidentified Cortex-A5 component)")}, diff --git a/src/target/cortexm.c b/src/target/cortexm.c index f2bf525..274edf6 100644 --- a/src/target/cortexm.c +++ b/src/target/cortexm.c @@ -379,6 +379,10 @@ bool cortexm_probe(ADIv5_AP_t *ap) switch (ap->ap_designer) { case AP_DESIGNER_FREESCALE: PROBE(kinetis_probe); + if (ap->ap_partno == 0x88c) { + t->driver = "MIMXRT10xx(no flash)"; + target_halt_resume(t, 0); + } break; case AP_DESIGNER_STM: PROBE(stm32f1_probe); @@ -386,6 +390,10 @@ bool cortexm_probe(ADIv5_AP_t *ap) PROBE(stm32h7_probe); PROBE(stm32l0_probe); PROBE(stm32l4_probe); + if (ap->ap_partno == 0x472) { + t->driver = "STM32L552(no flash)"; + target_halt_resume(t, 0); + } break; case AP_DESIGNER_CYPRESS: DEBUG_WARN("Unhandled Cypress device\n"); @@ -432,6 +440,8 @@ bool cortexm_probe(ADIv5_AP_t *ap) PROBE(lpc17xx_probe); } #undef PROBE + /* Restart the CortexM we stopped for Romtable scan. Allow pure debug.*/ + target_halt_resume(t, 0); return true; }