From d6c1d8a1cc29abb3851a35af0868e8f097600f4c Mon Sep 17 00:00:00 2001 From: dragonmux Date: Tue, 9 Aug 2022 22:11:43 +0100 Subject: [PATCH] stm32g0: Made the flash write routine a little more understandable --- src/target/stm32g0.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/target/stm32g0.c b/src/target/stm32g0.c index df7b6b8..c1aafb7 100644 --- a/src/target/stm32g0.c +++ b/src/target/stm32g0.c @@ -407,7 +407,7 @@ static int stm32g0_flash_write(target_flash_s *f, target_addr dest, const void * target *const t = f->t; stm32g0_priv_s *ps = (stm32g0_priv_s *)t->target_storage; - if ((dest >= (target_addr)FLASH_OTP_START) && !ps->irreversible_enabled) { + if (dest >= FLASH_OTP_START && !ps->irreversible_enabled) { tc_printf(t, "Irreversible operations disabled\n"); stm32g0_flash_op_finish(t); return -1; @@ -418,25 +418,25 @@ static int stm32g0_flash_write(target_flash_s *f, target_addr dest, const void * target_mem_write32(t, FLASH_CR, FLASH_CR_PG); target_mem_write(t, dest, src, len); /* Wait for completion or an error */ - uint32_t flash_sr; - do { - flash_sr = target_mem_read32(t, FLASH_SR); + uint32_t status = FLASH_SR_BSY_MASK; + while (status & FLASH_SR_BSY_MASK) { + status = target_mem_read32(t, FLASH_SR); if (target_check_error(t)) { DEBUG_WARN("stm32g0 flash write: comm error\n"); stm32g0_flash_op_finish(t); return -1; } - } while (flash_sr & FLASH_SR_BSY_MASK); + } - if (flash_sr & FLASH_SR_ERROR_MASK) { - DEBUG_WARN("stm32g0 flash write error: sr 0x%" PRIx32 "\n", flash_sr); + if (status & FLASH_SR_ERROR_MASK) { + DEBUG_WARN("stm32g0 flash write error: sr 0x%" PRIx32 "\n", status); stm32g0_flash_op_finish(t); return -1; } - if ((dest == (target_addr)FLASH_START) && target_mem_read32(t, FLASH_START) != 0xFFFFFFFF) { - uint32_t flash_acr = target_mem_read32(t, FLASH_ACR); - flash_acr &= ~(uint32_t)FLASH_ACR_EMPTY; - target_mem_write32(t, FLASH_ACR, flash_acr); + + if (dest == FLASH_START && target_mem_read32(t, FLASH_START) != 0xFFFFFFFF) { + const uint32_t acr = target_mem_read32(t, FLASH_ACR) & ~FLASH_ACR_EMPTY; + target_mem_write32(t, FLASH_ACR, acr); } stm32g0_flash_op_finish(t);