diff --git a/UsingSWO b/UsingSWO index e582df5..36517ea 100644 --- a/UsingSWO +++ b/UsingSWO @@ -25,13 +25,13 @@ the it is a pretty long run before it becomes a problem). Note that the baudrate equation means there are only certain speeds available. The highest half dozen are; - -1 4.50 Mbps -2 2.25 Mbps -3 1.50 Mbps -4 1.125 Mbps -5 0.900 Mbps -6 0.750 Mbps +SWO uses USART1(stlink) USART2(swlink) +1 4.50 Mbps 2.25 Mbps +2 2.25 Mbps 1.125 Mbps +3 1.50 Mbps 0.75 Mbps +4 1.125 Mbps 0.5635 Mbps +5 0.900 Mbps 0.45 Mbps +6 0.750 Mbps 0.375 Mbps ...the USART will cope with some timing slip, but it's advisible to stay as close to these values as you can. As the speed comes down the spread between @@ -50,13 +50,14 @@ An example for a STM32F103 for the UART (NRZ) data format that we use; AFIO->MAPR |= (2 << 24); // Disable JTAG to release TRACESWO DBGMCU->CR |= DBGMCU_CR_TRACE_IOEN; // Enable IO trace pins - *((volatile unsigned *)(0xE0040010)) = 31; // Output bits at 72000000/(31+1)=2.25MHz. - *((volatile unsigned *)(0xE00400F0)) = 2; // Use Async mode (1 for RZ/Manchester) - *((volatile unsigned *)(0xE0040304)) = 0; // Disable formatter + TPI->ACPR = 31; // Output bits at 72000000/(31+1)=2.25MHz. + TPI->SPPR = 2; // Use Async mode (1 for RZ/Manchester) + TPI-FFCR = 0; // Disable formatter /* Configure instrumentation trace macroblock */ ITM->LAR = 0xC5ACCE55; - ITM->TCR = 0x00010005; + ITM->TCR = 1 << ITM_TCR_TraceBusID_Pos | ITM_TCR_SYNCENA_Msk | + ITM_TCR_ITMENA_Msk; ITM->TER = 0xFFFFFFFF; // Enable all stimulus ports Code for the STM32L476 might look like: @@ -234,7 +235,7 @@ can pick this up. Success has been had with CP2102 dongles at up to 921600 baud. To use this mode just connect SWO to the RX pin of your dongle, and start -swolisten with parmeters representing the speed and port. An example; +swolisten with parameters representing the speed and port. An example; >./swolisten -p /dev/cu.SLAB_USBtoUART -v -b swo/ -s 921600 @@ -251,4 +252,4 @@ Further information SWO is a wide field. Read e.g. the blogs around SWD on http://shadetail.com/blog/swo-starting-the-steroids/ An open source program suite for SWO under active development is -https://github.com/mubes/orbuculum \ No newline at end of file +https://github.com/mubes/orbuculum diff --git a/src/platforms/swlink/Makefile.inc b/src/platforms/swlink/Makefile.inc index b7b6c1b..19941ab 100644 --- a/src/platforms/swlink/Makefile.inc +++ b/src/platforms/swlink/Makefile.inc @@ -26,6 +26,7 @@ SRC += cdcacm.c \ serialno.c \ timing.c \ timing_stm32.c \ + traceswoasync.c \ platform_common.c \ all: blackmagic.bin blackmagic_dfu.bin blackmagic_dfu.hex dfu_upgrade.bin dfu_upgrade.hex diff --git a/src/platforms/swlink/README.md b/src/platforms/swlink/README.md new file mode 100644 index 0000000..7085662 --- /dev/null +++ b/src/platforms/swlink/README.md @@ -0,0 +1,72 @@ +# Blackmagic for STM8S Discovery and STM32F103 Minimum System Development Board + +## External connections: + +| Function | PIN | STM8S-DISCO | BLUEPILL | +| ----------- | ----- | ----------- | ----------- | +| JTMS/SWDIO | PA13 | CN5/5 | P2/2 | +| JTCK/SWCLK | PA14 | CN5/4 | P2/3 | +| JTDI | PA15 | CN5/6 | P4/11 (38) | +| JTDO | PB3 | CN5/3 | P4/10 (39) | +| SRST | PB4 | CN5/8 | P4/9 (40) | +| UART1_TX | PB6 | CN7/4 | P4/7 (42) | +| UART1_RX | PB7 | CN7/2 | P4/6 (43) | +| SWO/RX2 | PA3 | NA(*1) | P3/7 (13) | + +*1: Wire JTDO/PB3 (U2/39) to USART2_RX/PA3 (U2/13) to expose SWO for Stlink +on STM8S-Disco on CN5/3 + +### Force Bootloader Entry: + STM8S Discovery: Jumper CN7/4 to CN7/3 to read PB6 low. + Bluepill: Jumper Boot1 to '1' to read PB2 high. + +### References: +[STM8S UM0817 User manual + ](https://www.st.com/resource/en/user_manual/cd00250600.pdf) + +[Blue Pill Schematics 1 + ](https://jeelabs.org/img/2016/STM32F103C8T6-DEV-BOARD-SCH.pdf) : + Use first number! + +[Blue Pill Schematics 2 + ](https://wiki.stm32duino.com/images/a/ae/Bluepillpinout.gif) : + Use second number! + +Distinguish boards by checking the SWIM_IN connection PB9/PB10 seen on +STM8S Discovery. + +## STM8S Discovery + +The board is a ST-Link V1 Board, but with access to JTAG pins accessible +on CN5. This allows easy reprogramming and reuse of the JTAG header. +Programmatical it seems indistinguishable from a e.g. STM32VL +Discovery. So here a variant that uses CN5 for JTAG/SWD and CN7 for +UART. + +Force Bootloader entry is done with shorting CN7 Pin3/4 so PB6 read low while +pulled up momentary by PB6. As PB6 is USBUART TX, this pin is idle +high. Setting the jumper while BMP is running means shorting the GPIO with +output high to ground. Do not do that for extended periods. Un- and repower +soon after setting the jump. Best is to short only when unplugged. + +Reuse SWIM Pins for Uart (USART1) + RX: CN7 Pin2 ->SWIM_IN (PB7)/USART1_RX / SWIM_IN(PB9) + TX: CN7 Pin4 -> SWIM_RST_IN(PB6)/USART1_TX + +## STM32F103 Minimum System Development Board (aka Blue Pill) + +This board has the SWD pins of the onboard F103 accessible on one side. +Reuse these pins. There are also jumpers for BOOT0 and BOOT1(PB2). Reuse +Boot1 as "Force Bootloader entry" jumpered high when booting. Boot1 +has 100 k Ohm between MCU and header pin and can not be used as output. + +All other port pins are have header access with headers not yet soldered. + +This platform can be used for any STM32F103x[8|B] board when JTAG/SWD are +accessible, with the LED depending on actual board layout routed to some +wrong pin and force boot not working. + +## Other STM32F103x[8|B] boards +If the needed JTAG connections are accessible, you can use this swlink variant. +Depending on board layout, LED and force bootloader entry may be routed to +wrong pins. diff --git a/src/platforms/swlink/Readme b/src/platforms/swlink/Readme deleted file mode 100644 index b6a442e..0000000 --- a/src/platforms/swlink/Readme +++ /dev/null @@ -1,49 +0,0 @@ -Blackmagic for STM8S Discovery and STM32F103 Minimum System Development Board -============================================================================= - -* External connections: - -Function PIN STM8S-DISCO BLUPILL -JTMS/SWDIO PA13 CN5/5 P2/2 -TTCK/SWCLK PA14 CN5/4 P2/3 -JTDI PA15 CN5/6 P4/11 (38) -JTDO PB3 CN5/3 P4/10 (39) -SRST PB4 CN5/8 P4/9 (40) - -UART1_TX PB6 CN7/4 P4/7 (42) -UART1_RX PB7 CN7/2 P4/6 (43) - -References: -https://www.st.com/resource/en/user_manual/cd00250600.pdf -Blue Pill: -https://jeelabs.org/img/2016/STM32F103C8T6-DEV-BOARD-SCH.pdf (first number) -https://wiki.stm32duino.com/images/a/ae/Bluepillpinout.gif (second number) - -* STM8S Discovery - -The board is a ST-Link V1 Board, but with access to JTAG pins accessible -on CN5. This allows easy reprogramming and reuse of the JTAG header. -Programmatical it seems indistinguishable from a e.g. STM32VL -Discovery. So here a variant that uses CN5 for JTAG/SWD and CN7 for -UART. - -Force Bootloader entry is done with shorting CN7 Pin3/4 so PB6 read low while -pulled up momentary by PB6. - -Reuse SWIM Pins for Uart (USART1) -RX: CN7 Pin2 ->SWIM_IN (PB7)/USART1_RX / SWIM_IN(PB9) -TX: CN7 Pin4 -> SWIM_RST_IN(PB6)/USART1_TX - -* STM32F103 Minimum System Development Board (aka Blue Pill) - -This board has the SWD pins of the onboard F103 accessible on one side. -Reuse these pins. There are also jumpers for BOOT0 and BOOT1(PB2). Reuse -Boot1 as "Force Bootloader entry" jumpered high when connecting to USB. Boot1 -has 100 k Ohm between MCU and header pin and can not be used as SRST. - -All other port pins are have header access with headers not yet soldered. -JTAG TDO: PB3 -JTAG TDI: PA15 -SWD SWO: PA10 (use Uart pin as on normal STLINK) - -Distinguish boards by checking the SWIM_IN connection PB9/PB10 diff --git a/src/platforms/swlink/platform.h b/src/platforms/swlink/platform.h index 52df074..bbccac9 100644 --- a/src/platforms/swlink/platform.h +++ b/src/platforms/swlink/platform.h @@ -62,6 +62,9 @@ #define LED_PORT_UART GPIOC #define LED_UART GPIO14 +#define PLATFORM_HAS_TRACESWO 1 +#define NUM_TRACE_PACKETS (128) /* This is an 8K buffer */ + # define SWD_CR GPIO_CRH(SWDIO_PORT) # define SWD_CR_MULT (1 << ((13 - 8) << 2)) @@ -97,7 +100,7 @@ #define IRQ_PRI_USBUSART (1 << 4) #define IRQ_PRI_USBUSART_TIM (3 << 4) #define IRQ_PRI_USB_VBUS (14 << 4) -#define IRQ_PRI_TRACE (0 << 4) +#define IRQ_PRI_SWO_DMA (0 << 4) #define USBUSART USART1 #define USBUSART_CR1 USART1_CR1 @@ -126,6 +129,21 @@ int usbuart_debug_write(const char *buf, size_t len); # define DEBUG(...) #endif +/* On F103, only USART1 is on AHB2 and can reach 4.5 MBaud at 72 MHz. + * USART1 is already used. sp maximum speed is 2.25 MBaud. */ +#define SWO_UART USART2 +#define SWO_UART_DR USART2_DR +#define SWO_UART_CLK RCC_USART2 +#define SWO_UART_PORT GPIOA +#define SWO_UART_RX_PIN GPIO3 + +/* This DMA channel is set by the USART in use */ +#define SWO_DMA_BUS DMA1 +#define SWO_DMA_CLK RCC_DMA1 +#define SWO_DMA_CHAN DMA_CHANNEL6 +#define SWO_DMA_IRQ NVIC_DMA1_CHANNEL6_IRQ +#define SWO_DMA_ISR(x) dma1_channel6_isr(x) + #define LED_PORT GPIOC #define LED_IDLE_RUN GPIO15 #define SET_RUN_STATE(state)