From e3fd12ebc651a031bc5feb9bc3f1d33a0e3d0930 Mon Sep 17 00:00:00 2001
From: mean <fixounet@free.fr>
Date: Thu, 3 Dec 2020 07:30:24 +0100
Subject: [PATCH] gd32f1/f3 detection and ram/flash autoset

---
 src/target/adiv5.h           |  3 ++-
 src/target/cortexm.c         |  3 +++
 src/target/stm32f1.c         | 32 ++++++++++++++++++++++++++++++++
 src/target/target_internal.h |  1 +
 4 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/src/target/adiv5.h b/src/target/adiv5.h
index 63e21f6..38c1ccc 100644
--- a/src/target/adiv5.h
+++ b/src/target/adiv5.h
@@ -97,8 +97,9 @@
 #define AP_DESIGNER_ARM          0x43b
 /*LPC845 with designer 501. Strange!? */
 #define AP_DESIGNER_SPECULAR     0x501
+#define AP_DESIGNER_CS           0x555
 #define AP_DESIGNER_ENERGY_MICRO 0x673
-#define AP_DESIGNER_CS		 0x555
+#define AP_DESIGNER_GIGADEVICE   0x751
 
 /* AP Control and Status Word (CSW) */
 #define ADIV5_AP_CSW_DBGSWENABLE	(1u << 31)
diff --git a/src/target/cortexm.c b/src/target/cortexm.c
index b8982d0..f717073 100644
--- a/src/target/cortexm.c
+++ b/src/target/cortexm.c
@@ -390,6 +390,9 @@ bool cortexm_probe(ADIv5_AP_t *ap)
 	case AP_DESIGNER_CS:
 		PROBE(stm32f1_probe);
 		break;
+	case AP_DESIGNER_GIGADEVICE:
+		PROBE(gd32f1_probe);
+		break;
 	case AP_DESIGNER_STM:
 		PROBE(stm32f1_probe);
 		PROBE(stm32f4_probe);
diff --git a/src/target/stm32f1.c b/src/target/stm32f1.c
index 7285494..53c347b 100644
--- a/src/target/stm32f1.c
+++ b/src/target/stm32f1.c
@@ -116,6 +116,38 @@ static void stm32f1_add_flash(target *t,
 	target_add_flash(t, f);
 }
 
+/**
+    \brief identify the correct gd32 f1/f3 chip
+    GD32 : STM32 compatible chip
+*/
+bool gd32f1_probe(target *t)
+{
+	uint16_t stored_idcode = t->idcode;
+	// M3 & M4 & riscV only afaik
+	t->idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff;
+	uint32_t signature= target_mem_read32(t, FLASHSIZE);
+	uint32_t flashSize=signature & 0xFFFF;
+	uint32_t ramSize=signature >>16 ;
+	switch(t->idcode) {
+	case 0x414:  /* Gigadevice gd32f303 */
+		t->driver = "GD32F3";
+		break;
+	case 0x410:  /* Gigadevice gd32f103 */
+        t->driver = "GD32F1";
+		break;
+	default:
+        t->idcode = stored_idcode;
+		return false;
+	}
+	target_add_ram(t, 0x20000000, ramSize*1024);
+	stm32f1_add_flash(t, 0x8000000, flashSize*1024, 0x400);
+	target_add_commands(t, stm32f1_cmd_list, t->driver);
+	return true;
+}
+/**
+    \brief identify the stm32f1 chip
+*/
+
 bool stm32f1_probe(target *t)
 {
 	uint16_t stored_idcode = t->idcode;
diff --git a/src/target/target_internal.h b/src/target/target_internal.h
index 58475bc..7299ee8 100644
--- a/src/target/target_internal.h
+++ b/src/target/target_internal.h
@@ -169,6 +169,7 @@ int tc_system(target *t, target_addr cmd, size_t cmdlen);
 /* Probe for various targets.
  * Actual functions implemented in their respective drivers.
  */
+bool gd32f1_probe(target *t);
 bool stm32f1_probe(target *t);
 bool stm32f4_probe(target *t);
 bool stm32h7_probe(target *t);