From a025c9a7bd00b78000d5bbda2c12b0087e0b61d1 Mon Sep 17 00:00:00 2001
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Fri, 26 Mar 2021 15:28:08 +0100
Subject: [PATCH 1/2] Revert "stm32f1: On ST parts there is no need to read
 IDCODE again."

Romtable partno is not unique for devices, e.g. in STM32F0
This reverts commit f89b07d892c6034ea68494a72e047b2c437754f7.
---
 src/target/stm32f1.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/target/stm32f1.c b/src/target/stm32f1.c
index fb2d0af..a0ade73 100644
--- a/src/target/stm32f1.c
+++ b/src/target/stm32f1.c
@@ -155,6 +155,11 @@ bool gd32f1_probe(target *t)
 
 bool stm32f1_probe(target *t)
 {
+	uint16_t stored_idcode = t->idcode;
+	if ((t->cpuid & CPUID_PARTNO_MASK) == CORTEX_M0)
+		t->idcode = target_mem_read32(t, DBGMCU_IDCODE_F0) & 0xfff;
+	else
+		t->idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff;
 	size_t flash_size;
 	size_t block_size = 0x400;
 	switch(t->idcode) {
@@ -227,6 +232,7 @@ bool stm32f1_probe(target *t)
 		block_size = 0x800;
 		break;
 	default:     /* NONE */
+		t->idcode = stored_idcode;
 		return false;
 	}
 

From 58f153e12b9d0c97200c8b039527ece4fa7bf6d4 Mon Sep 17 00:00:00 2001
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Fri, 26 Mar 2021 17:43:11 +0100
Subject: [PATCH 2/2] cortexm: Always halt and release reset before romtable
 scan

Only release from halt once after romtable scan
Should fix #836.
---
 src/target/adiv5.c   | 17 +++++++----------
 src/target/cortexm.c |  2 +-
 2 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/src/target/adiv5.c b/src/target/adiv5.c
index 2826774..57a6456 100644
--- a/src/target/adiv5.c
+++ b/src/target/adiv5.c
@@ -321,6 +321,9 @@ uint64_t adiv5_ap_read_pidr(ADIv5_AP_t *ap, uint32_t addr)
  * - fails reading outside SYSROM when halted from WFI and
  *   DBGMCU_CR not set.
  *
+ * E.g. Stm32F0
+ * - fails reading DBGMCU when under reset
+ *
  * Keep a copy of DEMCR at startup to restore with exit, to
  * not interrupt tracing initiated by the CPU.
  */
@@ -411,17 +414,8 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr, int recursion,
 	if (addr == 0) /* No rom table on this AP */
 		return;
 	uint32_t cidr = adiv5_ap_read_id(ap, addr + CIDR0_OFFSET);
-	if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE) {
-		/* Maybe caused by a not halted CortexM */
-		if ((ap->idr & 0xf) == ARM_AP_TYPE_AHB) {
-			if (!cortexm_prepare(ap))
-				return; /* Halting failed! */
-			/* CPU now halted, read cidr again. */
-			cidr = adiv5_ap_read_id(ap, addr + CIDR0_OFFSET);
-			if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE)
+	if ((cidr & ~CID_CLASS_MASK) != CID_PREAMBLE)
 				return;
-		}
-	}
 #if defined(ENABLE_DEBUG)
 	char indent[recursion + 1];
 
@@ -755,6 +749,9 @@ void adiv5_dp_init(ADIv5_DP_t *dp)
 		extern void efm32_aap_probe(ADIv5_AP_t *);
 		efm32_aap_probe(ap);
 
+		/* Halt the device and release from reset if reset is active!*/
+		if (!ap->apsel && ((ap->idr & 0xf) == ARM_AP_TYPE_AHB))
+			cortexm_prepare(ap);
 		/* Should probe further here to make sure it's a valid target.
 		 * AP should be unref'd if not valid.
 		 */
diff --git a/src/target/cortexm.c b/src/target/cortexm.c
index 99ae41f..28bc225 100644
--- a/src/target/cortexm.c
+++ b/src/target/cortexm.c
@@ -377,7 +377,7 @@ bool cortexm_probe(ADIv5_AP_t *ap)
 		target_check_error(t);
 	}
 #define PROBE(x) \
-	do { if ((x)(t)) {target_halt_resume(t, 0); return true;} else target_check_error(t); } while (0)
+	do { if ((x)(t)) {return true;} else target_check_error(t); } while (0)
 
 	switch (ap->ap_designer) {
 	case AP_DESIGNER_FREESCALE: